[mirror_ubuntu-jammy-kernel.git] / drivers / watchdog / qcom-wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 */
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/of_device.h>

enum wdt_reg {
	WDT_RST,
	WDT_EN,
	WDT_STS,
	WDT_BARK_TIME,
	WDT_BITE_TIME,
};

#define QCOM_WDT_ENABLE		BIT(0)

static const u32 reg_offset_data_apcs_tmr[] = {
	[WDT_RST] = 0x38,
	[WDT_EN] = 0x40,
	[WDT_STS] = 0x44,
	[WDT_BARK_TIME] = 0x4C,
	[WDT_BITE_TIME] = 0x5C,
};

static const u32 reg_offset_data_kpss[] = {
	[WDT_RST] = 0x4,
	[WDT_EN] = 0x8,
	[WDT_STS] = 0xC,
	[WDT_BARK_TIME] = 0x10,
	[WDT_BITE_TIME] = 0x14,
};

struct qcom_wdt_match_data {
	const u32 *offset;
	bool pretimeout;
};

struct qcom_wdt {
	struct watchdog_device	wdd;
	unsigned long		rate;
	void __iomem		*base;
	const u32		*layout;
};

static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
{
	return wdt->base + wdt->layout[reg];
}

static inline
struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
{
	return container_of(wdd, struct qcom_wdt, wdd);
}

static irqreturn_t qcom_wdt_isr(int irq, void *arg)
{
	struct watchdog_device *wdd = arg;

	watchdog_notify_pretimeout(wdd);

	return IRQ_HANDLED;
}

static int qcom_wdt_start(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	unsigned int bark = wdd->timeout - wdd->pretimeout;

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_stop(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(0, wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_ping(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(1, wdt_addr(wdt, WDT_RST));
	return 0;
}

static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
				unsigned int timeout)
{
	wdd->timeout = timeout;
	return qcom_wdt_start(wdd);
}

static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
				   unsigned int timeout)
{
	wdd->pretimeout = timeout;
	return qcom_wdt_start(wdd);
}

static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
			    void *data)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	u32 timeout;

	/*
	 * Trigger watchdog bite:
	 *    Setup BITE_TIME to be 128ms, and enable WDT.
	 */
	timeout = 128 * wdt->rate / 1000;

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));

	/*
	 * Actually make sure the above sequence hits hardware before sleeping.
	 */
	wmb();

	mdelay(150);
	return 0;
}

static int qcom_wdt_is_running(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
}

static const struct watchdog_ops qcom_wdt_ops = {
	.start		= qcom_wdt_start,
	.stop		= qcom_wdt_stop,
	.ping		= qcom_wdt_ping,
	.set_timeout	= qcom_wdt_set_timeout,
	.set_pretimeout	= qcom_wdt_set_pretimeout,
	.restart        = qcom_wdt_restart,
	.owner		= THIS_MODULE,
};

static const struct watchdog_info qcom_wdt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT
			| WDIOF_CARDRESET,
	.identity	= KBUILD_MODNAME,
};

static const struct watchdog_info qcom_wdt_pt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT
			| WDIOF_PRETIMEOUT
			| WDIOF_CARDRESET,
	.identity	= KBUILD_MODNAME,
};

static void qcom_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static const struct qcom_wdt_match_data match_data_apcs_tmr = {
	.offset = reg_offset_data_apcs_tmr,
	.pretimeout = false,
};

static const struct qcom_wdt_match_data match_data_kpss = {
	.offset = reg_offset_data_kpss,
	.pretimeout = true,
};

static int qcom_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct qcom_wdt *wdt;
	struct resource *res;
	struct device_node *np = dev->of_node;
	const struct qcom_wdt_match_data *data;
	u32 percpu_offset;
	int irq, ret;
	struct clk *clk;

	data = of_device_get_match_data(dev);
	if (!data) {
		dev_err(dev, "Unsupported QCOM WDT module\n");
		return -ENODEV;
	}

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOMEM;

	/* We use CPU0's DGT for the watchdog */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	res->start += percpu_offset;
	res->end += percpu_offset;

	wdt->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get input clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		dev_err(dev, "failed to setup clock\n");
		return ret;
	}
	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
	if (ret)
		return ret;

	/*
	 * We use the clock rate to calculate the max timeout, so ensure it's
	 * not zero to avoid a divide-by-zero exception.
	 *
	 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	 * that it would bite before a second elapses it's usefulness is
	 * limited.  Bail if this is the case.
	 */
	wdt->rate = clk_get_rate(clk);
	if (wdt->rate == 0 ||
	    wdt->rate > 0x10000000U) {
		dev_err(dev, "invalid clock rate\n");
		return -EINVAL;
	}

	/* check if there is pretimeout support */
	irq = platform_get_irq_optional(pdev, 0);
	if (data->pretimeout && irq > 0) {
		ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
				       "wdt_bark", &wdt->wdd);
		if (ret)
			return ret;

		wdt->wdd.info = &qcom_wdt_pt_info;
		wdt->wdd.pretimeout = 1;
	} else {
		if (irq == -EPROBE_DEFER)
			return -EPROBE_DEFER;

		wdt->wdd.info = &qcom_wdt_info;
	}

	wdt->wdd.ops = &qcom_wdt_ops;
	wdt->wdd.min_timeout = 1;
	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
	wdt->wdd.parent = dev;
	wdt->layout = data->offset;

	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
		wdt->wdd.bootstatus = WDIOF_CARDRESET;

	/*
	 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
	 * default, unless the max timeout is less than 30 seconds, then use
	 * the max instead.
	 */
	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
	watchdog_init_timeout(&wdt->wdd, 0, dev);

	/*
	 * If WDT is already running, call WDT start which
	 * will stop the WDT, set timeouts as bootloader
	 * might use different ones and set running bit
	 * to inform the WDT subsystem to ping the WDT
	 */
	if (qcom_wdt_is_running(&wdt->wdd)) {
		qcom_wdt_start(&wdt->wdd);
		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	}

	ret = devm_watchdog_register_device(dev, &wdt->wdd);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, wdt);
	return 0;
}

static int __maybe_unused qcom_wdt_suspend(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_stop(&wdt->wdd);

	return 0;
}

static int __maybe_unused qcom_wdt_resume(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_start(&wdt->wdd);

	return 0;
}

static const struct dev_pm_ops qcom_wdt_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume)
};

static const struct of_device_id qcom_wdt_of_table[] = {
	{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
	{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
	{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
	{ },
};
MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);

static struct platform_driver qcom_watchdog_driver = {
	.probe	= qcom_wdt_probe,
	.driver	= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= qcom_wdt_of_table,
		.pm		= &qcom_wdt_pm_ops,
	},
};
module_platform_driver(qcom_watchdog_driver);

MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
1094ebe9	2	/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
1094ebe9	3	*/
36375491	4	#include <linux/bits.h>
1094ebe9	5	#include <linux/clk.h>
05e487d9	6	#include <linux/delay.h>
36375491	7	#include <linux/interrupt.h>
1094ebe9 JC	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/watchdog.h>
f0d9d0f4	14	#include <linux/of_device.h>
1094ebe9	15
f0d9d0f4 MM	16	enum wdt_reg {
	17	WDT_RST,
	18	WDT_EN,
	19	WDT_STS,
10073a20	20	WDT_BARK_TIME,
f0d9d0f4 MM	21	WDT_BITE_TIME,
	22	};
	23
36375491	24	#define QCOM_WDT_ENABLE BIT(0)
36375491	25
f0d9d0f4 MM	26	static const u32 reg_offset_data_apcs_tmr[] = {
	27	[WDT_RST] = 0x38,
	28	[WDT_EN] = 0x40,
	29	[WDT_STS] = 0x44,
10073a20	30	[WDT_BARK_TIME] = 0x4C,
f0d9d0f4 MM	31	[WDT_BITE_TIME] = 0x5C,
	32	};
	33
	34	static const u32 reg_offset_data_kpss[] = {
	35	[WDT_RST] = 0x4,
	36	[WDT_EN] = 0x8,
	37	[WDT_STS] = 0xC,
10073a20	38	[WDT_BARK_TIME] = 0x10,
f0d9d0f4 MM	39	[WDT_BITE_TIME] = 0x14,
f0d9d0f4 MM	40	};
1094ebe9	41
000de541 AS	42	struct qcom_wdt_match_data {
	43	const u32 *offset;
	44	bool pretimeout;
	45	};
	46
1094ebe9 JC	47	struct qcom_wdt {
1094ebe9 JC	48	struct watchdog_device wdd;
1094ebe9 JC	49	unsigned long rate;
1094ebe9 JC	50	void __iomem *base;
f0d9d0f4	51	const u32 *layout;
1094ebe9 JC	52	};
1094ebe9 JC	53
f0d9d0f4 MM	54	static void __iomem wdt_addr(struct qcom_wdt wdt, enum wdt_reg reg)
	55	{
	56	return wdt->base + wdt->layout[reg];
	57	}
	58
1094ebe9 JC	59	static inline
	60	struct qcom_wdt to_qcom_wdt(struct watchdog_device wdd)
	61	{
	62	return container_of(wdd, struct qcom_wdt, wdd);
	63	}
	64
36375491 JRO	65	static irqreturn_t qcom_wdt_isr(int irq, void *arg)
	66	{
	67	struct watchdog_device *wdd = arg;
	68
	69	watchdog_notify_pretimeout(wdd);
	70
	71	return IRQ_HANDLED;
	72	}
	73
1094ebe9 JC	74	static int qcom_wdt_start(struct watchdog_device *wdd)
	75	{
	76	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
36375491	77	unsigned int bark = wdd->timeout - wdd->pretimeout;
1094ebe9	78
f0d9d0f4 MM	79	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	80	writel(1, wdt_addr(wdt, WDT_RST));
36375491	81	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4	82	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
a4f3407c	83	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
1094ebe9 JC	84	return 0;
	85	}
	86
	87	static int qcom_wdt_stop(struct watchdog_device *wdd)
	88	{
	89	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	90
f0d9d0f4	91	writel(0, wdt_addr(wdt, WDT_EN));
1094ebe9 JC	92	return 0;
	93	}
	94
	95	static int qcom_wdt_ping(struct watchdog_device *wdd)
	96	{
	97	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	98
f0d9d0f4	99	writel(1, wdt_addr(wdt, WDT_RST));
1094ebe9 JC	100	return 0;
	101	}
	102
	103	static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
	104	unsigned int timeout)
	105	{
	106	wdd->timeout = timeout;
	107	return qcom_wdt_start(wdd);
	108	}
	109
36375491 JRO	110	static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
	111	unsigned int timeout)
	112	{
	113	wdd->pretimeout = timeout;
	114	return qcom_wdt_start(wdd);
	115	}
	116
4d8b229d GR	117	static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
4d8b229d GR	118	void *data)
05e487d9	119	{
80969a68	120	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
05e487d9 JC	121	u32 timeout;
	122
	123	/*
	124	* Trigger watchdog bite:
	125	* Setup BITE_TIME to be 128ms, and enable WDT.
	126	*/
	127	timeout = 128 * wdt->rate / 1000;
	128
f0d9d0f4 MM	129	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	130	writel(1, wdt_addr(wdt, WDT_RST));
10073a20	131	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4	132	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
36375491	133	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
05e487d9 JC	134
	135	/*
	136	* Actually make sure the above sequence hits hardware before sleeping.
	137	*/
	138	wmb();
	139
7948fab2	140	mdelay(150);
80969a68	141	return 0;
05e487d9 JC	142	}
05e487d9 JC	143
8650d0f9 RM	144	static int qcom_wdt_is_running(struct watchdog_device *wdd)
	145	{
	146	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	147
	148	return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
	149	}
	150
80969a68 DR	151	static const struct watchdog_ops qcom_wdt_ops = {
	152	.start = qcom_wdt_start,
	153	.stop = qcom_wdt_stop,
	154	.ping = qcom_wdt_ping,
	155	.set_timeout = qcom_wdt_set_timeout,
36375491	156	.set_pretimeout = qcom_wdt_set_pretimeout,
80969a68 DR	157	.restart = qcom_wdt_restart,
	158	.owner = THIS_MODULE,
	159	};
	160
	161	static const struct watchdog_info qcom_wdt_info = {
	162	.options = WDIOF_KEEPALIVEPING
	163	\| WDIOF_MAGICCLOSE
b6ef36d2 GR	164	\| WDIOF_SETTIMEOUT
b6ef36d2 GR	165	\| WDIOF_CARDRESET,
80969a68 DR	166	.identity = KBUILD_MODNAME,
	167	};
	168
36375491 JRO	169	static const struct watchdog_info qcom_wdt_pt_info = {
	170	.options = WDIOF_KEEPALIVEPING
	171	\| WDIOF_MAGICCLOSE
	172	\| WDIOF_SETTIMEOUT
	173	\| WDIOF_PRETIMEOUT
	174	\| WDIOF_CARDRESET,
	175	.identity = KBUILD_MODNAME,
	176	};
	177
bba07e6e GR	178	static void qcom_clk_disable_unprepare(void *data)
	179	{
	180	clk_disable_unprepare(data);
	181	}
	182
000de541 AS	183	static const struct qcom_wdt_match_data match_data_apcs_tmr = {
	184	.offset = reg_offset_data_apcs_tmr,
	185	.pretimeout = false,
	186	};
	187
	188	static const struct qcom_wdt_match_data match_data_kpss = {
	189	.offset = reg_offset_data_kpss,
	190	.pretimeout = true,
	191	};
	192
1094ebe9 JC	193	static int qcom_wdt_probe(struct platform_device *pdev)
1094ebe9 JC	194	{
bba07e6e	195	struct device *dev = &pdev->dev;
1094ebe9 JC	196	struct qcom_wdt *wdt;
1094ebe9 JC	197	struct resource *res;
bba07e6e	198	struct device_node *np = dev->of_node;
000de541	199	const struct qcom_wdt_match_data *data;
0dfd582e	200	u32 percpu_offset;
36375491	201	int irq, ret;
52a14214	202	struct clk *clk;
1094ebe9	203
000de541 AS	204	data = of_device_get_match_data(dev);
000de541 AS	205	if (!data) {
bba07e6e	206	dev_err(dev, "Unsupported QCOM WDT module\n");
f0d9d0f4 MM	207	return -ENODEV;
	208	}
	209
bba07e6e	210	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
1094ebe9 JC	211	if (!wdt)
	212	return -ENOMEM;
	213
	214	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15210ad1 FE	215	if (!res)
15210ad1 FE	216	return -ENOMEM;
0dfd582e MO	217
	218	/* We use CPU0's DGT for the watchdog */
	219	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	220	percpu_offset = 0;
	221
	222	res->start += percpu_offset;
	223	res->end += percpu_offset;
	224
bba07e6e	225	wdt->base = devm_ioremap_resource(dev, res);
1094ebe9 JC	226	if (IS_ERR(wdt->base))
	227	return PTR_ERR(wdt->base);
	228
52a14214 JRO	229	clk = devm_clk_get(dev, NULL);
52a14214 JRO	230	if (IS_ERR(clk)) {
bba07e6e	231	dev_err(dev, "failed to get input clock\n");
52a14214	232	return PTR_ERR(clk);
1094ebe9 JC	233	}
1094ebe9 JC	234
52a14214	235	ret = clk_prepare_enable(clk);
1094ebe9	236	if (ret) {
bba07e6e	237	dev_err(dev, "failed to setup clock\n");
1094ebe9 JC	238	return ret;
1094ebe9 JC	239	}
52a14214	240	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
bba07e6e GR	241	if (ret)
bba07e6e GR	242	return ret;
1094ebe9 JC	243
	244	/*
	245	* We use the clock rate to calculate the max timeout, so ensure it's
	246	* not zero to avoid a divide-by-zero exception.
	247	*
	248	* WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	249	* that it would bite before a second elapses it's usefulness is
	250	* limited. Bail if this is the case.
	251	*/
52a14214	252	wdt->rate = clk_get_rate(clk);
1094ebe9 JC	253	if (wdt->rate == 0 \|\|
1094ebe9 JC	254	wdt->rate > 0x10000000U) {
bba07e6e GR	255	dev_err(dev, "invalid clock rate\n");
bba07e6e GR	256	return -EINVAL;
1094ebe9 JC	257	}
1094ebe9 JC	258
36375491	259	/* check if there is pretimeout support */
e0b4f4e0	260	irq = platform_get_irq_optional(pdev, 0);
000de541	261	if (data->pretimeout && irq > 0) {
cc9cc794	262	ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
36375491 JRO	263	"wdt_bark", &wdt->wdd);
	264	if (ret)
	265	return ret;
	266
	267	wdt->wdd.info = &qcom_wdt_pt_info;
	268	wdt->wdd.pretimeout = 1;
	269	} else {
	270	if (irq == -EPROBE_DEFER)
	271	return -EPROBE_DEFER;
	272
	273	wdt->wdd.info = &qcom_wdt_info;
	274	}
	275
1094ebe9 JC	276	wdt->wdd.ops = &qcom_wdt_ops;
	277	wdt->wdd.min_timeout = 1;
	278	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
bba07e6e	279	wdt->wdd.parent = dev;
000de541	280	wdt->layout = data->offset;
1094ebe9	281
f06f35c6	282	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
b6ef36d2 GR	283	wdt->wdd.bootstatus = WDIOF_CARDRESET;
b6ef36d2 GR	284
1094ebe9 JC	285	/*
	286	* If 'timeout-sec' unspecified in devicetree, assume a 30 second
	287	* default, unless the max timeout is less than 30 seconds, then use
	288	* the max instead.
	289	*/
	290	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
bba07e6e	291	watchdog_init_timeout(&wdt->wdd, 0, dev);
1094ebe9	292
8650d0f9 RM	293	/*
	294	* If WDT is already running, call WDT start which
	295	* will stop the WDT, set timeouts as bootloader
	296	* might use different ones and set running bit
	297	* to inform the WDT subsystem to ping the WDT
	298	*/
	299	if (qcom_wdt_is_running(&wdt->wdd)) {
	300	qcom_wdt_start(&wdt->wdd);
	301	set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	302	}
	303
bba07e6e	304	ret = devm_watchdog_register_device(dev, &wdt->wdd);
ccbf872a	305	if (ret)
bba07e6e	306	return ret;
1094ebe9 JC	307
	308	platform_set_drvdata(pdev, wdt);
	309	return 0;
1094ebe9 JC	310	}
1094ebe9 JC	311
671cdde3 SPR	312	static int __maybe_unused qcom_wdt_suspend(struct device *dev)
	313	{
	314	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	315
	316	if (watchdog_active(&wdt->wdd))
	317	qcom_wdt_stop(&wdt->wdd);
	318
	319	return 0;
	320	}
	321
	322	static int __maybe_unused qcom_wdt_resume(struct device *dev)
	323	{
	324	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	325
	326	if (watchdog_active(&wdt->wdd))
	327	qcom_wdt_start(&wdt->wdd);
	328
	329	return 0;
	330	}
	331
8442ef6f SPR	332	static const struct dev_pm_ops qcom_wdt_pm_ops = {
	333	SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume)
	334	};
671cdde3	335
1094ebe9	336	static const struct of_device_id qcom_wdt_of_table[] = {
000de541 AS	337	{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
	338	{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
	339	{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
1094ebe9 JC	340	{ },
	341	};
	342	MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
	343
	344	static struct platform_driver qcom_watchdog_driver = {
	345	.probe = qcom_wdt_probe,
1094ebe9 JC	346	.driver = {
	347	.name = KBUILD_MODNAME,
	348	.of_match_table = qcom_wdt_of_table,
671cdde3	349	.pm = &qcom_wdt_pm_ops,
1094ebe9 JC	350	},
	351	};
	352	module_platform_driver(qcom_watchdog_driver);
	353
	354	MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
	355	MODULE_LICENSE("GPL v2");