[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / renesas_wdt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Watchdog driver for Renesas WDT watchdog
 *
 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 * Copyright (C) 2015-17 Renesas Electronics Corporation
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/smp.h>
#include <linux/sys_soc.h>
#include <linux/watchdog.h>

#define RWTCNT		0
#define RWTCSRA		4
#define RWTCSRA_WOVF	BIT(4)
#define RWTCSRA_WRFLG	BIT(5)
#define RWTCSRA_TME	BIT(7)
#define RWTCSRB		8

#define RWDT_DEFAULT_TIMEOUT 60U

/*
 * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
 * divider (12 bits). d is only a factor to fully utilize the WDT counter and
 * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
 */
#define MUL_BY_CLKS_PER_SEC(p, d) \
	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])

/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)

static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

struct rwdt_priv {
	void __iomem *base;
	struct watchdog_device wdev;
	unsigned long clk_rate;
	u8 cks;
};

static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
{
	if (reg == RWTCNT)
		val |= 0x5a5a0000;
	else
		val |= 0xa5a5a500;

	writel_relaxed(val, priv->base + reg);
}

static int rwdt_init_timeout(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);

	return 0;
}

static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
{
	unsigned int delay;

	delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);

	usleep_range(delay, 2 * delay);
}

static int rwdt_start(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	u8 val;

	pm_runtime_get_sync(wdev->parent);

	/* Stop the timer before we modify any register */
	val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
	rwdt_write(priv, val, RWTCSRA);
	/* Delay 2 cycles before setting watchdog counter */
	rwdt_wait_cycles(priv, 2);

	rwdt_init_timeout(wdev);
	rwdt_write(priv, priv->cks, RWTCSRA);
	rwdt_write(priv, 0, RWTCSRB);

	while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
		cpu_relax();

	rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);

	return 0;
}

static int rwdt_stop(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	rwdt_write(priv, priv->cks, RWTCSRA);
	/* Delay 3 cycles before disabling module clock */
	rwdt_wait_cycles(priv, 3);
	pm_runtime_put(wdev->parent);

	return 0;
}

static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	u16 val = readw_relaxed(priv->base + RWTCNT);

	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
}

static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
			void *data)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	rwdt_start(wdev);
	rwdt_write(priv, 0xffff, RWTCNT);
	return 0;
}

static const struct watchdog_info rwdt_ident = {
	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
		WDIOF_CARDRESET,
	.identity = "Renesas WDT Watchdog",
};

static const struct watchdog_ops rwdt_ops = {
	.owner = THIS_MODULE,
	.start = rwdt_start,
	.stop = rwdt_stop,
	.ping = rwdt_init_timeout,
	.get_timeleft = rwdt_get_timeleft,
	.restart = rwdt_restart,
};

#if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
/*
 * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
 */
static const struct soc_device_attribute rwdt_quirks_match[] = {
	{
		.soc_id = "r8a7790",
		.revision = "ES1.*",
		.data = (void *)1,	/* needs single CPU */
	}, {
		.soc_id = "r8a7791",
		.revision = "ES1.*",
		.data = (void *)1,	/* needs single CPU */
	}, {
		.soc_id = "r8a7792",
		.data = (void *)0,	/* needs SMP disabled */
	},
	{ /* sentinel */ }
};

static bool rwdt_blacklisted(struct device *dev)
{
	const struct soc_device_attribute *attr;

	attr = soc_device_match(rwdt_quirks_match);
	if (attr && setup_max_cpus > (uintptr_t)attr->data) {
		dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
			 attr->revision);
		return true;
	}

	return false;
}
#else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
static inline bool rwdt_blacklisted(struct device *dev) { return false; }
#endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */

static int rwdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rwdt_priv *priv;
	struct clk *clk;
	unsigned long clks_per_sec;
	int ret, i;

	if (rwdt_blacklisted(dev))
		return -ENODEV;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	priv->clk_rate = clk_get_rate(clk);
	priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) &
				RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0;
	pm_runtime_put(dev);

	if (!priv->clk_rate) {
		ret = -ENOENT;
		goto out_pm_disable;
	}

	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
		clks_per_sec = priv->clk_rate / clk_divs[i];
		if (clks_per_sec && clks_per_sec < 65536) {
			priv->cks = i;
			break;
		}
	}

	if (i < 0) {
		dev_err(dev, "Can't find suitable clock divider\n");
		ret = -ERANGE;
		goto out_pm_disable;
	}

	priv->wdev.info = &rwdt_ident;
	priv->wdev.ops = &rwdt_ops;
	priv->wdev.parent = dev;
	priv->wdev.min_timeout = 1;
	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);

	platform_set_drvdata(pdev, priv);
	watchdog_set_drvdata(&priv->wdev, priv);
	watchdog_set_nowayout(&priv->wdev, nowayout);
	watchdog_set_restart_priority(&priv->wdev, 0);
	watchdog_stop_on_unregister(&priv->wdev);

	/* This overrides the default timeout only if DT configuration was found */
	watchdog_init_timeout(&priv->wdev, 0, dev);

	ret = watchdog_register_device(&priv->wdev);
	if (ret < 0)
		goto out_pm_disable;

	return 0;

 out_pm_disable:
	pm_runtime_disable(dev);
	return ret;
}

static int rwdt_remove(struct platform_device *pdev)
{
	struct rwdt_priv *priv = platform_get_drvdata(pdev);

	watchdog_unregister_device(&priv->wdev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static int __maybe_unused rwdt_suspend(struct device *dev)
{
	struct rwdt_priv *priv = dev_get_drvdata(dev);

	if (watchdog_active(&priv->wdev))
		rwdt_stop(&priv->wdev);

	return 0;
}

static int __maybe_unused rwdt_resume(struct device *dev)
{
	struct rwdt_priv *priv = dev_get_drvdata(dev);

	if (watchdog_active(&priv->wdev))
		rwdt_start(&priv->wdev);

	return 0;
}

static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);

static const struct of_device_id rwdt_ids[] = {
	{ .compatible = "renesas,rcar-gen2-wdt", },
	{ .compatible = "renesas,rcar-gen3-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rwdt_ids);

static struct platform_driver rwdt_driver = {
	.driver = {
		.name = "renesas_wdt",
		.of_match_table = rwdt_ids,
		.pm = &rwdt_pm_ops,
	},
	.probe = rwdt_probe,
	.remove = rwdt_remove,
};
module_platform_driver(rwdt_driver);

MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
Commit	Line	Data
3bed02a2	1	// SPDX-License-Identifier: GPL-2.0
bd99b68e WS	2	/*
	3	* Watchdog driver for Renesas WDT watchdog
	4	*
1f185596 WS	5	* Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
1f185596 WS	6	* Copyright (C) 2015-17 Renesas Electronics Corporation
bd99b68e WS	7	*/
	8	#include <linux/bitops.h>
	9	#include <linux/clk.h>
b836005b	10	#include <linux/delay.h>
bd99b68e WS	11	#include <linux/io.h>
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/pm_runtime.h>
3fe95e6c FC	17	#include <linux/smp.h>
3fe95e6c FC	18	#include <linux/sys_soc.h>
bd99b68e WS	19	#include <linux/watchdog.h>
	20
	21	#define RWTCNT 0
	22	#define RWTCSRA 4
	23	#define RWTCSRA_WOVF BIT(4)
	24	#define RWTCSRA_WRFLG BIT(5)
	25	#define RWTCSRA_TME BIT(7)
03a196f2	26	#define RWTCSRB 8
bd99b68e WS	27
	28	#define RWDT_DEFAULT_TIMEOUT 60U
	29
82f64cd2 WS	30	/*
82f64cd2 WS	31	* In probe, clk_rate is checked to be not more than 16 bit * biggest clock
03a196f2	32	* divider (12 bits). d is only a factor to fully utilize the WDT counter and
82f64cd2 WS	33	* will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
	34	*/
	35	#define MUL_BY_CLKS_PER_SEC(p, d) \
	36	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
	37
03a196f2	38	/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
82f64cd2 WS	39	#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
82f64cd2 WS	40
03a196f2	41	static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
bd99b68e WS	42
	43	static bool nowayout = WATCHDOG_NOWAYOUT;
	44	module_param(nowayout, bool, 0);
	45	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	46	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	47
	48	struct rwdt_priv {
	49	void __iomem *base;
	50	struct watchdog_device wdev;
82f64cd2	51	unsigned long clk_rate;
bd99b68e WS	52	u8 cks;
	53	};
	54
	55	static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
	56	{
	57	if (reg == RWTCNT)
	58	val \|= 0x5a5a0000;
	59	else
	60	val \|= 0xa5a5a500;
	61
	62	writel_relaxed(val, priv->base + reg);
	63	}
	64
	65	static int rwdt_init_timeout(struct watchdog_device *wdev)
	66	{
	67	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	68
82f64cd2	69	rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
bd99b68e WS	70
	71	return 0;
	72	}
	73
b836005b YS	74	static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
	75	{
	76	unsigned int delay;
	77
	78	delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
	79
	80	usleep_range(delay, 2 * delay);
	81	}
	82
bd99b68e WS	83	static int rwdt_start(struct watchdog_device *wdev)
	84	{
	85	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
e990e127	86	u8 val;
bd99b68e	87
3be42941	88	pm_runtime_get_sync(wdev->parent);
bd99b68e	89
e990e127 WS	90	/* Stop the timer before we modify any register */
	91	val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
	92	rwdt_write(priv, val, RWTCSRA);
b836005b YS	93	/* Delay 2 cycles before setting watchdog counter */
b836005b YS	94	rwdt_wait_cycles(priv, 2);
e990e127	95
bd99b68e	96	rwdt_init_timeout(wdev);
e990e127 WS	97	rwdt_write(priv, priv->cks, RWTCSRA);
e990e127 WS	98	rwdt_write(priv, 0, RWTCSRB);
bd99b68e WS	99
	100	while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
	101	cpu_relax();
	102
	103	rwdt_write(priv, priv->cks \| RWTCSRA_TME, RWTCSRA);
	104
	105	return 0;
	106	}
	107
	108	static int rwdt_stop(struct watchdog_device *wdev)
	109	{
	110	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	111
	112	rwdt_write(priv, priv->cks, RWTCSRA);
b836005b YS	113	/* Delay 3 cycles before disabling module clock */
b836005b YS	114	rwdt_wait_cycles(priv, 3);
3be42941	115	pm_runtime_put(wdev->parent);
bd99b68e WS	116
	117	return 0;
	118	}
	119
	120	static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
	121	{
	122	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	123	u16 val = readw_relaxed(priv->base + RWTCNT);
	124
82f64cd2	125	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
bd99b68e WS	126	}
bd99b68e WS	127
089bcaa8 FC	128	static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
	129	void *data)
	130	{
	131	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	132
	133	rwdt_start(wdev);
	134	rwdt_write(priv, 0xffff, RWTCNT);
	135	return 0;
	136	}
	137
bd99b68e	138	static const struct watchdog_info rwdt_ident = {
fdac6a90 VC	139	.options = WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \|
fdac6a90 VC	140	WDIOF_CARDRESET,
bd99b68e WS	141	.identity = "Renesas WDT Watchdog",
	142	};
	143
	144	static const struct watchdog_ops rwdt_ops = {
	145	.owner = THIS_MODULE,
	146	.start = rwdt_start,
	147	.stop = rwdt_stop,
	148	.ping = rwdt_init_timeout,
	149	.get_timeleft = rwdt_get_timeleft,
089bcaa8	150	.restart = rwdt_restart,
bd99b68e WS	151	};
bd99b68e WS	152
3fe95e6c FC	153	#if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
	154	/*
	155	* Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
	156	*/
	157	static const struct soc_device_attribute rwdt_quirks_match[] = {
	158	{
	159	.soc_id = "r8a7790",
	160	.revision = "ES1.*",
	161	.data = (void )1, / needs single CPU */
	162	}, {
	163	.soc_id = "r8a7791",
665f9442	164	.revision = "ES1.*",
3fe95e6c FC	165	.data = (void )1, / needs single CPU */
	166	}, {
	167	.soc_id = "r8a7792",
3fe95e6c FC	168	.data = (void )0, / needs SMP disabled */
	169	},
	170	{ /* sentinel */ }
	171	};
	172
	173	static bool rwdt_blacklisted(struct device *dev)
	174	{
	175	const struct soc_device_attribute *attr;
	176
	177	attr = soc_device_match(rwdt_quirks_match);
	178	if (attr && setup_max_cpus > (uintptr_t)attr->data) {
	179	dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
	180	attr->revision);
	181	return true;
	182	}
	183
	184	return false;
	185	}
	186	#else /* !CONFIG_ARCH_RCAR_GEN2 \|\| !CONFIG_SMP */
	187	static inline bool rwdt_blacklisted(struct device *dev) { return false; }
	188	#endif /* !CONFIG_ARCH_RCAR_GEN2 \|\| !CONFIG_SMP */
	189
bd99b68e WS	190	static int rwdt_probe(struct platform_device *pdev)
bd99b68e WS	191	{
b7fbd3e5	192	struct device *dev = &pdev->dev;
bd99b68e	193	struct rwdt_priv *priv;
9c22b6d3	194	struct clk *clk;
82f64cd2	195	unsigned long clks_per_sec;
bd99b68e WS	196	int ret, i;
bd99b68e WS	197
b7fbd3e5	198	if (rwdt_blacklisted(dev))
3fe95e6c FC	199	return -ENODEV;
3fe95e6c FC	200
b7fbd3e5	201	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
bd99b68e WS	202	if (!priv)
	203	return -ENOMEM;
	204
0f0a6a28	205	priv->base = devm_platform_ioremap_resource(pdev, 0);
bd99b68e WS	206	if (IS_ERR(priv->base))
	207	return PTR_ERR(priv->base);
	208
b7fbd3e5	209	clk = devm_clk_get(dev, NULL);
9c22b6d3 WS	210	if (IS_ERR(clk))
9c22b6d3 WS	211	return PTR_ERR(clk);
bd99b68e	212
b7fbd3e5 HNA	213	pm_runtime_enable(dev);
b7fbd3e5 HNA	214	pm_runtime_get_sync(dev);
9c22b6d3	215	priv->clk_rate = clk_get_rate(clk);
fdac6a90 VC	216	priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) &
fdac6a90 VC	217	RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0;
b7fbd3e5	218	pm_runtime_put(dev);
3be42941 WS	219
	220	if (!priv->clk_rate) {
	221	ret = -ENOENT;
	222	goto out_pm_disable;
	223	}
bd99b68e WS	224
bd99b68e WS	225	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
82f64cd2	226	clks_per_sec = priv->clk_rate / clk_divs[i];
b51247c8	227	if (clks_per_sec && clks_per_sec < 65536) {
bd99b68e WS	228	priv->cks = i;
	229	break;
	230	}
	231	}
	232
b51247c8	233	if (i < 0) {
b7fbd3e5	234	dev_err(dev, "Can't find suitable clock divider\n");
3be42941 WS	235	ret = -ERANGE;
3be42941 WS	236	goto out_pm_disable;
bd99b68e WS	237	}
bd99b68e WS	238
f8cde726 FC	239	priv->wdev.info = &rwdt_ident;
f8cde726 FC	240	priv->wdev.ops = &rwdt_ops;
b7fbd3e5	241	priv->wdev.parent = dev;
bd99b68e	242	priv->wdev.min_timeout = 1;
82f64cd2	243	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
bd99b68e WS	244	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
	245
	246	platform_set_drvdata(pdev, priv);
	247	watchdog_set_drvdata(&priv->wdev, priv);
	248	watchdog_set_nowayout(&priv->wdev, nowayout);
089bcaa8	249	watchdog_set_restart_priority(&priv->wdev, 0);
14de99b4	250	watchdog_stop_on_unregister(&priv->wdev);
bd99b68e WS	251
bd99b68e WS	252	/* This overrides the default timeout only if DT configuration was found */
b7fbd3e5	253	watchdog_init_timeout(&priv->wdev, 0, dev);
bd99b68e WS	254
bd99b68e WS	255	ret = watchdog_register_device(&priv->wdev);
3be42941 WS	256	if (ret < 0)
3be42941 WS	257	goto out_pm_disable;
bd99b68e WS	258
bd99b68e WS	259	return 0;
3be42941 WS	260
3be42941 WS	261	out_pm_disable:
b7fbd3e5	262	pm_runtime_disable(dev);
3be42941	263	return ret;
bd99b68e WS	264	}
	265
	266	static int rwdt_remove(struct platform_device *pdev)
	267	{
	268	struct rwdt_priv *priv = platform_get_drvdata(pdev);
	269
	270	watchdog_unregister_device(&priv->wdev);
bd99b68e WS	271	pm_runtime_disable(&pdev->dev);
	272
	273	return 0;
	274	}
	275
07278ca1 FC	276	static int __maybe_unused rwdt_suspend(struct device *dev)
	277	{
	278	struct rwdt_priv *priv = dev_get_drvdata(dev);
	279
9077123c	280	if (watchdog_active(&priv->wdev))
07278ca1	281	rwdt_stop(&priv->wdev);
9077123c	282
07278ca1 FC	283	return 0;
	284	}
	285
	286	static int __maybe_unused rwdt_resume(struct device *dev)
	287	{
	288	struct rwdt_priv *priv = dev_get_drvdata(dev);
	289
9077123c	290	if (watchdog_active(&priv->wdev))
07278ca1	291	rwdt_start(&priv->wdev);
9077123c	292
07278ca1 FC	293	return 0;
	294	}
	295
	296	static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
	297
bd99b68e	298	static const struct of_device_id rwdt_ids[] = {
3fe95e6c	299	{ .compatible = "renesas,rcar-gen2-wdt", },
bd99b68e WS	300	{ .compatible = "renesas,rcar-gen3-wdt", },
	301	{ /* sentinel */ }
	302	};
	303	MODULE_DEVICE_TABLE(of, rwdt_ids);
	304
	305	static struct platform_driver rwdt_driver = {
	306	.driver = {
	307	.name = "renesas_wdt",
	308	.of_match_table = rwdt_ids,
07278ca1	309	.pm = &rwdt_pm_ops,
bd99b68e WS	310	},
	311	.probe = rwdt_probe,
	312	.remove = rwdt_remove,
	313	};
	314	module_platform_driver(rwdt_driver);
	315
	316	MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
	317	MODULE_LICENSE("GPL v2");
	318	MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");