[mirror_ubuntu-jammy-kernel.git] / drivers / watchdog / renesas_wdt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Watchdog driver for Renesas WDT watchdog
 *
 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 * Copyright (C) 2015-17 Renesas Electronics Corporation
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/smp.h>
#include <linux/sys_soc.h>
#include <linux/watchdog.h>

#define RWTCNT		0
#define RWTCSRA		4
#define RWTCSRA_WOVF	BIT(4)
#define RWTCSRA_WRFLG	BIT(5)
#define RWTCSRA_TME	BIT(7)
#define RWTCSRB		8

#define RWDT_DEFAULT_TIMEOUT 60U

/*
 * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
 * divider (12 bits). d is only a factor to fully utilize the WDT counter and
 * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
 */
#define MUL_BY_CLKS_PER_SEC(p, d) \
	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])

/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)

static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

struct rwdt_priv {
	void __iomem *base;
	struct watchdog_device wdev;
	unsigned long clk_rate;
	u8 cks;
	struct clk *clk;
};

static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
{
	if (reg == RWTCNT)
		val |= 0x5a5a0000;
	else
		val |= 0xa5a5a500;

	writel_relaxed(val, priv->base + reg);
}

static int rwdt_init_timeout(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);

	return 0;
}

static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
{
	unsigned int delay;

	delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);

	usleep_range(delay, 2 * delay);
}

static int rwdt_start(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	u8 val;

	pm_runtime_get_sync(wdev->parent);

	/* Stop the timer before we modify any register */
	val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
	rwdt_write(priv, val, RWTCSRA);
	/* Delay 2 cycles before setting watchdog counter */
	rwdt_wait_cycles(priv, 2);

	rwdt_init_timeout(wdev);
	rwdt_write(priv, priv->cks, RWTCSRA);
	rwdt_write(priv, 0, RWTCSRB);

	while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
		cpu_relax();

	rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);

	return 0;
}

static int rwdt_stop(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	rwdt_write(priv, priv->cks, RWTCSRA);
	/* Delay 3 cycles before disabling module clock */
	rwdt_wait_cycles(priv, 3);
	pm_runtime_put(wdev->parent);

	return 0;
}

static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	u16 val = readw_relaxed(priv->base + RWTCNT);

	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
}

/* needs to be atomic - no RPM, no usleep_range, no scheduling! */
static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
			void *data)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	u8 val;

	clk_prepare_enable(priv->clk);

	/* Stop the timer before we modify any register */
	val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
	rwdt_write(priv, val, RWTCSRA);
	/* Delay 2 cycles before setting watchdog counter */
	udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));

	rwdt_write(priv, 0xffff, RWTCNT);
	/* smallest divider to reboot soon */
	rwdt_write(priv, 0, RWTCSRA);

	readb_poll_timeout_atomic(priv->base + RWTCSRA, val,
				  !(val & RWTCSRA_WRFLG), 1, 100);

	rwdt_write(priv, RWTCSRA_TME, RWTCSRA);

	/* wait 2 cycles, so watchdog will trigger */
	udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));

	return 0;
}

static const struct watchdog_info rwdt_ident = {
	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
		WDIOF_CARDRESET,
	.identity = "Renesas WDT Watchdog",
};

static const struct watchdog_ops rwdt_ops = {
	.owner = THIS_MODULE,
	.start = rwdt_start,
	.stop = rwdt_stop,
	.ping = rwdt_init_timeout,
	.get_timeleft = rwdt_get_timeleft,
	.restart = rwdt_restart,
};

#if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
/*
 * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
 */
static const struct soc_device_attribute rwdt_quirks_match[] = {
	{
		.soc_id = "r8a7790",
		.revision = "ES1.*",
		.data = (void *)1,	/* needs single CPU */
	}, {
		.soc_id = "r8a7791",
		.revision = "ES1.*",
		.data = (void *)1,	/* needs single CPU */
	}, {
		.soc_id = "r8a7792",
		.data = (void *)0,	/* needs SMP disabled */
	},
	{ /* sentinel */ }
};

static bool rwdt_blacklisted(struct device *dev)
{
	const struct soc_device_attribute *attr;

	attr = soc_device_match(rwdt_quirks_match);
	if (attr && setup_max_cpus > (uintptr_t)attr->data) {
		dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
			 attr->revision);
		return true;
	}

	return false;
}
#else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
static inline bool rwdt_blacklisted(struct device *dev) { return false; }
#endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */

static int rwdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rwdt_priv *priv;
	unsigned long clks_per_sec;
	int ret, i;
	u8 csra;

	if (rwdt_blacklisted(dev))
		return -ENODEV;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk))
		return PTR_ERR(priv->clk);

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	priv->clk_rate = clk_get_rate(priv->clk);
	csra = readb_relaxed(priv->base + RWTCSRA);
	priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
	pm_runtime_put(dev);

	if (!priv->clk_rate) {
		ret = -ENOENT;
		goto out_pm_disable;
	}

	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
		clks_per_sec = priv->clk_rate / clk_divs[i];
		if (clks_per_sec && clks_per_sec < 65536) {
			priv->cks = i;
			break;
		}
	}

	if (i < 0) {
		dev_err(dev, "Can't find suitable clock divider\n");
		ret = -ERANGE;
		goto out_pm_disable;
	}

	priv->wdev.info = &rwdt_ident;
	priv->wdev.ops = &rwdt_ops;
	priv->wdev.parent = dev;
	priv->wdev.min_timeout = 1;
	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);

	platform_set_drvdata(pdev, priv);
	watchdog_set_drvdata(&priv->wdev, priv);
	watchdog_set_nowayout(&priv->wdev, nowayout);
	watchdog_set_restart_priority(&priv->wdev, 0);
	watchdog_stop_on_unregister(&priv->wdev);

	/* This overrides the default timeout only if DT configuration was found */
	watchdog_init_timeout(&priv->wdev, 0, dev);

	/* Check if FW enabled the watchdog */
	if (csra & RWTCSRA_TME) {
		/* Ensure properly initialized dividers */
		rwdt_start(&priv->wdev);
		set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
	}

	ret = watchdog_register_device(&priv->wdev);
	if (ret < 0)
		goto out_pm_disable;

	return 0;

 out_pm_disable:
	pm_runtime_disable(dev);
	return ret;
}

static int rwdt_remove(struct platform_device *pdev)
{
	struct rwdt_priv *priv = platform_get_drvdata(pdev);

	watchdog_unregister_device(&priv->wdev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static int __maybe_unused rwdt_suspend(struct device *dev)
{
	struct rwdt_priv *priv = dev_get_drvdata(dev);

	if (watchdog_active(&priv->wdev))
		rwdt_stop(&priv->wdev);

	return 0;
}

static int __maybe_unused rwdt_resume(struct device *dev)
{
	struct rwdt_priv *priv = dev_get_drvdata(dev);

	if (watchdog_active(&priv->wdev))
		rwdt_start(&priv->wdev);

	return 0;
}

static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);

static const struct of_device_id rwdt_ids[] = {
	{ .compatible = "renesas,rcar-gen2-wdt", },
	{ .compatible = "renesas,rcar-gen3-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rwdt_ids);

static struct platform_driver rwdt_driver = {
	.driver = {
		.name = "renesas_wdt",
		.of_match_table = rwdt_ids,
		.pm = &rwdt_pm_ops,
	},
	.probe = rwdt_probe,
	.remove = rwdt_remove,
};
module_platform_driver(rwdt_driver);

MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
Commit	Line	Data
3bed02a2	1	// SPDX-License-Identifier: GPL-2.0
bd99b68e WS	2	/*
	3	* Watchdog driver for Renesas WDT watchdog
	4	*
1f185596 WS	5	* Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
1f185596 WS	6	* Copyright (C) 2015-17 Renesas Electronics Corporation
bd99b68e WS	7	*/
	8	#include <linux/bitops.h>
	9	#include <linux/clk.h>
b836005b	10	#include <linux/delay.h>
bd99b68e	11	#include <linux/io.h>
fa01fa70	12	#include <linux/iopoll.h>
bd99b68e WS	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/pm_runtime.h>
3fe95e6c FC	18	#include <linux/smp.h>
3fe95e6c FC	19	#include <linux/sys_soc.h>
bd99b68e WS	20	#include <linux/watchdog.h>
	21
	22	#define RWTCNT 0
	23	#define RWTCSRA 4
	24	#define RWTCSRA_WOVF BIT(4)
	25	#define RWTCSRA_WRFLG BIT(5)
	26	#define RWTCSRA_TME BIT(7)
03a196f2	27	#define RWTCSRB 8
bd99b68e WS	28
	29	#define RWDT_DEFAULT_TIMEOUT 60U
	30
82f64cd2 WS	31	/*
82f64cd2 WS	32	* In probe, clk_rate is checked to be not more than 16 bit * biggest clock
03a196f2	33	* divider (12 bits). d is only a factor to fully utilize the WDT counter and
82f64cd2 WS	34	* will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
	35	*/
	36	#define MUL_BY_CLKS_PER_SEC(p, d) \
	37	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
	38
03a196f2	39	/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
82f64cd2 WS	40	#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
82f64cd2 WS	41
03a196f2	42	static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
bd99b68e WS	43
	44	static bool nowayout = WATCHDOG_NOWAYOUT;
	45	module_param(nowayout, bool, 0);
	46	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	47	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	48
	49	struct rwdt_priv {
	50	void __iomem *base;
	51	struct watchdog_device wdev;
82f64cd2	52	unsigned long clk_rate;
bd99b68e	53	u8 cks;
fa01fa70	54	struct clk *clk;
bd99b68e WS	55	};
	56
	57	static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
	58	{
	59	if (reg == RWTCNT)
	60	val \|= 0x5a5a0000;
	61	else
	62	val \|= 0xa5a5a500;
	63
	64	writel_relaxed(val, priv->base + reg);
	65	}
	66
	67	static int rwdt_init_timeout(struct watchdog_device *wdev)
	68	{
	69	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	70
82f64cd2	71	rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
bd99b68e WS	72
	73	return 0;
	74	}
	75
b836005b YS	76	static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
	77	{
	78	unsigned int delay;
	79
	80	delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
	81
	82	usleep_range(delay, 2 * delay);
	83	}
	84
bd99b68e WS	85	static int rwdt_start(struct watchdog_device *wdev)
	86	{
	87	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
e990e127	88	u8 val;
bd99b68e	89
3be42941	90	pm_runtime_get_sync(wdev->parent);
bd99b68e	91
e990e127 WS	92	/* Stop the timer before we modify any register */
	93	val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
	94	rwdt_write(priv, val, RWTCSRA);
b836005b YS	95	/* Delay 2 cycles before setting watchdog counter */
b836005b YS	96	rwdt_wait_cycles(priv, 2);
e990e127	97
bd99b68e	98	rwdt_init_timeout(wdev);
e990e127 WS	99	rwdt_write(priv, priv->cks, RWTCSRA);
e990e127 WS	100	rwdt_write(priv, 0, RWTCSRB);
bd99b68e WS	101
	102	while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
	103	cpu_relax();
	104
	105	rwdt_write(priv, priv->cks \| RWTCSRA_TME, RWTCSRA);
	106
	107	return 0;
	108	}
	109
	110	static int rwdt_stop(struct watchdog_device *wdev)
	111	{
	112	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	113
	114	rwdt_write(priv, priv->cks, RWTCSRA);
b836005b YS	115	/* Delay 3 cycles before disabling module clock */
b836005b YS	116	rwdt_wait_cycles(priv, 3);
3be42941	117	pm_runtime_put(wdev->parent);
bd99b68e WS	118
	119	return 0;
	120	}
	121
	122	static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
	123	{
	124	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	125	u16 val = readw_relaxed(priv->base + RWTCNT);
	126
82f64cd2	127	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
bd99b68e WS	128	}
bd99b68e WS	129
fa01fa70	130	/* needs to be atomic - no RPM, no usleep_range, no scheduling! */
089bcaa8 FC	131	static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
	132	void *data)
	133	{
	134	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
fa01fa70 WS	135	u8 val;
	136
	137	clk_prepare_enable(priv->clk);
	138
	139	/* Stop the timer before we modify any register */
	140	val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
	141	rwdt_write(priv, val, RWTCSRA);
	142	/* Delay 2 cycles before setting watchdog counter */
	143	udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
089bcaa8	144
089bcaa8	145	rwdt_write(priv, 0xffff, RWTCNT);
fa01fa70 WS	146	/* smallest divider to reboot soon */
	147	rwdt_write(priv, 0, RWTCSRA);
	148
	149	readb_poll_timeout_atomic(priv->base + RWTCSRA, val,
	150	!(val & RWTCSRA_WRFLG), 1, 100);
	151
	152	rwdt_write(priv, RWTCSRA_TME, RWTCSRA);
	153
e007372b WS	154	/* wait 2 cycles, so watchdog will trigger */
	155	udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
	156
089bcaa8 FC	157	return 0;
	158	}
	159
bd99b68e	160	static const struct watchdog_info rwdt_ident = {
fdac6a90 VC	161	.options = WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \|
fdac6a90 VC	162	WDIOF_CARDRESET,
bd99b68e WS	163	.identity = "Renesas WDT Watchdog",
	164	};
	165
	166	static const struct watchdog_ops rwdt_ops = {
	167	.owner = THIS_MODULE,
	168	.start = rwdt_start,
	169	.stop = rwdt_stop,
	170	.ping = rwdt_init_timeout,
	171	.get_timeleft = rwdt_get_timeleft,
089bcaa8	172	.restart = rwdt_restart,
bd99b68e WS	173	};
bd99b68e WS	174
3fe95e6c FC	175	#if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
	176	/*
	177	* Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
	178	*/
	179	static const struct soc_device_attribute rwdt_quirks_match[] = {
	180	{
	181	.soc_id = "r8a7790",
	182	.revision = "ES1.*",
	183	.data = (void )1, / needs single CPU */
	184	}, {
	185	.soc_id = "r8a7791",
665f9442	186	.revision = "ES1.*",
3fe95e6c FC	187	.data = (void )1, / needs single CPU */
	188	}, {
	189	.soc_id = "r8a7792",
3fe95e6c FC	190	.data = (void )0, / needs SMP disabled */
	191	},
	192	{ /* sentinel */ }
	193	};
	194
	195	static bool rwdt_blacklisted(struct device *dev)
	196	{
	197	const struct soc_device_attribute *attr;
	198
	199	attr = soc_device_match(rwdt_quirks_match);
	200	if (attr && setup_max_cpus > (uintptr_t)attr->data) {
	201	dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
	202	attr->revision);
	203	return true;
	204	}
	205
	206	return false;
	207	}
	208	#else /* !CONFIG_ARCH_RCAR_GEN2 \|\| !CONFIG_SMP */
	209	static inline bool rwdt_blacklisted(struct device *dev) { return false; }
	210	#endif /* !CONFIG_ARCH_RCAR_GEN2 \|\| !CONFIG_SMP */
	211
bd99b68e WS	212	static int rwdt_probe(struct platform_device *pdev)
bd99b68e WS	213	{
b7fbd3e5	214	struct device *dev = &pdev->dev;
bd99b68e	215	struct rwdt_priv *priv;
82f64cd2	216	unsigned long clks_per_sec;
bd99b68e	217	int ret, i;
962085a2	218	u8 csra;
bd99b68e	219
b7fbd3e5	220	if (rwdt_blacklisted(dev))
3fe95e6c FC	221	return -ENODEV;
3fe95e6c FC	222
b7fbd3e5	223	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
bd99b68e WS	224	if (!priv)
	225	return -ENOMEM;
	226
0f0a6a28	227	priv->base = devm_platform_ioremap_resource(pdev, 0);
bd99b68e WS	228	if (IS_ERR(priv->base))
	229	return PTR_ERR(priv->base);
	230
fa01fa70 WS	231	priv->clk = devm_clk_get(dev, NULL);
	232	if (IS_ERR(priv->clk))
	233	return PTR_ERR(priv->clk);
bd99b68e	234
b7fbd3e5 HNA	235	pm_runtime_enable(dev);
b7fbd3e5 HNA	236	pm_runtime_get_sync(dev);
fa01fa70	237	priv->clk_rate = clk_get_rate(priv->clk);
962085a2 WS	238	csra = readb_relaxed(priv->base + RWTCSRA);
962085a2 WS	239	priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
b7fbd3e5	240	pm_runtime_put(dev);
3be42941 WS	241
	242	if (!priv->clk_rate) {
	243	ret = -ENOENT;
	244	goto out_pm_disable;
	245	}
bd99b68e WS	246
bd99b68e WS	247	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
82f64cd2	248	clks_per_sec = priv->clk_rate / clk_divs[i];
b51247c8	249	if (clks_per_sec && clks_per_sec < 65536) {
bd99b68e WS	250	priv->cks = i;
	251	break;
	252	}
	253	}
	254
b51247c8	255	if (i < 0) {
b7fbd3e5	256	dev_err(dev, "Can't find suitable clock divider\n");
3be42941 WS	257	ret = -ERANGE;
3be42941 WS	258	goto out_pm_disable;
bd99b68e WS	259	}
bd99b68e WS	260
f8cde726 FC	261	priv->wdev.info = &rwdt_ident;
f8cde726 FC	262	priv->wdev.ops = &rwdt_ops;
b7fbd3e5	263	priv->wdev.parent = dev;
bd99b68e	264	priv->wdev.min_timeout = 1;
82f64cd2	265	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
bd99b68e WS	266	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
	267
	268	platform_set_drvdata(pdev, priv);
	269	watchdog_set_drvdata(&priv->wdev, priv);
	270	watchdog_set_nowayout(&priv->wdev, nowayout);
089bcaa8	271	watchdog_set_restart_priority(&priv->wdev, 0);
14de99b4	272	watchdog_stop_on_unregister(&priv->wdev);
bd99b68e WS	273
bd99b68e WS	274	/* This overrides the default timeout only if DT configuration was found */
b7fbd3e5	275	watchdog_init_timeout(&priv->wdev, 0, dev);
bd99b68e	276
962085a2 WS	277	/* Check if FW enabled the watchdog */
	278	if (csra & RWTCSRA_TME) {
	279	/* Ensure properly initialized dividers */
	280	rwdt_start(&priv->wdev);
	281	set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
	282	}
	283
bd99b68e	284	ret = watchdog_register_device(&priv->wdev);
3be42941 WS	285	if (ret < 0)
3be42941 WS	286	goto out_pm_disable;
bd99b68e WS	287
bd99b68e WS	288	return 0;
3be42941 WS	289
3be42941 WS	290	out_pm_disable:
b7fbd3e5	291	pm_runtime_disable(dev);
3be42941	292	return ret;
bd99b68e WS	293	}
	294
	295	static int rwdt_remove(struct platform_device *pdev)
	296	{
	297	struct rwdt_priv *priv = platform_get_drvdata(pdev);
	298
	299	watchdog_unregister_device(&priv->wdev);
bd99b68e WS	300	pm_runtime_disable(&pdev->dev);
	301
	302	return 0;
	303	}
	304
07278ca1 FC	305	static int __maybe_unused rwdt_suspend(struct device *dev)
	306	{
	307	struct rwdt_priv *priv = dev_get_drvdata(dev);
	308
9077123c	309	if (watchdog_active(&priv->wdev))
07278ca1	310	rwdt_stop(&priv->wdev);
9077123c	311
07278ca1 FC	312	return 0;
	313	}
	314
	315	static int __maybe_unused rwdt_resume(struct device *dev)
	316	{
	317	struct rwdt_priv *priv = dev_get_drvdata(dev);
	318
9077123c	319	if (watchdog_active(&priv->wdev))
07278ca1	320	rwdt_start(&priv->wdev);
9077123c	321
07278ca1 FC	322	return 0;
	323	}
	324
	325	static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
	326
bd99b68e	327	static const struct of_device_id rwdt_ids[] = {
3fe95e6c	328	{ .compatible = "renesas,rcar-gen2-wdt", },
bd99b68e WS	329	{ .compatible = "renesas,rcar-gen3-wdt", },
	330	{ /* sentinel */ }
	331	};
	332	MODULE_DEVICE_TABLE(of, rwdt_ids);
	333
	334	static struct platform_driver rwdt_driver = {
	335	.driver = {
	336	.name = "renesas_wdt",
	337	.of_match_table = rwdt_ids,
07278ca1	338	.pm = &rwdt_pm_ops,
bd99b68e WS	339	},
	340	.probe = rwdt_probe,
	341	.remove = rwdt_remove,
	342	};
	343	module_platform_driver(rwdt_driver);
	344
	345	MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
	346	MODULE_LICENSE("GPL v2");
	347	MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");