[mirror_ubuntu-bionic-kernel.git] / drivers / watchdog / rza_wdt.c

/*
 * Renesas RZ/A Series WDT Driver
 *
 * Copyright (C) 2017 Renesas Electronics America, Inc.
 * Copyright (C) 2017 Chris Brandt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>

#define DEFAULT_TIMEOUT		30

/* Watchdog Timer Registers */
#define WTCSR			0
#define WTCSR_MAGIC		0xA500
#define WTSCR_WT		BIT(6)
#define WTSCR_TME		BIT(5)
#define WTSCR_CKS(i)		(i)

#define WTCNT			2
#define WTCNT_MAGIC		0x5A00

#define WRCSR			4
#define WRCSR_MAGIC		0x5A00
#define WRCSR_RSTE		BIT(6)
#define WRCSR_CLEAR_WOVF	0xA500	/* special value */

struct rza_wdt {
	struct watchdog_device wdev;
	void __iomem *base;
	struct clk *clk;
};

static int rza_wdt_start(struct watchdog_device *wdev)
{
	struct rza_wdt *priv = watchdog_get_drvdata(wdev);

	/* Stop timer */
	writew(WTCSR_MAGIC | 0, priv->base + WTCSR);

	/* Must dummy read WRCSR:WOVF at least once before clearing */
	readb(priv->base + WRCSR);
	writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);

	/*
	 * Start timer with slowest clock source and reset option enabled.
	 */
	writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
	writew(WTCNT_MAGIC | 0, priv->base + WTCNT);
	writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | WTSCR_CKS(7),
	       priv->base + WTCSR);

	return 0;
}

static int rza_wdt_stop(struct watchdog_device *wdev)
{
	struct rza_wdt *priv = watchdog_get_drvdata(wdev);

	writew(WTCSR_MAGIC | 0, priv->base + WTCSR);

	return 0;
}

static int rza_wdt_ping(struct watchdog_device *wdev)
{
	struct rza_wdt *priv = watchdog_get_drvdata(wdev);

	writew(WTCNT_MAGIC | 0, priv->base + WTCNT);

	return 0;
}

static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action,
			    void *data)
{
	struct rza_wdt *priv = watchdog_get_drvdata(wdev);

	/* Stop timer */
	writew(WTCSR_MAGIC | 0, priv->base + WTCSR);

	/* Must dummy read WRCSR:WOVF at least once before clearing */
	readb(priv->base + WRCSR);
	writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);

	/*
	 * Start timer with fastest clock source and only 1 clock left before
	 * overflow with reset option enabled.
	 */
	writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
	writew(WTCNT_MAGIC | 255, priv->base + WTCNT);
	writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR);

	/*
	 * Actually make sure the above sequence hits hardware before sleeping.
	 */
	wmb();

	/* Wait for WDT overflow (reset) */
	udelay(20);

	return 0;
}

static const struct watchdog_info rza_wdt_ident = {
	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
	.identity = "Renesas RZ/A WDT Watchdog",
};

static const struct watchdog_ops rza_wdt_ops = {
	.owner = THIS_MODULE,
	.start = rza_wdt_start,
	.stop = rza_wdt_stop,
	.ping = rza_wdt_ping,
	.restart = rza_wdt_restart,
};

static int rza_wdt_probe(struct platform_device *pdev)
{
	struct rza_wdt *priv;
	struct resource *res;
	unsigned long rate;
	int ret;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(priv->clk))
		return PTR_ERR(priv->clk);

	rate = clk_get_rate(priv->clk);
	if (rate < 16384) {
		dev_err(&pdev->dev, "invalid clock rate (%ld)\n", rate);
		return -ENOENT;
	}

	/* Assume slowest clock rate possible (CKS=7) */
	rate /= 16384;

	priv->wdev.info = &rza_wdt_ident,
	priv->wdev.ops = &rza_wdt_ops,
	priv->wdev.parent = &pdev->dev;

	/*
	 * Since the max possible timeout of our 8-bit count register is less
	 * than a second, we must use max_hw_heartbeat_ms.
	 */
	priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
	dev_dbg(&pdev->dev, "max hw timeout of %dms\n",
		 priv->wdev.max_hw_heartbeat_ms);

	priv->wdev.min_timeout = 1;
	priv->wdev.timeout = DEFAULT_TIMEOUT;

	watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
	watchdog_set_drvdata(&priv->wdev, priv);

	ret = devm_watchdog_register_device(&pdev->dev, &priv->wdev);
	if (ret)
		dev_err(&pdev->dev, "Cannot register watchdog device\n");

	return ret;
}

static const struct of_device_id rza_wdt_of_match[] = {
	{ .compatible = "renesas,rza-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rza_wdt_of_match);

static struct platform_driver rza_wdt_driver = {
	.probe = rza_wdt_probe,
	.driver = {
		.name = "rza_wdt",
		.of_match_table = rza_wdt_of_match,
	},
};

module_platform_driver(rza_wdt_driver);

MODULE_DESCRIPTION("Renesas RZ/A WDT Driver");
MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
aea24187 CB	1	/*
	2	* Renesas RZ/A Series WDT Driver
	3	*
	4	* Copyright (C) 2017 Renesas Electronics America, Inc.
	5	* Copyright (C) 2017 Chris Brandt
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11
	12	#include <linux/bitops.h>
	13	#include <linux/clk.h>
	14	#include <linux/delay.h>
	15	#include <linux/module.h>
	16	#include <linux/of_address.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/watchdog.h>
	19
	20	#define DEFAULT_TIMEOUT 30
	21
	22	/* Watchdog Timer Registers */
	23	#define WTCSR 0
	24	#define WTCSR_MAGIC 0xA500
	25	#define WTSCR_WT BIT(6)
	26	#define WTSCR_TME BIT(5)
	27	#define WTSCR_CKS(i) (i)
	28
	29	#define WTCNT 2
	30	#define WTCNT_MAGIC 0x5A00
	31
	32	#define WRCSR 4
	33	#define WRCSR_MAGIC 0x5A00
	34	#define WRCSR_RSTE BIT(6)
	35	#define WRCSR_CLEAR_WOVF 0xA500 /* special value */
	36
	37	struct rza_wdt {
	38	struct watchdog_device wdev;
	39	void __iomem *base;
	40	struct clk *clk;
	41	};
	42
	43	static int rza_wdt_start(struct watchdog_device *wdev)
	44	{
	45	struct rza_wdt *priv = watchdog_get_drvdata(wdev);
	46
	47	/* Stop timer */
	48	writew(WTCSR_MAGIC \| 0, priv->base + WTCSR);
	49
	50	/* Must dummy read WRCSR:WOVF at least once before clearing */
	51	readb(priv->base + WRCSR);
	52	writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
	53
	54	/*
	55	* Start timer with slowest clock source and reset option enabled.
	56	*/
	57	writew(WRCSR_MAGIC \| WRCSR_RSTE, priv->base + WRCSR);
	58	writew(WTCNT_MAGIC \| 0, priv->base + WTCNT);
	59	writew(WTCSR_MAGIC \| WTSCR_WT \| WTSCR_TME \| WTSCR_CKS(7),
	60	priv->base + WTCSR);
	61
	62	return 0;
	63	}
	64
65	static int rza_wdt_stop(struct watchdog_device *wdev)
66	{
67	struct rza_wdt *priv = watchdog_get_drvdata(wdev);
68
69	writew(WTCSR_MAGIC \| 0, priv->base + WTCSR);
70
71	return 0;
72	}
73
74	static int rza_wdt_ping(struct watchdog_device *wdev)
75	{
76	struct rza_wdt *priv = watchdog_get_drvdata(wdev);
77
78	writew(WTCNT_MAGIC \| 0, priv->base + WTCNT);
79
80	return 0;
81	}
82
83	static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action,
84	void *data)
85	{
86	struct rza_wdt *priv = watchdog_get_drvdata(wdev);
87
88	/* Stop timer */
89	writew(WTCSR_MAGIC \| 0, priv->base + WTCSR);
90
91	/* Must dummy read WRCSR:WOVF at least once before clearing */
92	readb(priv->base + WRCSR);
93	writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
94
95	/*
96	* Start timer with fastest clock source and only 1 clock left before
97	* overflow with reset option enabled.
98	*/
99	writew(WRCSR_MAGIC \| WRCSR_RSTE, priv->base + WRCSR);
100	writew(WTCNT_MAGIC \| 255, priv->base + WTCNT);
101	writew(WTCSR_MAGIC \| WTSCR_WT \| WTSCR_TME, priv->base + WTCSR);
102
103	/*
104	* Actually make sure the above sequence hits hardware before sleeping.
105	*/
106	wmb();
107
108	/* Wait for WDT overflow (reset) */
109	udelay(20);
110
111	return 0;
112	}
113
114	static const struct watchdog_info rza_wdt_ident = {
115	.options = WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT,
116	.identity = "Renesas RZ/A WDT Watchdog",
117	};
118
119	static const struct watchdog_ops rza_wdt_ops = {
120	.owner = THIS_MODULE,
121	.start = rza_wdt_start,
122	.stop = rza_wdt_stop,
123	.ping = rza_wdt_ping,
124	.restart = rza_wdt_restart,
125	};
126
127	static int rza_wdt_probe(struct platform_device *pdev)
128	{
129	struct rza_wdt *priv;
130	struct resource *res;
131	unsigned long rate;
132	int ret;
133
134	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
135	if (!priv)
136	return -ENOMEM;
137
138	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
139	priv->base = devm_ioremap_resource(&pdev->dev, res);
140	if (IS_ERR(priv->base))
141	return PTR_ERR(priv->base);
142
143	priv->clk = devm_clk_get(&pdev->dev, NULL);
144	if (IS_ERR(priv->clk))
145	return PTR_ERR(priv->clk);
146
147	rate = clk_get_rate(priv->clk);
148	if (rate < 16384) {
149	dev_err(&pdev->dev, "invalid clock rate (%ld)\n", rate);
150	return -ENOENT;
151	}
152
153	/* Assume slowest clock rate possible (CKS=7) */
154	rate /= 16384;
155
156	priv->wdev.info = &rza_wdt_ident,
157	priv->wdev.ops = &rza_wdt_ops,
158	priv->wdev.parent = &pdev->dev;
159
160	/*
161	* Since the max possible timeout of our 8-bit count register is less
162	* than a second, we must use max_hw_heartbeat_ms.
163	*/
164	priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
165	dev_dbg(&pdev->dev, "max hw timeout of %dms\n",
166	priv->wdev.max_hw_heartbeat_ms);
167
168	priv->wdev.min_timeout = 1;
169	priv->wdev.timeout = DEFAULT_TIMEOUT;
170
171	watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
172	watchdog_set_drvdata(&priv->wdev, priv);
173
174	ret = devm_watchdog_register_device(&pdev->dev, &priv->wdev);
175	if (ret)
176	dev_err(&pdev->dev, "Cannot register watchdog device\n");
177
178	return ret;
179	}
180
181	static const struct of_device_id rza_wdt_of_match[] = {
182	{ .compatible = "renesas,rza-wdt", },
183	{ /* sentinel */ }
184	};
185	MODULE_DEVICE_TABLE(of, rza_wdt_of_match);
186
187	static struct platform_driver rza_wdt_driver = {
188	.probe = rza_wdt_probe,
189	.driver = {
190	.name = "rza_wdt",
191	.of_match_table = rza_wdt_of_match,
192	},
193	};
194
195	module_platform_driver(rza_wdt_driver);
196
197	MODULE_DESCRIPTION("Renesas RZ/A WDT Driver");
198	MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
199	MODULE_LICENSE("GPL v2");