[mirror_ubuntu-artful-kernel.git] / drivers / watchdog / s3c2410_wdt.c

/* linux/drivers/char/watchdog/s3c2410_wdt.c
 *
 * Copyright (c) 2004 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 Watchdog Timer Support
 *
 * Based on, softdog.c by Alan Cox,
 *     (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>

#define S3C2410_WTCON		0x00
#define S3C2410_WTDAT		0x04
#define S3C2410_WTCNT		0x08

#define S3C2410_WTCON_RSTEN	(1 << 0)
#define S3C2410_WTCON_INTEN	(1 << 2)
#define S3C2410_WTCON_ENABLE	(1 << 5)

#define S3C2410_WTCON_DIV16	(0 << 3)
#define S3C2410_WTCON_DIV32	(1 << 3)
#define S3C2410_WTCON_DIV64	(2 << 3)
#define S3C2410_WTCON_DIV128	(3 << 3)

#define S3C2410_WTCON_PRESCALE(x)	((x) << 8)
#define S3C2410_WTCON_PRESCALE_MASK	(0xff << 8)

#define CONFIG_S3C2410_WATCHDOG_ATBOOT		(0)
#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME	(15)

static bool nowayout	= WATCHDOG_NOWAYOUT;
static int tmr_margin;
static int tmr_atboot	= CONFIG_S3C2410_WATCHDOG_ATBOOT;
static int soft_noboot;
static int debug;

module_param(tmr_margin,  int, 0);
module_param(tmr_atboot,  int, 0);
module_param(nowayout,   bool, 0);
module_param(soft_noboot, int, 0);
module_param(debug,	  int, 0);

MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
		__MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
MODULE_PARM_DESC(tmr_atboot,
		"Watchdog is started at boot time if set to 1, default="
			__MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
			__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
			"0 to reboot (default 0)");
MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");

struct s3c2410_wdt {
	struct device		*dev;
	struct clk		*clock;
	void __iomem		*reg_base;
	unsigned int		count;
	spinlock_t		lock;
	unsigned long		wtcon_save;
	unsigned long		wtdat_save;
	struct watchdog_device	wdt_device;
	struct notifier_block	freq_transition;
};

/* watchdog control routines */

#define DBG(fmt, ...)					\
do {							\
	if (debug)					\
		pr_info(fmt, ##__VA_ARGS__);		\
} while (0)

/* functions */

static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
{
	return container_of(nb, struct s3c2410_wdt, freq_transition);
}

static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
{
	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);

	spin_lock(&wdt->lock);
	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
	spin_unlock(&wdt->lock);

	return 0;
}

static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
{
	unsigned long wtcon;

	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
	wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
}

static int s3c2410wdt_stop(struct watchdog_device *wdd)
{
	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);

	spin_lock(&wdt->lock);
	__s3c2410wdt_stop(wdt);
	spin_unlock(&wdt->lock);

	return 0;
}

static int s3c2410wdt_start(struct watchdog_device *wdd)
{
	unsigned long wtcon;
	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);

	spin_lock(&wdt->lock);

	__s3c2410wdt_stop(wdt);

	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
	wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;

	if (soft_noboot) {
		wtcon |= S3C2410_WTCON_INTEN;
		wtcon &= ~S3C2410_WTCON_RSTEN;
	} else {
		wtcon &= ~S3C2410_WTCON_INTEN;
		wtcon |= S3C2410_WTCON_RSTEN;
	}

	DBG("%s: count=0x%08x, wtcon=%08lx\n",
	    __func__, wdt->count, wtcon);

	writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
	spin_unlock(&wdt->lock);

	return 0;
}

static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
{
	return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
}

static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
{
	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
	unsigned long freq = clk_get_rate(wdt->clock);
	unsigned int count;
	unsigned int divisor = 1;
	unsigned long wtcon;

	if (timeout < 1)
		return -EINVAL;

	freq /= 128;
	count = timeout * freq;

	DBG("%s: count=%d, timeout=%d, freq=%lu\n",
	    __func__, count, timeout, freq);

	/* if the count is bigger than the watchdog register,
	   then work out what we need to do (and if) we can
	   actually make this value
	*/

	if (count >= 0x10000) {
		for (divisor = 1; divisor <= 0x100; divisor++) {
			if ((count / divisor) < 0x10000)
				break;
		}

		if ((count / divisor) >= 0x10000) {
			dev_err(wdt->dev, "timeout %d too big\n", timeout);
			return -EINVAL;
		}
	}

	DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
	    __func__, timeout, divisor, count, count/divisor);

	count /= divisor;
	wdt->count = count;

	/* update the pre-scaler */
	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
	wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
	wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);

	writel(count, wdt->reg_base + S3C2410_WTDAT);
	writel(wtcon, wdt->reg_base + S3C2410_WTCON);

	wdd->timeout = (count * divisor) / freq;

	return 0;
}

#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)

static const struct watchdog_info s3c2410_wdt_ident = {
	.options          =     OPTIONS,
	.firmware_version =	0,
	.identity         =	"S3C2410 Watchdog",
};

static struct watchdog_ops s3c2410wdt_ops = {
	.owner = THIS_MODULE,
	.start = s3c2410wdt_start,
	.stop = s3c2410wdt_stop,
	.ping = s3c2410wdt_keepalive,
	.set_timeout = s3c2410wdt_set_heartbeat,
};

static struct watchdog_device s3c2410_wdd = {
	.info = &s3c2410_wdt_ident,
	.ops = &s3c2410wdt_ops,
	.timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
};

/* interrupt handler code */

static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
{
	struct s3c2410_wdt *wdt = platform_get_drvdata(param);

	dev_info(wdt->dev, "watchdog timer expired (irq)\n");

	s3c2410wdt_keepalive(&wdt->wdt_device);
	return IRQ_HANDLED;
}

#ifdef CONFIG_CPU_FREQ

static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
					  unsigned long val, void *data)
{
	int ret;
	struct s3c2410_wdt *wdt = freq_to_wdt(nb);

	if (!s3c2410wdt_is_running(wdt))
		goto done;

	if (val == CPUFREQ_PRECHANGE) {
		/* To ensure that over the change we don't cause the
		 * watchdog to trigger, we perform an keep-alive if
		 * the watchdog is running.
		 */

		s3c2410wdt_keepalive(&wdt->wdt_device);
	} else if (val == CPUFREQ_POSTCHANGE) {
		s3c2410wdt_stop(&wdt->wdt_device);

		ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
						wdt->wdt_device.timeout);

		if (ret >= 0)
			s3c2410wdt_start(&wdt->wdt_device);
		else
			goto err;
	}

done:
	return 0;

 err:
	dev_err(wdt->dev, "cannot set new value for timeout %d\n",
				wdt->wdt_device.timeout);
	return ret;
}

static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
{
	wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;

	return cpufreq_register_notifier(&wdt->freq_transition,
					 CPUFREQ_TRANSITION_NOTIFIER);
}

static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
{
	wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;

	cpufreq_unregister_notifier(&wdt->freq_transition,
				    CPUFREQ_TRANSITION_NOTIFIER);
}

#else

static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
{
	return 0;
}

static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
{
}
#endif

static int s3c2410wdt_probe(struct platform_device *pdev)
{
	struct device *dev;
	struct s3c2410_wdt *wdt;
	struct resource *wdt_mem;
	struct resource *wdt_irq;
	unsigned int wtcon;
	int started = 0;
	int ret;

	DBG("%s: probe=%p\n", __func__, pdev);

	dev = &pdev->dev;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdt->dev = &pdev->dev;
	spin_lock_init(&wdt->lock);
	wdt->wdt_device = s3c2410_wdd;

	wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (wdt_irq == NULL) {
		dev_err(dev, "no irq resource specified\n");
		ret = -ENOENT;
		goto err;
	}

	/* get the memory region for the watchdog timer */
	wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
	if (IS_ERR(wdt->reg_base)) {
		ret = PTR_ERR(wdt->reg_base);
		goto err;
	}

	DBG("probe: mapped reg_base=%p\n", wdt->reg_base);

	wdt->clock = devm_clk_get(dev, "watchdog");
	if (IS_ERR(wdt->clock)) {
		dev_err(dev, "failed to find watchdog clock source\n");
		ret = PTR_ERR(wdt->clock);
		goto err;
	}

	clk_prepare_enable(wdt->clock);

	ret = s3c2410wdt_cpufreq_register(wdt);
	if (ret < 0) {
		dev_err(dev, "failed to register cpufreq\n");
		goto err_clk;
	}

	watchdog_set_drvdata(&wdt->wdt_device, wdt);

	/* see if we can actually set the requested timer margin, and if
	 * not, try the default value */

	watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
	ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
					wdt->wdt_device.timeout);
	if (ret) {
		started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
					CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);

		if (started == 0)
			dev_info(dev,
			   "tmr_margin value out of range, default %d used\n",
			       CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
		else
			dev_info(dev, "default timer value is out of range, "
							"cannot start\n");
	}

	ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
				pdev->name, pdev);
	if (ret != 0) {
		dev_err(dev, "failed to install irq (%d)\n", ret);
		goto err_cpufreq;
	}

	watchdog_set_nowayout(&wdt->wdt_device, nowayout);

	ret = watchdog_register_device(&wdt->wdt_device);
	if (ret) {
		dev_err(dev, "cannot register watchdog (%d)\n", ret);
		goto err_cpufreq;
	}

	if (tmr_atboot && started == 0) {
		dev_info(dev, "starting watchdog timer\n");
		s3c2410wdt_start(&wdt->wdt_device);
	} else if (!tmr_atboot) {
		/* if we're not enabling the watchdog, then ensure it is
		 * disabled if it has been left running from the bootloader
		 * or other source */

		s3c2410wdt_stop(&wdt->wdt_device);
	}

	platform_set_drvdata(pdev, wdt);

	/* print out a statement of readiness */

	wtcon = readl(wdt->reg_base + S3C2410_WTCON);

	dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
		 (wtcon & S3C2410_WTCON_ENABLE) ?  "" : "in",
		 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
		 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");

	return 0;

 err_cpufreq:
	s3c2410wdt_cpufreq_deregister(wdt);

 err_clk:
	clk_disable_unprepare(wdt->clock);
	wdt->clock = NULL;

 err:
	return ret;
}

static int s3c2410wdt_remove(struct platform_device *dev)
{
	struct s3c2410_wdt *wdt = platform_get_drvdata(dev);

	watchdog_unregister_device(&wdt->wdt_device);

	s3c2410wdt_cpufreq_deregister(wdt);

	clk_disable_unprepare(wdt->clock);
	wdt->clock = NULL;

	return 0;
}

static void s3c2410wdt_shutdown(struct platform_device *dev)
{
	struct s3c2410_wdt *wdt = platform_get_drvdata(dev);

	s3c2410wdt_stop(&wdt->wdt_device);
}

#ifdef CONFIG_PM_SLEEP

static int s3c2410wdt_suspend(struct device *dev)
{
	struct s3c2410_wdt *wdt = dev_get_drvdata(dev);

	/* Save watchdog state, and turn it off. */
	wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
	wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);

	/* Note that WTCNT doesn't need to be saved. */
	s3c2410wdt_stop(&wdt->wdt_device);

	return 0;
}

static int s3c2410wdt_resume(struct device *dev)
{
	struct s3c2410_wdt *wdt = dev_get_drvdata(dev);

	/* Restore watchdog state. */
	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
	writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);

	dev_info(dev, "watchdog %sabled\n",
		(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
			s3c2410wdt_resume);

#ifdef CONFIG_OF
static const struct of_device_id s3c2410_wdt_match[] = {
	{ .compatible = "samsung,s3c2410-wdt" },
	{},
};
MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
#endif

static struct platform_driver s3c2410wdt_driver = {
	.probe		= s3c2410wdt_probe,
	.remove		= s3c2410wdt_remove,
	.shutdown	= s3c2410wdt_shutdown,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "s3c2410-wdt",
		.pm	= &s3c2410wdt_pm_ops,
		.of_match_table	= of_match_ptr(s3c2410_wdt_match),
	},
};

module_platform_driver(s3c2410wdt_driver);

MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
	      "Dimitry Andric <dimitry.andric@tomtom.com>");
MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:s3c2410-wdt");
Commit	Line	Data
1da177e4 LT	1	/* linux/drivers/char/watchdog/s3c2410_wdt.c
	2	*
	3	* Copyright (c) 2004 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2410 Watchdog Timer Support
	7	*
	8	* Based on, softdog.c by Alan Cox,
29fa0586	9	* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4 LT	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1da177e4 LT	24	*/
1da177e4 LT	25
27c766aa JP	26	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	27
1da177e4 LT	28	#include <linux/module.h>
1da177e4 LT	29	#include <linux/moduleparam.h>
1da177e4 LT	30	#include <linux/types.h>
1da177e4 LT	31	#include <linux/timer.h>
1da177e4	32	#include <linux/watchdog.h>
1da177e4	33	#include <linux/init.h>
d052d1be	34	#include <linux/platform_device.h>
1da177e4	35	#include <linux/interrupt.h>
f8ce2547	36	#include <linux/clk.h>
41dc8b72 AC	37	#include <linux/uaccess.h>
41dc8b72 AC	38	#include <linux/io.h>
e02f838e	39	#include <linux/cpufreq.h>
5a0e3ad6	40	#include <linux/slab.h>
25dc46e3	41	#include <linux/err.h>
3016a552	42	#include <linux/of.h>
1da177e4	43
a8f5401a TF	44	#define S3C2410_WTCON 0x00
	45	#define S3C2410_WTDAT 0x04
	46	#define S3C2410_WTCNT 0x08
1da177e4	47
a8f5401a TF	48	#define S3C2410_WTCON_RSTEN (1 << 0)
	49	#define S3C2410_WTCON_INTEN (1 << 2)
	50	#define S3C2410_WTCON_ENABLE (1 << 5)
1da177e4	51
a8f5401a TF	52	#define S3C2410_WTCON_DIV16 (0 << 3)
	53	#define S3C2410_WTCON_DIV32 (1 << 3)
	54	#define S3C2410_WTCON_DIV64 (2 << 3)
	55	#define S3C2410_WTCON_DIV128 (3 << 3)
	56
	57	#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
	58	#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
1da177e4	59
1da177e4 LT	60	#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
	61	#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
	62
86a1e189	63	static bool nowayout = WATCHDOG_NOWAYOUT;
c1fd5f64	64	static int tmr_margin;
1da177e4	65	static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
41dc8b72 AC	66	static int soft_noboot;
41dc8b72 AC	67	static int debug;
1da177e4 LT	68
	69	module_param(tmr_margin, int, 0);
	70	module_param(tmr_atboot, int, 0);
86a1e189	71	module_param(nowayout, bool, 0);
1da177e4 LT	72	module_param(soft_noboot, int, 0);
	73	module_param(debug, int, 0);
	74
76550d32	75	MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
41dc8b72 AC	76	__MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
	77	MODULE_PARM_DESC(tmr_atboot,
	78	"Watchdog is started at boot time if set to 1, default="
	79	__MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
	80	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	81	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
a77dba7e	82	MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
76550d32 RD	83	"0 to reboot (default 0)");
76550d32 RD	84	MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
1da177e4	85
af4ea631 LKA	86	struct s3c2410_wdt {
	87	struct device *dev;
	88	struct clk *clock;
	89	void __iomem *reg_base;
	90	unsigned int count;
	91	spinlock_t lock;
	92	unsigned long wtcon_save;
	93	unsigned long wtdat_save;
	94	struct watchdog_device wdt_device;
	95	struct notifier_block freq_transition;
	96	};
1da177e4 LT	97
	98	/* watchdog control routines */
	99
27c766aa JP	100	#define DBG(fmt, ...) \
	101	do { \
	102	if (debug) \
	103	pr_info(fmt, ##__VA_ARGS__); \
	104	} while (0)
1da177e4 LT	105
	106	/* functions */
	107
af4ea631 LKA	108	static inline struct s3c2410_wdt freq_to_wdt(struct notifier_block nb)
	109	{
	110	return container_of(nb, struct s3c2410_wdt, freq_transition);
	111	}
	112
25dc46e3	113	static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
1da177e4	114	{
af4ea631 LKA	115	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
	116
	117	spin_lock(&wdt->lock);
	118	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
	119	spin_unlock(&wdt->lock);
25dc46e3 WS	120
25dc46e3 WS	121	return 0;
1da177e4 LT	122	}
1da177e4 LT	123
af4ea631	124	static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
41dc8b72 AC	125	{
	126	unsigned long wtcon;
	127
af4ea631	128	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
41dc8b72	129	wtcon &= ~(S3C2410_WTCON_ENABLE \| S3C2410_WTCON_RSTEN);
af4ea631	130	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
41dc8b72 AC	131	}
41dc8b72 AC	132
25dc46e3	133	static int s3c2410wdt_stop(struct watchdog_device *wdd)
41dc8b72	134	{
af4ea631 LKA	135	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
	136
	137	spin_lock(&wdt->lock);
	138	__s3c2410wdt_stop(wdt);
	139	spin_unlock(&wdt->lock);
25dc46e3 WS	140
25dc46e3 WS	141	return 0;
1da177e4 LT	142	}
1da177e4 LT	143
25dc46e3	144	static int s3c2410wdt_start(struct watchdog_device *wdd)
1da177e4 LT	145	{
1da177e4 LT	146	unsigned long wtcon;
af4ea631	147	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
1da177e4	148
af4ea631	149	spin_lock(&wdt->lock);
41dc8b72	150
af4ea631	151	__s3c2410wdt_stop(wdt);
1da177e4	152
af4ea631	153	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
1da177e4 LT	154	wtcon \|= S3C2410_WTCON_ENABLE \| S3C2410_WTCON_DIV128;
	155
	156	if (soft_noboot) {
	157	wtcon \|= S3C2410_WTCON_INTEN;
	158	wtcon &= ~S3C2410_WTCON_RSTEN;
	159	} else {
	160	wtcon &= ~S3C2410_WTCON_INTEN;
	161	wtcon \|= S3C2410_WTCON_RSTEN;
	162	}
	163
af4ea631 LKA	164	DBG("%s: count=0x%08x, wtcon=%08lx\n",
af4ea631 LKA	165	__func__, wdt->count, wtcon);
1da177e4	166
af4ea631 LKA	167	writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
	168	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
	169	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
	170	spin_unlock(&wdt->lock);
25dc46e3 WS	171
25dc46e3 WS	172	return 0;
1da177e4 LT	173	}
1da177e4 LT	174
af4ea631	175	static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
e02f838e	176	{
af4ea631	177	return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
e02f838e BD	178	}
e02f838e BD	179
25dc46e3	180	static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
1da177e4	181	{
af4ea631 LKA	182	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
af4ea631 LKA	183	unsigned long freq = clk_get_rate(wdt->clock);
1da177e4 LT	184	unsigned int count;
	185	unsigned int divisor = 1;
	186	unsigned long wtcon;
	187
	188	if (timeout < 1)
	189	return -EINVAL;
	190
	191	freq /= 128;
	192	count = timeout * freq;
	193
e02f838e	194	DBG("%s: count=%d, timeout=%d, freq=%lu\n",
fa9363c5	195	__func__, count, timeout, freq);
1da177e4 LT	196
	197	/* if the count is bigger than the watchdog register,
	198	then work out what we need to do (and if) we can
	199	actually make this value
	200	*/
	201
	202	if (count >= 0x10000) {
	203	for (divisor = 1; divisor <= 0x100; divisor++) {
	204	if ((count / divisor) < 0x10000)
	205	break;
	206	}
	207
	208	if ((count / divisor) >= 0x10000) {
af4ea631	209	dev_err(wdt->dev, "timeout %d too big\n", timeout);
1da177e4 LT	210	return -EINVAL;
	211	}
	212	}
	213
1da177e4	214	DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
fa9363c5	215	__func__, timeout, divisor, count, count/divisor);
1da177e4 LT	216
1da177e4 LT	217	count /= divisor;
af4ea631	218	wdt->count = count;
1da177e4 LT	219
1da177e4 LT	220	/* update the pre-scaler */
af4ea631	221	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
1da177e4 LT	222	wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
	223	wtcon \|= S3C2410_WTCON_PRESCALE(divisor-1);
	224
af4ea631 LKA	225	writel(count, wdt->reg_base + S3C2410_WTDAT);
af4ea631 LKA	226	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
1da177e4	227
5f2430f5	228	wdd->timeout = (count * divisor) / freq;
0197c1c4	229
1da177e4 LT	230	return 0;
	231	}
	232
a77dba7e	233	#define OPTIONS (WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE)
1da177e4	234
41dc8b72	235	static const struct watchdog_info s3c2410_wdt_ident = {
1da177e4 LT	236	.options = OPTIONS,
	237	.firmware_version = 0,
	238	.identity = "S3C2410 Watchdog",
	239	};
	240
25dc46e3 WS	241	static struct watchdog_ops s3c2410wdt_ops = {
	242	.owner = THIS_MODULE,
	243	.start = s3c2410wdt_start,
	244	.stop = s3c2410wdt_stop,
	245	.ping = s3c2410wdt_keepalive,
	246	.set_timeout = s3c2410wdt_set_heartbeat,
1da177e4 LT	247	};
1da177e4 LT	248
25dc46e3 WS	249	static struct watchdog_device s3c2410_wdd = {
	250	.info = &s3c2410_wdt_ident,
	251	.ops = &s3c2410wdt_ops,
c1fd5f64	252	.timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
1da177e4 LT	253	};
1da177e4 LT	254
1da177e4 LT	255	/* interrupt handler code */
1da177e4 LT	256
7d12e780	257	static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
1da177e4	258	{
af4ea631	259	struct s3c2410_wdt *wdt = platform_get_drvdata(param);
1da177e4	260
af4ea631 LKA	261	dev_info(wdt->dev, "watchdog timer expired (irq)\n");
	262
	263	s3c2410wdt_keepalive(&wdt->wdt_device);
1da177e4 LT	264	return IRQ_HANDLED;
1da177e4 LT	265	}
e02f838e	266
e02f838e BD	267	#ifdef CONFIG_CPU_FREQ
	268
	269	static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
	270	unsigned long val, void *data)
	271	{
	272	int ret;
af4ea631	273	struct s3c2410_wdt *wdt = freq_to_wdt(nb);
e02f838e	274
af4ea631	275	if (!s3c2410wdt_is_running(wdt))
e02f838e BD	276	goto done;
	277
	278	if (val == CPUFREQ_PRECHANGE) {
	279	/* To ensure that over the change we don't cause the
	280	* watchdog to trigger, we perform an keep-alive if
	281	* the watchdog is running.
	282	*/
	283
af4ea631	284	s3c2410wdt_keepalive(&wdt->wdt_device);
e02f838e	285	} else if (val == CPUFREQ_POSTCHANGE) {
af4ea631	286	s3c2410wdt_stop(&wdt->wdt_device);
e02f838e	287
af4ea631 LKA	288	ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
af4ea631 LKA	289	wdt->wdt_device.timeout);
e02f838e BD	290
e02f838e BD	291	if (ret >= 0)
af4ea631	292	s3c2410wdt_start(&wdt->wdt_device);
e02f838e BD	293	else
	294	goto err;
	295	}
	296
	297	done:
	298	return 0;
	299
	300	err:
af4ea631 LKA	301	dev_err(wdt->dev, "cannot set new value for timeout %d\n",
af4ea631 LKA	302	wdt->wdt_device.timeout);
e02f838e BD	303	return ret;
	304	}
	305
af4ea631	306	static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
e02f838e	307	{
af4ea631 LKA	308	wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
	309
	310	return cpufreq_register_notifier(&wdt->freq_transition,
e02f838e BD	311	CPUFREQ_TRANSITION_NOTIFIER);
	312	}
	313
af4ea631	314	static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
e02f838e	315	{
af4ea631 LKA	316	wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
	317
	318	cpufreq_unregister_notifier(&wdt->freq_transition,
e02f838e BD	319	CPUFREQ_TRANSITION_NOTIFIER);
	320	}
	321
	322	#else
af4ea631 LKA	323
af4ea631 LKA	324	static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
e02f838e BD	325	{
	326	return 0;
	327	}
	328
af4ea631	329	static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
e02f838e BD	330	{
	331	}
	332	#endif
	333
2d991a16	334	static int s3c2410wdt_probe(struct platform_device *pdev)
1da177e4	335	{
e8ef92b8	336	struct device *dev;
af4ea631 LKA	337	struct s3c2410_wdt *wdt;
	338	struct resource *wdt_mem;
	339	struct resource *wdt_irq;
46b814d6	340	unsigned int wtcon;
1da177e4 LT	341	int started = 0;
1da177e4 LT	342	int ret;
1da177e4	343
fa9363c5	344	DBG("%s: probe=%p\n", __func__, pdev);
1da177e4	345
e8ef92b8	346	dev = &pdev->dev;
e8ef92b8	347
af4ea631 LKA	348	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	349	if (!wdt)
	350	return -ENOMEM;
	351
	352	wdt->dev = &pdev->dev;
	353	spin_lock_init(&wdt->lock);
	354	wdt->wdt_device = s3c2410_wdd;
1da177e4	355
78d3e00b MH	356	wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	357	if (wdt_irq == NULL) {
	358	dev_err(dev, "no irq resource specified\n");
	359	ret = -ENOENT;
	360	goto err;
	361	}
	362
	363	/* get the memory region for the watchdog timer */
bd5cc119	364	wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af4ea631 LKA	365	wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
	366	if (IS_ERR(wdt->reg_base)) {
	367	ret = PTR_ERR(wdt->reg_base);
04ecc7dc	368	goto err;
1da177e4 LT	369	}
1da177e4 LT	370
af4ea631	371	DBG("probe: mapped reg_base=%p\n", wdt->reg_base);
1da177e4	372
af4ea631 LKA	373	wdt->clock = devm_clk_get(dev, "watchdog");
af4ea631 LKA	374	if (IS_ERR(wdt->clock)) {
e8ef92b8	375	dev_err(dev, "failed to find watchdog clock source\n");
af4ea631	376	ret = PTR_ERR(wdt->clock);
04ecc7dc	377	goto err;
1da177e4 LT	378	}
1da177e4 LT	379
af4ea631	380	clk_prepare_enable(wdt->clock);
1da177e4	381
af4ea631	382	ret = s3c2410wdt_cpufreq_register(wdt);
78d3e00b	383	if (ret < 0) {
3828924a	384	dev_err(dev, "failed to register cpufreq\n");
e02f838e BD	385	goto err_clk;
	386	}
	387
af4ea631 LKA	388	watchdog_set_drvdata(&wdt->wdt_device, wdt);
af4ea631 LKA	389
1da177e4 LT	390	/* see if we can actually set the requested timer margin, and if
	391	* not, try the default value */
	392
af4ea631 LKA	393	watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
	394	ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
	395	wdt->wdt_device.timeout);
	396	if (ret) {
	397	started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
41dc8b72	398	CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
1da177e4	399
41dc8b72 AC	400	if (started == 0)
	401	dev_info(dev,
	402	"tmr_margin value out of range, default %d used\n",
1da177e4	403	CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
41dc8b72	404	else
a77dba7e WVS	405	dev_info(dev, "default timer value is out of range, "
a77dba7e WVS	406	"cannot start\n");
1da177e4 LT	407	}
1da177e4 LT	408
04ecc7dc JH	409	ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
04ecc7dc JH	410	pdev->name, pdev);
78d3e00b MH	411	if (ret != 0) {
	412	dev_err(dev, "failed to install irq (%d)\n", ret);
	413	goto err_cpufreq;
	414	}
	415
af4ea631	416	watchdog_set_nowayout(&wdt->wdt_device, nowayout);
ff0b3cd4	417
af4ea631	418	ret = watchdog_register_device(&wdt->wdt_device);
1da177e4	419	if (ret) {
25dc46e3	420	dev_err(dev, "cannot register watchdog (%d)\n", ret);
04ecc7dc	421	goto err_cpufreq;
1da177e4 LT	422	}
	423
	424	if (tmr_atboot && started == 0) {
e8ef92b8	425	dev_info(dev, "starting watchdog timer\n");
af4ea631	426	s3c2410wdt_start(&wdt->wdt_device);
655516c8 BD	427	} else if (!tmr_atboot) {
	428	/* if we're not enabling the watchdog, then ensure it is
	429	* disabled if it has been left running from the bootloader
	430	* or other source */
	431
af4ea631	432	s3c2410wdt_stop(&wdt->wdt_device);
1da177e4 LT	433	}
1da177e4 LT	434
af4ea631 LKA	435	platform_set_drvdata(pdev, wdt);
af4ea631 LKA	436
46b814d6 BD	437	/* print out a statement of readiness */
46b814d6 BD	438
af4ea631	439	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
46b814d6	440
e8ef92b8	441	dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
46b814d6	442	(wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
20403e84 DA	443	(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
20403e84 DA	444	(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
41dc8b72	445
1da177e4	446	return 0;
0b6dd8a6	447
e02f838e	448	err_cpufreq:
af4ea631	449	s3c2410wdt_cpufreq_deregister(wdt);
e02f838e	450
0b6dd8a6	451	err_clk:
af4ea631 LKA	452	clk_disable_unprepare(wdt->clock);
af4ea631 LKA	453	wdt->clock = NULL;
0b6dd8a6	454
78d3e00b	455	err:
0b6dd8a6	456	return ret;
1da177e4 LT	457	}
1da177e4 LT	458
4b12b896	459	static int s3c2410wdt_remove(struct platform_device *dev)
1da177e4	460	{
af4ea631 LKA	461	struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
	462
	463	watchdog_unregister_device(&wdt->wdt_device);
1da177e4	464
af4ea631	465	s3c2410wdt_cpufreq_deregister(wdt);
1da177e4	466
af4ea631 LKA	467	clk_disable_unprepare(wdt->clock);
af4ea631 LKA	468	wdt->clock = NULL;
1da177e4	469
1da177e4 LT	470	return 0;
	471	}
	472
3ae5eaec	473	static void s3c2410wdt_shutdown(struct platform_device *dev)
94f1e9f3	474	{
af4ea631 LKA	475	struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
	476
	477	s3c2410wdt_stop(&wdt->wdt_device);
94f1e9f3 BD	478	}
94f1e9f3 BD	479
0183984c	480	#ifdef CONFIG_PM_SLEEP
af4bb822	481
0183984c	482	static int s3c2410wdt_suspend(struct device *dev)
af4bb822	483	{
af4ea631 LKA	484	struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
af4ea631 LKA	485
9480e307	486	/* Save watchdog state, and turn it off. */
af4ea631 LKA	487	wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
af4ea631 LKA	488	wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
af4bb822	489
9480e307	490	/* Note that WTCNT doesn't need to be saved. */
af4ea631	491	s3c2410wdt_stop(&wdt->wdt_device);
af4bb822 BD	492
	493	return 0;
	494	}
	495
0183984c	496	static int s3c2410wdt_resume(struct device *dev)
af4bb822	497	{
af4ea631	498	struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
af4bb822	499
af4ea631 LKA	500	/* Restore watchdog state. */
	501	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
	502	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
	503	writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
af4bb822	504
0183984c	505	dev_info(dev, "watchdog %sabled\n",
af4ea631	506	(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
af4bb822 BD	507
	508	return 0;
	509	}
0183984c	510	#endif
af4bb822	511
0183984c JH	512	static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
0183984c JH	513	s3c2410wdt_resume);
af4bb822	514
9487a9cc TA	515	#ifdef CONFIG_OF
	516	static const struct of_device_id s3c2410_wdt_match[] = {
	517	{ .compatible = "samsung,s3c2410-wdt" },
	518	{},
	519	};
	520	MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
9487a9cc	521	#endif
af4bb822	522
3ae5eaec	523	static struct platform_driver s3c2410wdt_driver = {
1da177e4	524	.probe = s3c2410wdt_probe,
82268714	525	.remove = s3c2410wdt_remove,
94f1e9f3	526	.shutdown = s3c2410wdt_shutdown,
3ae5eaec RK	527	.driver = {
	528	.owner = THIS_MODULE,
	529	.name = "s3c2410-wdt",
0183984c	530	.pm = &s3c2410wdt_pm_ops,
3016a552	531	.of_match_table = of_match_ptr(s3c2410_wdt_match),
3ae5eaec	532	},
1da177e4 LT	533	};
1da177e4 LT	534
6b761b29	535	module_platform_driver(s3c2410wdt_driver);
1da177e4	536
af4bb822 BD	537	MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
af4bb822 BD	538	"Dimitry Andric <dimitry.andric@tomtom.com>");
1da177e4 LT	539	MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
1da177e4 LT	540	MODULE_LICENSE("GPL");
f37d193c	541	MODULE_ALIAS("platform:s3c2410-wdt");