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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/timer.h> | |
1da177e4 | 32 | #include <linux/watchdog.h> |
d052d1be | 33 | #include <linux/platform_device.h> |
1da177e4 | 34 | #include <linux/interrupt.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
41dc8b72 AC |
36 | #include <linux/uaccess.h> |
37 | #include <linux/io.h> | |
e02f838e | 38 | #include <linux/cpufreq.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
25dc46e3 | 40 | #include <linux/err.h> |
3016a552 | 41 | #include <linux/of.h> |
4f1f653a LKA |
42 | #include <linux/mfd/syscon.h> |
43 | #include <linux/regmap.h> | |
f286e133 | 44 | #include <linux/delay.h> |
1da177e4 | 45 | |
a8f5401a TF |
46 | #define S3C2410_WTCON 0x00 |
47 | #define S3C2410_WTDAT 0x04 | |
48 | #define S3C2410_WTCNT 0x08 | |
15f416a0 | 49 | #define S3C2410_WTCLRINT 0x0c |
1da177e4 | 50 | |
882dec1f JMC |
51 | #define S3C2410_WTCNT_MAXCNT 0xffff |
52 | ||
a8f5401a TF |
53 | #define S3C2410_WTCON_RSTEN (1 << 0) |
54 | #define S3C2410_WTCON_INTEN (1 << 2) | |
55 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 56 | |
a8f5401a TF |
57 | #define S3C2410_WTCON_DIV16 (0 << 3) |
58 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
59 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
60 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
61 | ||
882dec1f JMC |
62 | #define S3C2410_WTCON_MAXDIV 0x80 |
63 | ||
a8f5401a TF |
64 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) |
65 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
882dec1f | 66 | #define S3C2410_WTCON_PRESCALE_MAX 0xff |
1da177e4 | 67 | |
1da177e4 LT |
68 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) |
69 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
70 | ||
cffc9a60 | 71 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
72 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
73 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
74 | #define QUIRK_HAS_PMU_CONFIG (1 << 0) | |
cffc9a60 | 75 | #define QUIRK_HAS_RST_STAT (1 << 1) |
15f416a0 | 76 | #define QUIRK_HAS_WTCLRINT_REG (1 << 2) |
cffc9a60 DA |
77 | |
78 | /* These quirks require that we have a PMU register map */ | |
79 | #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ | |
80 | QUIRK_HAS_RST_STAT) | |
4f1f653a | 81 | |
86a1e189 | 82 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 83 | static int tmr_margin; |
1da177e4 | 84 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 AC |
85 | static int soft_noboot; |
86 | static int debug; | |
1da177e4 LT |
87 | |
88 | module_param(tmr_margin, int, 0); | |
89 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 90 | module_param(nowayout, bool, 0); |
1da177e4 LT |
91 | module_param(soft_noboot, int, 0); |
92 | module_param(debug, int, 0); | |
93 | ||
76550d32 | 94 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
41dc8b72 AC |
95 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
96 | MODULE_PARM_DESC(tmr_atboot, | |
97 | "Watchdog is started at boot time if set to 1, default=" | |
98 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
99 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
100 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 101 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 RD |
102 | "0 to reboot (default 0)"); |
103 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); | |
1da177e4 | 104 | |
4f1f653a LKA |
105 | /** |
106 | * struct s3c2410_wdt_variant - Per-variant config data | |
107 | * | |
108 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
109 | * timer reset functionality. | |
110 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
111 | * timer reset functionality. | |
112 | * @mask_bit: Bit number for the watchdog timer in the disable register and the | |
113 | * mask reset register. | |
cffc9a60 DA |
114 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
115 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
116 | * reset. | |
4f1f653a LKA |
117 | * @quirks: A bitfield of quirks. |
118 | */ | |
119 | ||
120 | struct s3c2410_wdt_variant { | |
121 | int disable_reg; | |
122 | int mask_reset_reg; | |
123 | int mask_bit; | |
cffc9a60 DA |
124 | int rst_stat_reg; |
125 | int rst_stat_bit; | |
4f1f653a LKA |
126 | u32 quirks; |
127 | }; | |
128 | ||
af4ea631 LKA |
129 | struct s3c2410_wdt { |
130 | struct device *dev; | |
131 | struct clk *clock; | |
132 | void __iomem *reg_base; | |
133 | unsigned int count; | |
134 | spinlock_t lock; | |
135 | unsigned long wtcon_save; | |
136 | unsigned long wtdat_save; | |
137 | struct watchdog_device wdt_device; | |
138 | struct notifier_block freq_transition; | |
4f1f653a LKA |
139 | struct s3c2410_wdt_variant *drv_data; |
140 | struct regmap *pmureg; | |
141 | }; | |
142 | ||
143 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
144 | .quirks = 0 | |
145 | }; | |
146 | ||
147 | #ifdef CONFIG_OF | |
15f416a0 KK |
148 | static const struct s3c2410_wdt_variant drv_data_s3c6410 = { |
149 | .quirks = QUIRK_HAS_WTCLRINT_REG, | |
150 | }; | |
151 | ||
4f1f653a LKA |
152 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { |
153 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
154 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
155 | .mask_bit = 20, | |
cffc9a60 DA |
156 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
157 | .rst_stat_bit = 20, | |
15f416a0 KK |
158 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
159 | | QUIRK_HAS_WTCLRINT_REG, | |
4f1f653a LKA |
160 | }; |
161 | ||
162 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
163 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
164 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
165 | .mask_bit = 0, | |
cffc9a60 DA |
166 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
167 | .rst_stat_bit = 9, | |
15f416a0 KK |
168 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
169 | | QUIRK_HAS_WTCLRINT_REG, | |
4f1f653a LKA |
170 | }; |
171 | ||
2b9366b6 NKC |
172 | static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
173 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
174 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
5476b2b7 | 175 | .mask_bit = 23, |
2b9366b6 NKC |
176 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
177 | .rst_stat_bit = 23, /* A57 WDTRESET */ | |
15f416a0 KK |
178 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
179 | | QUIRK_HAS_WTCLRINT_REG, | |
2b9366b6 NKC |
180 | }; |
181 | ||
4f1f653a LKA |
182 | static const struct of_device_id s3c2410_wdt_match[] = { |
183 | { .compatible = "samsung,s3c2410-wdt", | |
184 | .data = &drv_data_s3c2410 }, | |
15f416a0 KK |
185 | { .compatible = "samsung,s3c6410-wdt", |
186 | .data = &drv_data_s3c6410 }, | |
4f1f653a LKA |
187 | { .compatible = "samsung,exynos5250-wdt", |
188 | .data = &drv_data_exynos5250 }, | |
189 | { .compatible = "samsung,exynos5420-wdt", | |
190 | .data = &drv_data_exynos5420 }, | |
2b9366b6 NKC |
191 | { .compatible = "samsung,exynos7-wdt", |
192 | .data = &drv_data_exynos7 }, | |
4f1f653a | 193 | {}, |
af4ea631 | 194 | }; |
4f1f653a LKA |
195 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
196 | #endif | |
197 | ||
198 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
199 | { | |
200 | .name = "s3c2410-wdt", | |
201 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
202 | }, | |
203 | {} | |
204 | }; | |
205 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 LT |
206 | |
207 | /* watchdog control routines */ | |
208 | ||
27c766aa JP |
209 | #define DBG(fmt, ...) \ |
210 | do { \ | |
211 | if (debug) \ | |
212 | pr_info(fmt, ##__VA_ARGS__); \ | |
213 | } while (0) | |
1da177e4 LT |
214 | |
215 | /* functions */ | |
216 | ||
882dec1f JMC |
217 | static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock) |
218 | { | |
219 | unsigned long freq = clk_get_rate(clock); | |
220 | ||
221 | return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) | |
222 | / S3C2410_WTCON_MAXDIV); | |
223 | } | |
224 | ||
af4ea631 LKA |
225 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
226 | { | |
227 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
228 | } | |
229 | ||
4f1f653a LKA |
230 | static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
231 | { | |
232 | int ret; | |
233 | u32 mask_val = 1 << wdt->drv_data->mask_bit; | |
234 | u32 val = 0; | |
235 | ||
236 | /* No need to do anything if no PMU CONFIG needed */ | |
237 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) | |
238 | return 0; | |
239 | ||
240 | if (mask) | |
241 | val = mask_val; | |
242 | ||
243 | ret = regmap_update_bits(wdt->pmureg, | |
244 | wdt->drv_data->disable_reg, | |
245 | mask_val, val); | |
246 | if (ret < 0) | |
247 | goto error; | |
248 | ||
249 | ret = regmap_update_bits(wdt->pmureg, | |
250 | wdt->drv_data->mask_reset_reg, | |
251 | mask_val, val); | |
252 | error: | |
253 | if (ret < 0) | |
254 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
25dc46e3 | 259 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 260 | { |
af4ea631 LKA |
261 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
262 | ||
263 | spin_lock(&wdt->lock); | |
264 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
265 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
266 | |
267 | return 0; | |
1da177e4 LT |
268 | } |
269 | ||
af4ea631 | 270 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
271 | { |
272 | unsigned long wtcon; | |
273 | ||
af4ea631 | 274 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 275 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 276 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
277 | } |
278 | ||
25dc46e3 | 279 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 280 | { |
af4ea631 LKA |
281 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
282 | ||
283 | spin_lock(&wdt->lock); | |
284 | __s3c2410wdt_stop(wdt); | |
285 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
286 | |
287 | return 0; | |
1da177e4 LT |
288 | } |
289 | ||
25dc46e3 | 290 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
291 | { |
292 | unsigned long wtcon; | |
af4ea631 | 293 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 294 | |
af4ea631 | 295 | spin_lock(&wdt->lock); |
41dc8b72 | 296 | |
af4ea631 | 297 | __s3c2410wdt_stop(wdt); |
1da177e4 | 298 | |
af4ea631 | 299 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
300 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
301 | ||
302 | if (soft_noboot) { | |
303 | wtcon |= S3C2410_WTCON_INTEN; | |
304 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
305 | } else { | |
306 | wtcon &= ~S3C2410_WTCON_INTEN; | |
307 | wtcon |= S3C2410_WTCON_RSTEN; | |
308 | } | |
309 | ||
af4ea631 LKA |
310 | DBG("%s: count=0x%08x, wtcon=%08lx\n", |
311 | __func__, wdt->count, wtcon); | |
1da177e4 | 312 | |
af4ea631 LKA |
313 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
314 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
315 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
316 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
317 | |
318 | return 0; | |
1da177e4 LT |
319 | } |
320 | ||
af4ea631 | 321 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 322 | { |
af4ea631 | 323 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
324 | } |
325 | ||
25dc46e3 | 326 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 327 | { |
af4ea631 LKA |
328 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
329 | unsigned long freq = clk_get_rate(wdt->clock); | |
1da177e4 LT |
330 | unsigned int count; |
331 | unsigned int divisor = 1; | |
332 | unsigned long wtcon; | |
333 | ||
334 | if (timeout < 1) | |
335 | return -EINVAL; | |
336 | ||
17862440 | 337 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
338 | count = timeout * freq; |
339 | ||
e02f838e | 340 | DBG("%s: count=%d, timeout=%d, freq=%lu\n", |
fa9363c5 | 341 | __func__, count, timeout, freq); |
1da177e4 LT |
342 | |
343 | /* if the count is bigger than the watchdog register, | |
344 | then work out what we need to do (and if) we can | |
345 | actually make this value | |
346 | */ | |
347 | ||
348 | if (count >= 0x10000) { | |
17862440 | 349 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 350 | |
17862440 | 351 | if (divisor > 0x100) { |
af4ea631 | 352 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
353 | return -EINVAL; |
354 | } | |
355 | } | |
356 | ||
1da177e4 | 357 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", |
17862440 | 358 | __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor)); |
1da177e4 | 359 | |
17862440 | 360 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 361 | wdt->count = count; |
1da177e4 LT |
362 | |
363 | /* update the pre-scaler */ | |
af4ea631 | 364 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
365 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
366 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
367 | ||
af4ea631 LKA |
368 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
369 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 370 | |
5f2430f5 | 371 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 372 | |
1da177e4 LT |
373 | return 0; |
374 | } | |
375 | ||
4d8b229d GR |
376 | static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, |
377 | void *data) | |
c71f5cd2 DR |
378 | { |
379 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); | |
380 | void __iomem *wdt_base = wdt->reg_base; | |
381 | ||
382 | /* disable watchdog, to be safe */ | |
383 | writel(0, wdt_base + S3C2410_WTCON); | |
384 | ||
385 | /* put initial values into count and data */ | |
386 | writel(0x80, wdt_base + S3C2410_WTCNT); | |
387 | writel(0x80, wdt_base + S3C2410_WTDAT); | |
388 | ||
389 | /* set the watchdog to go and reset... */ | |
390 | writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | | |
391 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), | |
392 | wdt_base + S3C2410_WTCON); | |
393 | ||
394 | /* wait for reset to assert... */ | |
395 | mdelay(500); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
a77dba7e | 400 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 401 | |
41dc8b72 | 402 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
403 | .options = OPTIONS, |
404 | .firmware_version = 0, | |
405 | .identity = "S3C2410 Watchdog", | |
406 | }; | |
407 | ||
25dc46e3 WS |
408 | static struct watchdog_ops s3c2410wdt_ops = { |
409 | .owner = THIS_MODULE, | |
410 | .start = s3c2410wdt_start, | |
411 | .stop = s3c2410wdt_stop, | |
412 | .ping = s3c2410wdt_keepalive, | |
413 | .set_timeout = s3c2410wdt_set_heartbeat, | |
c71f5cd2 | 414 | .restart = s3c2410wdt_restart, |
1da177e4 LT |
415 | }; |
416 | ||
25dc46e3 WS |
417 | static struct watchdog_device s3c2410_wdd = { |
418 | .info = &s3c2410_wdt_ident, | |
419 | .ops = &s3c2410wdt_ops, | |
c1fd5f64 | 420 | .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
421 | }; |
422 | ||
1da177e4 LT |
423 | /* interrupt handler code */ |
424 | ||
7d12e780 | 425 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 426 | { |
af4ea631 | 427 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 428 | |
af4ea631 LKA |
429 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
430 | ||
431 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
15f416a0 KK |
432 | |
433 | if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG) | |
434 | writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); | |
435 | ||
1da177e4 LT |
436 | return IRQ_HANDLED; |
437 | } | |
e02f838e | 438 | |
0f1dd98d | 439 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
440 | |
441 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
442 | unsigned long val, void *data) | |
443 | { | |
444 | int ret; | |
af4ea631 | 445 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 446 | |
af4ea631 | 447 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
448 | goto done; |
449 | ||
450 | if (val == CPUFREQ_PRECHANGE) { | |
451 | /* To ensure that over the change we don't cause the | |
452 | * watchdog to trigger, we perform an keep-alive if | |
453 | * the watchdog is running. | |
454 | */ | |
455 | ||
af4ea631 | 456 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 457 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 458 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 459 | |
af4ea631 LKA |
460 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
461 | wdt->wdt_device.timeout); | |
e02f838e BD |
462 | |
463 | if (ret >= 0) | |
af4ea631 | 464 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
465 | else |
466 | goto err; | |
467 | } | |
468 | ||
469 | done: | |
470 | return 0; | |
471 | ||
472 | err: | |
af4ea631 LKA |
473 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
474 | wdt->wdt_device.timeout); | |
e02f838e BD |
475 | return ret; |
476 | } | |
477 | ||
af4ea631 | 478 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 479 | { |
af4ea631 LKA |
480 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
481 | ||
482 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
483 | CPUFREQ_TRANSITION_NOTIFIER); |
484 | } | |
485 | ||
af4ea631 | 486 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 487 | { |
af4ea631 LKA |
488 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
489 | ||
490 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
491 | CPUFREQ_TRANSITION_NOTIFIER); |
492 | } | |
493 | ||
494 | #else | |
af4ea631 LKA |
495 | |
496 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
497 | { |
498 | return 0; | |
499 | } | |
500 | ||
af4ea631 | 501 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
502 | { |
503 | } | |
504 | #endif | |
505 | ||
cffc9a60 DA |
506 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
507 | { | |
508 | unsigned int rst_stat; | |
509 | int ret; | |
510 | ||
511 | if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) | |
512 | return 0; | |
513 | ||
514 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
515 | if (ret) | |
516 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
517 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
518 | return WDIOF_CARDRESET; | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
4f1f653a LKA |
523 | /* s3c2410_get_wdt_driver_data */ |
524 | static inline struct s3c2410_wdt_variant * | |
525 | get_wdt_drv_data(struct platform_device *pdev) | |
526 | { | |
527 | if (pdev->dev.of_node) { | |
528 | const struct of_device_id *match; | |
529 | match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node); | |
530 | return (struct s3c2410_wdt_variant *)match->data; | |
531 | } else { | |
532 | return (struct s3c2410_wdt_variant *) | |
533 | platform_get_device_id(pdev)->driver_data; | |
534 | } | |
535 | } | |
536 | ||
2d991a16 | 537 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 538 | { |
e8ef92b8 | 539 | struct device *dev; |
af4ea631 LKA |
540 | struct s3c2410_wdt *wdt; |
541 | struct resource *wdt_mem; | |
542 | struct resource *wdt_irq; | |
46b814d6 | 543 | unsigned int wtcon; |
1da177e4 LT |
544 | int started = 0; |
545 | int ret; | |
1da177e4 | 546 | |
fa9363c5 | 547 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 548 | |
e8ef92b8 | 549 | dev = &pdev->dev; |
e8ef92b8 | 550 | |
af4ea631 LKA |
551 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
552 | if (!wdt) | |
553 | return -ENOMEM; | |
554 | ||
555 | wdt->dev = &pdev->dev; | |
556 | spin_lock_init(&wdt->lock); | |
557 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 558 | |
4f1f653a | 559 | wdt->drv_data = get_wdt_drv_data(pdev); |
cffc9a60 | 560 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
561 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
562 | "samsung,syscon-phandle"); | |
563 | if (IS_ERR(wdt->pmureg)) { | |
564 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
565 | return PTR_ERR(wdt->pmureg); | |
566 | } | |
567 | } | |
568 | ||
78d3e00b MH |
569 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
570 | if (wdt_irq == NULL) { | |
571 | dev_err(dev, "no irq resource specified\n"); | |
572 | ret = -ENOENT; | |
573 | goto err; | |
574 | } | |
575 | ||
576 | /* get the memory region for the watchdog timer */ | |
bd5cc119 | 577 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
af4ea631 LKA |
578 | wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); |
579 | if (IS_ERR(wdt->reg_base)) { | |
580 | ret = PTR_ERR(wdt->reg_base); | |
04ecc7dc | 581 | goto err; |
1da177e4 LT |
582 | } |
583 | ||
af4ea631 | 584 | DBG("probe: mapped reg_base=%p\n", wdt->reg_base); |
1da177e4 | 585 | |
af4ea631 LKA |
586 | wdt->clock = devm_clk_get(dev, "watchdog"); |
587 | if (IS_ERR(wdt->clock)) { | |
e8ef92b8 | 588 | dev_err(dev, "failed to find watchdog clock source\n"); |
af4ea631 | 589 | ret = PTR_ERR(wdt->clock); |
04ecc7dc | 590 | goto err; |
1da177e4 LT |
591 | } |
592 | ||
01b6af91 SK |
593 | ret = clk_prepare_enable(wdt->clock); |
594 | if (ret < 0) { | |
595 | dev_err(dev, "failed to enable clock\n"); | |
596 | return ret; | |
597 | } | |
1da177e4 | 598 | |
882dec1f JMC |
599 | wdt->wdt_device.min_timeout = 1; |
600 | wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock); | |
601 | ||
af4ea631 | 602 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 603 | if (ret < 0) { |
3828924a | 604 | dev_err(dev, "failed to register cpufreq\n"); |
e02f838e BD |
605 | goto err_clk; |
606 | } | |
607 | ||
af4ea631 LKA |
608 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
609 | ||
1da177e4 LT |
610 | /* see if we can actually set the requested timer margin, and if |
611 | * not, try the default value */ | |
612 | ||
af4ea631 LKA |
613 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); |
614 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
615 | wdt->wdt_device.timeout); | |
616 | if (ret) { | |
617 | started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
41dc8b72 | 618 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 619 | |
41dc8b72 AC |
620 | if (started == 0) |
621 | dev_info(dev, | |
622 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 623 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 624 | else |
a77dba7e WVS |
625 | dev_info(dev, "default timer value is out of range, " |
626 | "cannot start\n"); | |
1da177e4 LT |
627 | } |
628 | ||
04ecc7dc JH |
629 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
630 | pdev->name, pdev); | |
78d3e00b MH |
631 | if (ret != 0) { |
632 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
633 | goto err_cpufreq; | |
634 | } | |
635 | ||
af4ea631 | 636 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
c71f5cd2 | 637 | watchdog_set_restart_priority(&wdt->wdt_device, 128); |
ff0b3cd4 | 638 | |
cffc9a60 | 639 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
6551881c | 640 | wdt->wdt_device.parent = &pdev->dev; |
cffc9a60 | 641 | |
af4ea631 | 642 | ret = watchdog_register_device(&wdt->wdt_device); |
1da177e4 | 643 | if (ret) { |
25dc46e3 | 644 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 645 | goto err_cpufreq; |
1da177e4 LT |
646 | } |
647 | ||
4f1f653a LKA |
648 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
649 | if (ret < 0) | |
650 | goto err_unregister; | |
651 | ||
1da177e4 | 652 | if (tmr_atboot && started == 0) { |
e8ef92b8 | 653 | dev_info(dev, "starting watchdog timer\n"); |
af4ea631 | 654 | s3c2410wdt_start(&wdt->wdt_device); |
655516c8 BD |
655 | } else if (!tmr_atboot) { |
656 | /* if we're not enabling the watchdog, then ensure it is | |
657 | * disabled if it has been left running from the bootloader | |
658 | * or other source */ | |
659 | ||
af4ea631 | 660 | s3c2410wdt_stop(&wdt->wdt_device); |
1da177e4 LT |
661 | } |
662 | ||
af4ea631 LKA |
663 | platform_set_drvdata(pdev, wdt); |
664 | ||
46b814d6 BD |
665 | /* print out a statement of readiness */ |
666 | ||
af4ea631 | 667 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 668 | |
e8ef92b8 | 669 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 670 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
671 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
672 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 673 | |
1da177e4 | 674 | return 0; |
0b6dd8a6 | 675 | |
4f1f653a LKA |
676 | err_unregister: |
677 | watchdog_unregister_device(&wdt->wdt_device); | |
678 | ||
e02f838e | 679 | err_cpufreq: |
af4ea631 | 680 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 681 | |
0b6dd8a6 | 682 | err_clk: |
af4ea631 | 683 | clk_disable_unprepare(wdt->clock); |
0b6dd8a6 | 684 | |
78d3e00b | 685 | err: |
0b6dd8a6 | 686 | return ret; |
1da177e4 LT |
687 | } |
688 | ||
4b12b896 | 689 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 690 | { |
4f1f653a | 691 | int ret; |
af4ea631 LKA |
692 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
693 | ||
4f1f653a LKA |
694 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
695 | if (ret < 0) | |
696 | return ret; | |
697 | ||
af4ea631 | 698 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 699 | |
af4ea631 | 700 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 701 | |
af4ea631 | 702 | clk_disable_unprepare(wdt->clock); |
1da177e4 | 703 | |
1da177e4 LT |
704 | return 0; |
705 | } | |
706 | ||
3ae5eaec | 707 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 708 | { |
af4ea631 LKA |
709 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
710 | ||
4f1f653a LKA |
711 | s3c2410wdt_mask_and_disable_reset(wdt, true); |
712 | ||
af4ea631 | 713 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
714 | } |
715 | ||
0183984c | 716 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 717 | |
0183984c | 718 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 719 | { |
4f1f653a | 720 | int ret; |
af4ea631 LKA |
721 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
722 | ||
9480e307 | 723 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
724 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
725 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 726 | |
4f1f653a LKA |
727 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
728 | if (ret < 0) | |
729 | return ret; | |
730 | ||
9480e307 | 731 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 732 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
733 | |
734 | return 0; | |
735 | } | |
736 | ||
0183984c | 737 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 738 | { |
4f1f653a | 739 | int ret; |
af4ea631 | 740 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 741 | |
af4ea631 LKA |
742 | /* Restore watchdog state. */ |
743 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
744 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
745 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 746 | |
4f1f653a LKA |
747 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
748 | if (ret < 0) | |
749 | return ret; | |
750 | ||
0183984c | 751 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 752 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
753 | |
754 | return 0; | |
755 | } | |
0183984c | 756 | #endif |
af4bb822 | 757 | |
0183984c JH |
758 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
759 | s3c2410wdt_resume); | |
af4bb822 | 760 | |
3ae5eaec | 761 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 762 | .probe = s3c2410wdt_probe, |
82268714 | 763 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 764 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 765 | .id_table = s3c2410_wdt_ids, |
3ae5eaec | 766 | .driver = { |
3ae5eaec | 767 | .name = "s3c2410-wdt", |
0183984c | 768 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 769 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 770 | }, |
1da177e4 LT |
771 | }; |
772 | ||
6b761b29 | 773 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 774 | |
af4bb822 BD |
775 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
776 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
777 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
778 | MODULE_LICENSE("GPL"); |