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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/moduleparam.h> | |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/timer.h> | |
30 | #include <linux/miscdevice.h> | |
31 | #include <linux/watchdog.h> | |
32 | #include <linux/fs.h> | |
1da177e4 | 33 | #include <linux/init.h> |
d052d1be | 34 | #include <linux/platform_device.h> |
1da177e4 | 35 | #include <linux/interrupt.h> |
f8ce2547 | 36 | #include <linux/clk.h> |
41dc8b72 AC |
37 | #include <linux/uaccess.h> |
38 | #include <linux/io.h> | |
1da177e4 | 39 | |
a09e64fb | 40 | #include <mach/map.h> |
1da177e4 | 41 | |
b430708a BD |
42 | #undef S3C_VA_WATCHDOG |
43 | #define S3C_VA_WATCHDOG (0) | |
1da177e4 | 44 | |
180ee700 | 45 | #include <plat/regs-watchdog.h> |
1da177e4 LT |
46 | |
47 | #define PFX "s3c2410-wdt: " | |
48 | ||
49 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) | |
50 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
51 | ||
25ff3780 | 52 | static int nowayout = WATCHDOG_NOWAYOUT; |
1da177e4 LT |
53 | static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME; |
54 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; | |
41dc8b72 AC |
55 | static int soft_noboot; |
56 | static int debug; | |
1da177e4 LT |
57 | |
58 | module_param(tmr_margin, int, 0); | |
59 | module_param(tmr_atboot, int, 0); | |
60 | module_param(nowayout, int, 0); | |
61 | module_param(soft_noboot, int, 0); | |
62 | module_param(debug, int, 0); | |
63 | ||
41dc8b72 AC |
64 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default=" |
65 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); | |
66 | MODULE_PARM_DESC(tmr_atboot, | |
67 | "Watchdog is started at boot time if set to 1, default=" | |
68 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
69 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
70 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e WVS |
71 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
72 | "0 to reboot (default depends on ONLY_TESTING)"); | |
1da177e4 LT |
73 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)"); |
74 | ||
41dc8b72 | 75 | static unsigned long open_lock; |
e8ef92b8 | 76 | static struct device *wdt_dev; /* platform device attached to */ |
1da177e4 LT |
77 | static struct resource *wdt_mem; |
78 | static struct resource *wdt_irq; | |
79 | static struct clk *wdt_clock; | |
80 | static void __iomem *wdt_base; | |
81 | static unsigned int wdt_count; | |
a77dba7e | 82 | static char expect_close; |
41dc8b72 | 83 | static DEFINE_SPINLOCK(wdt_lock); |
1da177e4 LT |
84 | |
85 | /* watchdog control routines */ | |
86 | ||
87 | #define DBG(msg...) do { \ | |
88 | if (debug) \ | |
89 | printk(KERN_INFO msg); \ | |
41dc8b72 | 90 | } while (0) |
1da177e4 LT |
91 | |
92 | /* functions */ | |
93 | ||
41dc8b72 | 94 | static void s3c2410wdt_keepalive(void) |
1da177e4 | 95 | { |
41dc8b72 | 96 | spin_lock(&wdt_lock); |
1da177e4 | 97 | writel(wdt_count, wdt_base + S3C2410_WTCNT); |
41dc8b72 | 98 | spin_unlock(&wdt_lock); |
1da177e4 LT |
99 | } |
100 | ||
41dc8b72 AC |
101 | static void __s3c2410wdt_stop(void) |
102 | { | |
103 | unsigned long wtcon; | |
104 | ||
105 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
106 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); | |
107 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
108 | } | |
109 | ||
110 | static void s3c2410wdt_stop(void) | |
111 | { | |
112 | spin_lock(&wdt_lock); | |
113 | __s3c2410wdt_stop(); | |
114 | spin_unlock(&wdt_lock); | |
1da177e4 LT |
115 | } |
116 | ||
41dc8b72 | 117 | static void s3c2410wdt_start(void) |
1da177e4 LT |
118 | { |
119 | unsigned long wtcon; | |
120 | ||
41dc8b72 AC |
121 | spin_lock(&wdt_lock); |
122 | ||
123 | __s3c2410wdt_stop(); | |
1da177e4 LT |
124 | |
125 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
126 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; | |
127 | ||
128 | if (soft_noboot) { | |
129 | wtcon |= S3C2410_WTCON_INTEN; | |
130 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
131 | } else { | |
132 | wtcon &= ~S3C2410_WTCON_INTEN; | |
133 | wtcon |= S3C2410_WTCON_RSTEN; | |
134 | } | |
135 | ||
136 | DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n", | |
fa9363c5 | 137 | __func__, wdt_count, wtcon); |
1da177e4 LT |
138 | |
139 | writel(wdt_count, wdt_base + S3C2410_WTDAT); | |
140 | writel(wdt_count, wdt_base + S3C2410_WTCNT); | |
141 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
41dc8b72 | 142 | spin_unlock(&wdt_lock); |
1da177e4 LT |
143 | } |
144 | ||
145 | static int s3c2410wdt_set_heartbeat(int timeout) | |
146 | { | |
147 | unsigned int freq = clk_get_rate(wdt_clock); | |
148 | unsigned int count; | |
149 | unsigned int divisor = 1; | |
150 | unsigned long wtcon; | |
151 | ||
152 | if (timeout < 1) | |
153 | return -EINVAL; | |
154 | ||
155 | freq /= 128; | |
156 | count = timeout * freq; | |
157 | ||
158 | DBG("%s: count=%d, timeout=%d, freq=%d\n", | |
fa9363c5 | 159 | __func__, count, timeout, freq); |
1da177e4 LT |
160 | |
161 | /* if the count is bigger than the watchdog register, | |
162 | then work out what we need to do (and if) we can | |
163 | actually make this value | |
164 | */ | |
165 | ||
166 | if (count >= 0x10000) { | |
167 | for (divisor = 1; divisor <= 0x100; divisor++) { | |
168 | if ((count / divisor) < 0x10000) | |
169 | break; | |
170 | } | |
171 | ||
172 | if ((count / divisor) >= 0x10000) { | |
e8ef92b8 | 173 | dev_err(wdt_dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
174 | return -EINVAL; |
175 | } | |
176 | } | |
177 | ||
178 | tmr_margin = timeout; | |
179 | ||
180 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", | |
fa9363c5 | 181 | __func__, timeout, divisor, count, count/divisor); |
1da177e4 LT |
182 | |
183 | count /= divisor; | |
184 | wdt_count = count; | |
185 | ||
186 | /* update the pre-scaler */ | |
187 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
188 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; | |
189 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
190 | ||
191 | writel(count, wdt_base + S3C2410_WTDAT); | |
192 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /* | |
198 | * /dev/watchdog handling | |
199 | */ | |
200 | ||
201 | static int s3c2410wdt_open(struct inode *inode, struct file *file) | |
202 | { | |
41dc8b72 | 203 | if (test_and_set_bit(0, &open_lock)) |
1da177e4 LT |
204 | return -EBUSY; |
205 | ||
25ff3780 | 206 | if (nowayout) |
1da177e4 | 207 | __module_get(THIS_MODULE); |
25ff3780 | 208 | |
a77dba7e | 209 | expect_close = 0; |
1da177e4 LT |
210 | |
211 | /* start the timer */ | |
212 | s3c2410wdt_start(); | |
213 | return nonseekable_open(inode, file); | |
214 | } | |
215 | ||
216 | static int s3c2410wdt_release(struct inode *inode, struct file *file) | |
217 | { | |
218 | /* | |
219 | * Shut off the timer. | |
220 | * Lock it in if it's a module and we set nowayout | |
221 | */ | |
25ff3780 | 222 | |
a77dba7e | 223 | if (expect_close == 42) |
1da177e4 | 224 | s3c2410wdt_stop(); |
41dc8b72 | 225 | else { |
e8ef92b8 | 226 | dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n"); |
1da177e4 LT |
227 | s3c2410wdt_keepalive(); |
228 | } | |
a77dba7e | 229 | expect_close = 0; |
41dc8b72 | 230 | clear_bit(0, &open_lock); |
1da177e4 LT |
231 | return 0; |
232 | } | |
233 | ||
234 | static ssize_t s3c2410wdt_write(struct file *file, const char __user *data, | |
235 | size_t len, loff_t *ppos) | |
236 | { | |
237 | /* | |
238 | * Refresh the timer. | |
239 | */ | |
41dc8b72 | 240 | if (len) { |
1da177e4 LT |
241 | if (!nowayout) { |
242 | size_t i; | |
243 | ||
244 | /* In case it was set long ago */ | |
a77dba7e | 245 | expect_close = 0; |
1da177e4 LT |
246 | |
247 | for (i = 0; i != len; i++) { | |
248 | char c; | |
249 | ||
250 | if (get_user(c, data + i)) | |
251 | return -EFAULT; | |
252 | if (c == 'V') | |
a77dba7e | 253 | expect_close = 42; |
1da177e4 LT |
254 | } |
255 | } | |
1da177e4 LT |
256 | s3c2410wdt_keepalive(); |
257 | } | |
258 | return len; | |
259 | } | |
260 | ||
a77dba7e | 261 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 262 | |
41dc8b72 | 263 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
264 | .options = OPTIONS, |
265 | .firmware_version = 0, | |
266 | .identity = "S3C2410 Watchdog", | |
267 | }; | |
268 | ||
269 | ||
41dc8b72 AC |
270 | static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd, |
271 | unsigned long arg) | |
1da177e4 LT |
272 | { |
273 | void __user *argp = (void __user *)arg; | |
274 | int __user *p = argp; | |
275 | int new_margin; | |
276 | ||
277 | switch (cmd) { | |
41dc8b72 AC |
278 | case WDIOC_GETSUPPORT: |
279 | return copy_to_user(argp, &s3c2410_wdt_ident, | |
280 | sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0; | |
281 | case WDIOC_GETSTATUS: | |
282 | case WDIOC_GETBOOTSTATUS: | |
283 | return put_user(0, p); | |
284 | case WDIOC_KEEPALIVE: | |
285 | s3c2410wdt_keepalive(); | |
286 | return 0; | |
287 | case WDIOC_SETTIMEOUT: | |
288 | if (get_user(new_margin, p)) | |
289 | return -EFAULT; | |
290 | if (s3c2410wdt_set_heartbeat(new_margin)) | |
291 | return -EINVAL; | |
292 | s3c2410wdt_keepalive(); | |
293 | return put_user(tmr_margin, p); | |
294 | case WDIOC_GETTIMEOUT: | |
295 | return put_user(tmr_margin, p); | |
0c06090c WVS |
296 | default: |
297 | return -ENOTTY; | |
1da177e4 LT |
298 | } |
299 | } | |
300 | ||
1da177e4 LT |
301 | /* kernel interface */ |
302 | ||
62322d25 | 303 | static const struct file_operations s3c2410wdt_fops = { |
1da177e4 LT |
304 | .owner = THIS_MODULE, |
305 | .llseek = no_llseek, | |
306 | .write = s3c2410wdt_write, | |
41dc8b72 | 307 | .unlocked_ioctl = s3c2410wdt_ioctl, |
1da177e4 LT |
308 | .open = s3c2410wdt_open, |
309 | .release = s3c2410wdt_release, | |
310 | }; | |
311 | ||
312 | static struct miscdevice s3c2410wdt_miscdev = { | |
313 | .minor = WATCHDOG_MINOR, | |
314 | .name = "watchdog", | |
315 | .fops = &s3c2410wdt_fops, | |
316 | }; | |
317 | ||
1da177e4 LT |
318 | /* interrupt handler code */ |
319 | ||
7d12e780 | 320 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 321 | { |
e8ef92b8 | 322 | dev_info(wdt_dev, "watchdog timer expired (irq)\n"); |
1da177e4 LT |
323 | |
324 | s3c2410wdt_keepalive(); | |
325 | return IRQ_HANDLED; | |
326 | } | |
327 | /* device interface */ | |
328 | ||
a77dba7e | 329 | static int __devinit s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 330 | { |
1da177e4 | 331 | struct resource *res; |
e8ef92b8 | 332 | struct device *dev; |
46b814d6 | 333 | unsigned int wtcon; |
1da177e4 LT |
334 | int started = 0; |
335 | int ret; | |
336 | int size; | |
337 | ||
fa9363c5 | 338 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 339 | |
e8ef92b8 BD |
340 | dev = &pdev->dev; |
341 | wdt_dev = &pdev->dev; | |
342 | ||
1da177e4 LT |
343 | /* get the memory region for the watchdog timer */ |
344 | ||
345 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
346 | if (res == NULL) { | |
e8ef92b8 | 347 | dev_err(dev, "no memory resource specified\n"); |
1da177e4 LT |
348 | return -ENOENT; |
349 | } | |
350 | ||
0e65fb29 | 351 | size = (res->end - res->start) + 1; |
1da177e4 LT |
352 | wdt_mem = request_mem_region(res->start, size, pdev->name); |
353 | if (wdt_mem == NULL) { | |
e8ef92b8 | 354 | dev_err(dev, "failed to get memory region\n"); |
0b6dd8a6 BD |
355 | ret = -ENOENT; |
356 | goto err_req; | |
1da177e4 LT |
357 | } |
358 | ||
359 | wdt_base = ioremap(res->start, size); | |
b4253f8f | 360 | if (wdt_base == NULL) { |
e8ef92b8 | 361 | dev_err(dev, "failed to ioremap() region\n"); |
0b6dd8a6 BD |
362 | ret = -EINVAL; |
363 | goto err_req; | |
1da177e4 LT |
364 | } |
365 | ||
366 | DBG("probe: mapped wdt_base=%p\n", wdt_base); | |
367 | ||
62be0741 AP |
368 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
369 | if (wdt_irq == NULL) { | |
e8ef92b8 | 370 | dev_err(dev, "no irq resource specified\n"); |
0b6dd8a6 BD |
371 | ret = -ENOENT; |
372 | goto err_map; | |
1da177e4 LT |
373 | } |
374 | ||
62be0741 | 375 | ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev); |
1da177e4 | 376 | if (ret != 0) { |
e8ef92b8 | 377 | dev_err(dev, "failed to install irq (%d)\n", ret); |
0b6dd8a6 | 378 | goto err_map; |
1da177e4 LT |
379 | } |
380 | ||
3ae5eaec | 381 | wdt_clock = clk_get(&pdev->dev, "watchdog"); |
9cd44619 | 382 | if (IS_ERR(wdt_clock)) { |
e8ef92b8 | 383 | dev_err(dev, "failed to find watchdog clock source\n"); |
9cd44619 | 384 | ret = PTR_ERR(wdt_clock); |
0b6dd8a6 | 385 | goto err_irq; |
1da177e4 LT |
386 | } |
387 | ||
1da177e4 LT |
388 | clk_enable(wdt_clock); |
389 | ||
390 | /* see if we can actually set the requested timer margin, and if | |
391 | * not, try the default value */ | |
392 | ||
393 | if (s3c2410wdt_set_heartbeat(tmr_margin)) { | |
41dc8b72 AC |
394 | started = s3c2410wdt_set_heartbeat( |
395 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); | |
1da177e4 | 396 | |
41dc8b72 AC |
397 | if (started == 0) |
398 | dev_info(dev, | |
399 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 400 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 401 | else |
a77dba7e WVS |
402 | dev_info(dev, "default timer value is out of range, " |
403 | "cannot start\n"); | |
1da177e4 LT |
404 | } |
405 | ||
1da177e4 LT |
406 | ret = misc_register(&s3c2410wdt_miscdev); |
407 | if (ret) { | |
e8ef92b8 | 408 | dev_err(dev, "cannot register miscdev on minor=%d (%d)\n", |
1da177e4 | 409 | WATCHDOG_MINOR, ret); |
0b6dd8a6 | 410 | goto err_clk; |
1da177e4 LT |
411 | } |
412 | ||
413 | if (tmr_atboot && started == 0) { | |
e8ef92b8 | 414 | dev_info(dev, "starting watchdog timer\n"); |
1da177e4 | 415 | s3c2410wdt_start(); |
655516c8 BD |
416 | } else if (!tmr_atboot) { |
417 | /* if we're not enabling the watchdog, then ensure it is | |
418 | * disabled if it has been left running from the bootloader | |
419 | * or other source */ | |
420 | ||
421 | s3c2410wdt_stop(); | |
1da177e4 LT |
422 | } |
423 | ||
46b814d6 BD |
424 | /* print out a statement of readiness */ |
425 | ||
426 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
427 | ||
e8ef92b8 | 428 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 BD |
429 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
430 | (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis", | |
431 | (wtcon & S3C2410_WTCON_INTEN) ? "" : "en"); | |
41dc8b72 | 432 | |
1da177e4 | 433 | return 0; |
0b6dd8a6 BD |
434 | |
435 | err_clk: | |
436 | clk_disable(wdt_clock); | |
437 | clk_put(wdt_clock); | |
438 | ||
439 | err_irq: | |
440 | free_irq(wdt_irq->start, pdev); | |
441 | ||
442 | err_map: | |
443 | iounmap(wdt_base); | |
444 | ||
445 | err_req: | |
446 | release_resource(wdt_mem); | |
447 | kfree(wdt_mem); | |
448 | ||
449 | return ret; | |
1da177e4 LT |
450 | } |
451 | ||
a77dba7e | 452 | static int __devexit s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 453 | { |
0b6dd8a6 BD |
454 | release_resource(wdt_mem); |
455 | kfree(wdt_mem); | |
456 | wdt_mem = NULL; | |
1da177e4 | 457 | |
0b6dd8a6 BD |
458 | free_irq(wdt_irq->start, dev); |
459 | wdt_irq = NULL; | |
1da177e4 | 460 | |
0b6dd8a6 BD |
461 | clk_disable(wdt_clock); |
462 | clk_put(wdt_clock); | |
463 | wdt_clock = NULL; | |
1da177e4 | 464 | |
e34477e9 | 465 | iounmap(wdt_base); |
1da177e4 LT |
466 | misc_deregister(&s3c2410wdt_miscdev); |
467 | return 0; | |
468 | } | |
469 | ||
3ae5eaec | 470 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 471 | { |
41dc8b72 | 472 | s3c2410wdt_stop(); |
94f1e9f3 BD |
473 | } |
474 | ||
af4bb822 BD |
475 | #ifdef CONFIG_PM |
476 | ||
477 | static unsigned long wtcon_save; | |
478 | static unsigned long wtdat_save; | |
479 | ||
3ae5eaec | 480 | static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state) |
af4bb822 | 481 | { |
9480e307 RK |
482 | /* Save watchdog state, and turn it off. */ |
483 | wtcon_save = readl(wdt_base + S3C2410_WTCON); | |
484 | wtdat_save = readl(wdt_base + S3C2410_WTDAT); | |
af4bb822 | 485 | |
9480e307 RK |
486 | /* Note that WTCNT doesn't need to be saved. */ |
487 | s3c2410wdt_stop(); | |
af4bb822 BD |
488 | |
489 | return 0; | |
490 | } | |
491 | ||
3ae5eaec | 492 | static int s3c2410wdt_resume(struct platform_device *dev) |
af4bb822 | 493 | { |
9480e307 | 494 | /* Restore watchdog state. */ |
af4bb822 | 495 | |
9480e307 RK |
496 | writel(wtdat_save, wdt_base + S3C2410_WTDAT); |
497 | writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */ | |
498 | writel(wtcon_save, wdt_base + S3C2410_WTCON); | |
af4bb822 | 499 | |
9480e307 RK |
500 | printk(KERN_INFO PFX "watchdog %sabled\n", |
501 | (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); | |
af4bb822 BD |
502 | |
503 | return 0; | |
504 | } | |
505 | ||
506 | #else | |
507 | #define s3c2410wdt_suspend NULL | |
508 | #define s3c2410wdt_resume NULL | |
509 | #endif /* CONFIG_PM */ | |
510 | ||
511 | ||
3ae5eaec | 512 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 513 | .probe = s3c2410wdt_probe, |
a77dba7e | 514 | .remove = __devexit_p(s3c2410wdt_remove), |
94f1e9f3 | 515 | .shutdown = s3c2410wdt_shutdown, |
af4bb822 BD |
516 | .suspend = s3c2410wdt_suspend, |
517 | .resume = s3c2410wdt_resume, | |
3ae5eaec RK |
518 | .driver = { |
519 | .owner = THIS_MODULE, | |
520 | .name = "s3c2410-wdt", | |
521 | }, | |
1da177e4 LT |
522 | }; |
523 | ||
524 | ||
41dc8b72 AC |
525 | static char banner[] __initdata = |
526 | KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n"; | |
1da177e4 LT |
527 | |
528 | static int __init watchdog_init(void) | |
529 | { | |
530 | printk(banner); | |
3ae5eaec | 531 | return platform_driver_register(&s3c2410wdt_driver); |
1da177e4 LT |
532 | } |
533 | ||
534 | static void __exit watchdog_exit(void) | |
535 | { | |
3ae5eaec | 536 | platform_driver_unregister(&s3c2410wdt_driver); |
1da177e4 LT |
537 | } |
538 | ||
539 | module_init(watchdog_init); | |
540 | module_exit(watchdog_exit); | |
541 | ||
af4bb822 BD |
542 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
543 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
544 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
545 | MODULE_LICENSE("GPL"); | |
546 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
f37d193c | 547 | MODULE_ALIAS("platform:s3c2410-wdt"); |