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CommitLineData
1da177e4
LT
1/* linux/drivers/char/watchdog/s3c2410_wdt.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Watchdog Timer Support
7 *
8 * Based on, softdog.c by Alan Cox,
29fa0586 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1da177e4
LT
24*/
25
27c766aa
JP
26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
1da177e4
LT
28#include <linux/module.h>
29#include <linux/moduleparam.h>
1da177e4
LT
30#include <linux/types.h>
31#include <linux/timer.h>
25dc46e3 32#include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */
1da177e4 33#include <linux/watchdog.h>
1da177e4 34#include <linux/init.h>
d052d1be 35#include <linux/platform_device.h>
1da177e4 36#include <linux/interrupt.h>
f8ce2547 37#include <linux/clk.h>
41dc8b72
AC
38#include <linux/uaccess.h>
39#include <linux/io.h>
e02f838e 40#include <linux/cpufreq.h>
5a0e3ad6 41#include <linux/slab.h>
25dc46e3 42#include <linux/err.h>
1da177e4 43
a09e64fb 44#include <mach/map.h>
1da177e4 45
b430708a
BD
46#undef S3C_VA_WATCHDOG
47#define S3C_VA_WATCHDOG (0)
1da177e4 48
180ee700 49#include <plat/regs-watchdog.h>
1da177e4 50
1da177e4
LT
51#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
52#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
53
25ff3780 54static int nowayout = WATCHDOG_NOWAYOUT;
1da177e4
LT
55static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
56static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
41dc8b72
AC
57static int soft_noboot;
58static int debug;
1da177e4
LT
59
60module_param(tmr_margin, int, 0);
61module_param(tmr_atboot, int, 0);
62module_param(nowayout, int, 0);
63module_param(soft_noboot, int, 0);
64module_param(debug, int, 0);
65
76550d32 66MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
41dc8b72
AC
67 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
68MODULE_PARM_DESC(tmr_atboot,
69 "Watchdog is started at boot time if set to 1, default="
70 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
71MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
72 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
a77dba7e 73MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
76550d32
RD
74 "0 to reboot (default 0)");
75MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
1da177e4 76
e8ef92b8 77static struct device *wdt_dev; /* platform device attached to */
1da177e4
LT
78static struct resource *wdt_mem;
79static struct resource *wdt_irq;
80static struct clk *wdt_clock;
81static void __iomem *wdt_base;
82static unsigned int wdt_count;
41dc8b72 83static DEFINE_SPINLOCK(wdt_lock);
1da177e4
LT
84
85/* watchdog control routines */
86
27c766aa
JP
87#define DBG(fmt, ...) \
88do { \
89 if (debug) \
90 pr_info(fmt, ##__VA_ARGS__); \
91} while (0)
1da177e4
LT
92
93/* functions */
94
25dc46e3 95static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
1da177e4 96{
41dc8b72 97 spin_lock(&wdt_lock);
1da177e4 98 writel(wdt_count, wdt_base + S3C2410_WTCNT);
41dc8b72 99 spin_unlock(&wdt_lock);
25dc46e3
WS
100
101 return 0;
1da177e4
LT
102}
103
41dc8b72
AC
104static void __s3c2410wdt_stop(void)
105{
106 unsigned long wtcon;
107
108 wtcon = readl(wdt_base + S3C2410_WTCON);
109 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
110 writel(wtcon, wdt_base + S3C2410_WTCON);
111}
112
25dc46e3 113static int s3c2410wdt_stop(struct watchdog_device *wdd)
41dc8b72
AC
114{
115 spin_lock(&wdt_lock);
116 __s3c2410wdt_stop();
117 spin_unlock(&wdt_lock);
25dc46e3
WS
118
119 return 0;
1da177e4
LT
120}
121
25dc46e3 122static int s3c2410wdt_start(struct watchdog_device *wdd)
1da177e4
LT
123{
124 unsigned long wtcon;
125
41dc8b72
AC
126 spin_lock(&wdt_lock);
127
128 __s3c2410wdt_stop();
1da177e4
LT
129
130 wtcon = readl(wdt_base + S3C2410_WTCON);
131 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
132
133 if (soft_noboot) {
134 wtcon |= S3C2410_WTCON_INTEN;
135 wtcon &= ~S3C2410_WTCON_RSTEN;
136 } else {
137 wtcon &= ~S3C2410_WTCON_INTEN;
138 wtcon |= S3C2410_WTCON_RSTEN;
139 }
140
141 DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
fa9363c5 142 __func__, wdt_count, wtcon);
1da177e4
LT
143
144 writel(wdt_count, wdt_base + S3C2410_WTDAT);
145 writel(wdt_count, wdt_base + S3C2410_WTCNT);
146 writel(wtcon, wdt_base + S3C2410_WTCON);
41dc8b72 147 spin_unlock(&wdt_lock);
25dc46e3
WS
148
149 return 0;
1da177e4
LT
150}
151
e02f838e
BD
152static inline int s3c2410wdt_is_running(void)
153{
154 return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
155}
156
25dc46e3 157static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
1da177e4 158{
e02f838e 159 unsigned long freq = clk_get_rate(wdt_clock);
1da177e4
LT
160 unsigned int count;
161 unsigned int divisor = 1;
162 unsigned long wtcon;
163
164 if (timeout < 1)
165 return -EINVAL;
166
167 freq /= 128;
168 count = timeout * freq;
169
e02f838e 170 DBG("%s: count=%d, timeout=%d, freq=%lu\n",
fa9363c5 171 __func__, count, timeout, freq);
1da177e4
LT
172
173 /* if the count is bigger than the watchdog register,
174 then work out what we need to do (and if) we can
175 actually make this value
176 */
177
178 if (count >= 0x10000) {
179 for (divisor = 1; divisor <= 0x100; divisor++) {
180 if ((count / divisor) < 0x10000)
181 break;
182 }
183
184 if ((count / divisor) >= 0x10000) {
e8ef92b8 185 dev_err(wdt_dev, "timeout %d too big\n", timeout);
1da177e4
LT
186 return -EINVAL;
187 }
188 }
189
1da177e4 190 DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
fa9363c5 191 __func__, timeout, divisor, count, count/divisor);
1da177e4
LT
192
193 count /= divisor;
194 wdt_count = count;
195
196 /* update the pre-scaler */
197 wtcon = readl(wdt_base + S3C2410_WTCON);
198 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
199 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
200
201 writel(count, wdt_base + S3C2410_WTDAT);
202 writel(wtcon, wdt_base + S3C2410_WTCON);
203
204 return 0;
205}
206
a77dba7e 207#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
1da177e4 208
41dc8b72 209static const struct watchdog_info s3c2410_wdt_ident = {
1da177e4
LT
210 .options = OPTIONS,
211 .firmware_version = 0,
212 .identity = "S3C2410 Watchdog",
213};
214
25dc46e3
WS
215static struct watchdog_ops s3c2410wdt_ops = {
216 .owner = THIS_MODULE,
217 .start = s3c2410wdt_start,
218 .stop = s3c2410wdt_stop,
219 .ping = s3c2410wdt_keepalive,
220 .set_timeout = s3c2410wdt_set_heartbeat,
1da177e4
LT
221};
222
25dc46e3
WS
223static struct watchdog_device s3c2410_wdd = {
224 .info = &s3c2410_wdt_ident,
225 .ops = &s3c2410wdt_ops,
1da177e4
LT
226};
227
1da177e4
LT
228/* interrupt handler code */
229
7d12e780 230static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
1da177e4 231{
e8ef92b8 232 dev_info(wdt_dev, "watchdog timer expired (irq)\n");
1da177e4 233
25dc46e3 234 s3c2410wdt_keepalive(&s3c2410_wdd);
1da177e4
LT
235 return IRQ_HANDLED;
236}
e02f838e
BD
237
238
239#ifdef CONFIG_CPU_FREQ
240
241static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
242 unsigned long val, void *data)
243{
244 int ret;
245
246 if (!s3c2410wdt_is_running())
247 goto done;
248
249 if (val == CPUFREQ_PRECHANGE) {
250 /* To ensure that over the change we don't cause the
251 * watchdog to trigger, we perform an keep-alive if
252 * the watchdog is running.
253 */
254
25dc46e3 255 s3c2410wdt_keepalive(&s3c2410_wdd);
e02f838e 256 } else if (val == CPUFREQ_POSTCHANGE) {
25dc46e3 257 s3c2410wdt_stop(&s3c2410_wdd);
e02f838e 258
25dc46e3 259 ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout);
e02f838e
BD
260
261 if (ret >= 0)
25dc46e3 262 s3c2410wdt_start(&s3c2410_wdd);
e02f838e
BD
263 else
264 goto err;
265 }
266
267done:
268 return 0;
269
270 err:
25dc46e3
WS
271 dev_err(wdt_dev, "cannot set new value for timeout %d\n",
272 s3c2410_wdd.timeout);
e02f838e
BD
273 return ret;
274}
275
276static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
277 .notifier_call = s3c2410wdt_cpufreq_transition,
278};
279
280static inline int s3c2410wdt_cpufreq_register(void)
281{
282 return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
283 CPUFREQ_TRANSITION_NOTIFIER);
284}
285
286static inline void s3c2410wdt_cpufreq_deregister(void)
287{
288 cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
289 CPUFREQ_TRANSITION_NOTIFIER);
290}
291
292#else
293static inline int s3c2410wdt_cpufreq_register(void)
294{
295 return 0;
296}
297
298static inline void s3c2410wdt_cpufreq_deregister(void)
299{
300}
301#endif
302
a77dba7e 303static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
1da177e4 304{
e8ef92b8 305 struct device *dev;
46b814d6 306 unsigned int wtcon;
1da177e4
LT
307 int started = 0;
308 int ret;
309 int size;
310
fa9363c5 311 DBG("%s: probe=%p\n", __func__, pdev);
1da177e4 312
e8ef92b8
BD
313 dev = &pdev->dev;
314 wdt_dev = &pdev->dev;
315
f72401e9
JL
316 wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
317 if (wdt_mem == NULL) {
e8ef92b8 318 dev_err(dev, "no memory resource specified\n");
1da177e4
LT
319 return -ENOENT;
320 }
321
78d3e00b
MH
322 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
323 if (wdt_irq == NULL) {
324 dev_err(dev, "no irq resource specified\n");
325 ret = -ENOENT;
326 goto err;
327 }
328
329 /* get the memory region for the watchdog timer */
330
f72401e9
JL
331 size = resource_size(wdt_mem);
332 if (!request_mem_region(wdt_mem->start, size, pdev->name)) {
e8ef92b8 333 dev_err(dev, "failed to get memory region\n");
78d3e00b
MH
334 ret = -EBUSY;
335 goto err;
1da177e4
LT
336 }
337
f72401e9 338 wdt_base = ioremap(wdt_mem->start, size);
b4253f8f 339 if (wdt_base == NULL) {
e8ef92b8 340 dev_err(dev, "failed to ioremap() region\n");
0b6dd8a6
BD
341 ret = -EINVAL;
342 goto err_req;
1da177e4
LT
343 }
344
345 DBG("probe: mapped wdt_base=%p\n", wdt_base);
346
3ae5eaec 347 wdt_clock = clk_get(&pdev->dev, "watchdog");
9cd44619 348 if (IS_ERR(wdt_clock)) {
e8ef92b8 349 dev_err(dev, "failed to find watchdog clock source\n");
9cd44619 350 ret = PTR_ERR(wdt_clock);
78d3e00b 351 goto err_map;
1da177e4
LT
352 }
353
1da177e4
LT
354 clk_enable(wdt_clock);
355
78d3e00b
MH
356 ret = s3c2410wdt_cpufreq_register();
357 if (ret < 0) {
27c766aa 358 pr_err("failed to register cpufreq\n");
e02f838e
BD
359 goto err_clk;
360 }
361
1da177e4
LT
362 /* see if we can actually set the requested timer margin, and if
363 * not, try the default value */
364
25dc46e3
WS
365 if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, tmr_margin)) {
366 started = s3c2410wdt_set_heartbeat(&s3c2410_wdd,
41dc8b72 367 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
1da177e4 368
41dc8b72
AC
369 if (started == 0)
370 dev_info(dev,
371 "tmr_margin value out of range, default %d used\n",
1da177e4 372 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
41dc8b72 373 else
a77dba7e
WVS
374 dev_info(dev, "default timer value is out of range, "
375 "cannot start\n");
1da177e4
LT
376 }
377
78d3e00b
MH
378 ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
379 if (ret != 0) {
380 dev_err(dev, "failed to install irq (%d)\n", ret);
381 goto err_cpufreq;
382 }
383
ff0b3cd4
WVS
384 watchdog_set_nowayout(&s3c2410_wdd, nowayout);
385
25dc46e3 386 ret = watchdog_register_device(&s3c2410_wdd);
1da177e4 387 if (ret) {
25dc46e3 388 dev_err(dev, "cannot register watchdog (%d)\n", ret);
78d3e00b 389 goto err_irq;
1da177e4
LT
390 }
391
392 if (tmr_atboot && started == 0) {
e8ef92b8 393 dev_info(dev, "starting watchdog timer\n");
25dc46e3 394 s3c2410wdt_start(&s3c2410_wdd);
655516c8
BD
395 } else if (!tmr_atboot) {
396 /* if we're not enabling the watchdog, then ensure it is
397 * disabled if it has been left running from the bootloader
398 * or other source */
399
25dc46e3 400 s3c2410wdt_stop(&s3c2410_wdd);
1da177e4
LT
401 }
402
46b814d6
BD
403 /* print out a statement of readiness */
404
405 wtcon = readl(wdt_base + S3C2410_WTCON);
406
e8ef92b8 407 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
46b814d6 408 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
20403e84
DA
409 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
410 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
41dc8b72 411
1da177e4 412 return 0;
0b6dd8a6 413
78d3e00b
MH
414 err_irq:
415 free_irq(wdt_irq->start, pdev);
416
e02f838e
BD
417 err_cpufreq:
418 s3c2410wdt_cpufreq_deregister();
419
0b6dd8a6
BD
420 err_clk:
421 clk_disable(wdt_clock);
422 clk_put(wdt_clock);
78d3e00b 423 wdt_clock = NULL;
0b6dd8a6
BD
424
425 err_map:
426 iounmap(wdt_base);
427
428 err_req:
f72401e9 429 release_mem_region(wdt_mem->start, size);
0b6dd8a6 430
78d3e00b
MH
431 err:
432 wdt_irq = NULL;
433 wdt_mem = NULL;
0b6dd8a6 434 return ret;
1da177e4
LT
435}
436
a77dba7e 437static int __devexit s3c2410wdt_remove(struct platform_device *dev)
1da177e4 438{
25dc46e3 439 watchdog_unregister_device(&s3c2410_wdd);
1da177e4 440
78d3e00b
MH
441 free_irq(wdt_irq->start, dev);
442
9a372563 443 s3c2410wdt_cpufreq_deregister();
1da177e4 444
0b6dd8a6
BD
445 clk_disable(wdt_clock);
446 clk_put(wdt_clock);
447 wdt_clock = NULL;
1da177e4 448
e34477e9 449 iounmap(wdt_base);
9a372563 450
f72401e9 451 release_mem_region(wdt_mem->start, resource_size(wdt_mem));
78d3e00b 452 wdt_irq = NULL;
9a372563 453 wdt_mem = NULL;
1da177e4
LT
454 return 0;
455}
456
3ae5eaec 457static void s3c2410wdt_shutdown(struct platform_device *dev)
94f1e9f3 458{
25dc46e3 459 s3c2410wdt_stop(&s3c2410_wdd);
94f1e9f3
BD
460}
461
af4bb822
BD
462#ifdef CONFIG_PM
463
464static unsigned long wtcon_save;
465static unsigned long wtdat_save;
466
3ae5eaec 467static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
af4bb822 468{
9480e307
RK
469 /* Save watchdog state, and turn it off. */
470 wtcon_save = readl(wdt_base + S3C2410_WTCON);
471 wtdat_save = readl(wdt_base + S3C2410_WTDAT);
af4bb822 472
9480e307 473 /* Note that WTCNT doesn't need to be saved. */
25dc46e3 474 s3c2410wdt_stop(&s3c2410_wdd);
af4bb822
BD
475
476 return 0;
477}
478
3ae5eaec 479static int s3c2410wdt_resume(struct platform_device *dev)
af4bb822 480{
9480e307 481 /* Restore watchdog state. */
af4bb822 482
9480e307
RK
483 writel(wtdat_save, wdt_base + S3C2410_WTDAT);
484 writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
485 writel(wtcon_save, wdt_base + S3C2410_WTCON);
af4bb822 486
27c766aa
JP
487 pr_info("watchdog %sabled\n",
488 (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
af4bb822
BD
489
490 return 0;
491}
492
493#else
494#define s3c2410wdt_suspend NULL
495#define s3c2410wdt_resume NULL
496#endif /* CONFIG_PM */
497
9487a9cc
TA
498#ifdef CONFIG_OF
499static const struct of_device_id s3c2410_wdt_match[] = {
500 { .compatible = "samsung,s3c2410-wdt" },
501 {},
502};
503MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
504#else
505#define s3c2410_wdt_match NULL
506#endif
af4bb822 507
3ae5eaec 508static struct platform_driver s3c2410wdt_driver = {
1da177e4 509 .probe = s3c2410wdt_probe,
a77dba7e 510 .remove = __devexit_p(s3c2410wdt_remove),
94f1e9f3 511 .shutdown = s3c2410wdt_shutdown,
af4bb822
BD
512 .suspend = s3c2410wdt_suspend,
513 .resume = s3c2410wdt_resume,
3ae5eaec
RK
514 .driver = {
515 .owner = THIS_MODULE,
516 .name = "s3c2410-wdt",
9487a9cc 517 .of_match_table = s3c2410_wdt_match,
3ae5eaec 518 },
1da177e4
LT
519};
520
521
1da177e4
LT
522static int __init watchdog_init(void)
523{
27c766aa
JP
524 pr_info("S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
525
3ae5eaec 526 return platform_driver_register(&s3c2410wdt_driver);
1da177e4
LT
527}
528
529static void __exit watchdog_exit(void)
530{
3ae5eaec 531 platform_driver_unregister(&s3c2410wdt_driver);
1da177e4
LT
532}
533
534module_init(watchdog_init);
535module_exit(watchdog_exit);
536
af4bb822
BD
537MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
538 "Dimitry Andric <dimitry.andric@tomtom.com>");
1da177e4
LT
539MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
540MODULE_LICENSE("GPL");
541MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c 542MODULE_ALIAS("platform:s3c2410-wdt");