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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/timer.h> | |
1da177e4 | 32 | #include <linux/watchdog.h> |
d052d1be | 33 | #include <linux/platform_device.h> |
1da177e4 | 34 | #include <linux/interrupt.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
41dc8b72 AC |
36 | #include <linux/uaccess.h> |
37 | #include <linux/io.h> | |
e02f838e | 38 | #include <linux/cpufreq.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
25dc46e3 | 40 | #include <linux/err.h> |
3016a552 | 41 | #include <linux/of.h> |
4f1f653a LKA |
42 | #include <linux/mfd/syscon.h> |
43 | #include <linux/regmap.h> | |
1da177e4 | 44 | |
a8f5401a TF |
45 | #define S3C2410_WTCON 0x00 |
46 | #define S3C2410_WTDAT 0x04 | |
47 | #define S3C2410_WTCNT 0x08 | |
1da177e4 | 48 | |
a8f5401a TF |
49 | #define S3C2410_WTCON_RSTEN (1 << 0) |
50 | #define S3C2410_WTCON_INTEN (1 << 2) | |
51 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 52 | |
a8f5401a TF |
53 | #define S3C2410_WTCON_DIV16 (0 << 3) |
54 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
55 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
56 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
57 | ||
58 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) | |
59 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
1da177e4 | 60 | |
1da177e4 LT |
61 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) |
62 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
63 | ||
cffc9a60 | 64 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
65 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
66 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
67 | #define QUIRK_HAS_PMU_CONFIG (1 << 0) | |
cffc9a60 DA |
68 | #define QUIRK_HAS_RST_STAT (1 << 1) |
69 | ||
70 | /* These quirks require that we have a PMU register map */ | |
71 | #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ | |
72 | QUIRK_HAS_RST_STAT) | |
4f1f653a | 73 | |
86a1e189 | 74 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 75 | static int tmr_margin; |
1da177e4 | 76 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 AC |
77 | static int soft_noboot; |
78 | static int debug; | |
1da177e4 LT |
79 | |
80 | module_param(tmr_margin, int, 0); | |
81 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 82 | module_param(nowayout, bool, 0); |
1da177e4 LT |
83 | module_param(soft_noboot, int, 0); |
84 | module_param(debug, int, 0); | |
85 | ||
76550d32 | 86 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
41dc8b72 AC |
87 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
88 | MODULE_PARM_DESC(tmr_atboot, | |
89 | "Watchdog is started at boot time if set to 1, default=" | |
90 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
91 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
92 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 93 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 RD |
94 | "0 to reboot (default 0)"); |
95 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); | |
1da177e4 | 96 | |
4f1f653a LKA |
97 | /** |
98 | * struct s3c2410_wdt_variant - Per-variant config data | |
99 | * | |
100 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
101 | * timer reset functionality. | |
102 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
103 | * timer reset functionality. | |
104 | * @mask_bit: Bit number for the watchdog timer in the disable register and the | |
105 | * mask reset register. | |
cffc9a60 DA |
106 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
107 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
108 | * reset. | |
4f1f653a LKA |
109 | * @quirks: A bitfield of quirks. |
110 | */ | |
111 | ||
112 | struct s3c2410_wdt_variant { | |
113 | int disable_reg; | |
114 | int mask_reset_reg; | |
115 | int mask_bit; | |
cffc9a60 DA |
116 | int rst_stat_reg; |
117 | int rst_stat_bit; | |
4f1f653a LKA |
118 | u32 quirks; |
119 | }; | |
120 | ||
af4ea631 LKA |
121 | struct s3c2410_wdt { |
122 | struct device *dev; | |
123 | struct clk *clock; | |
124 | void __iomem *reg_base; | |
125 | unsigned int count; | |
126 | spinlock_t lock; | |
127 | unsigned long wtcon_save; | |
128 | unsigned long wtdat_save; | |
129 | struct watchdog_device wdt_device; | |
130 | struct notifier_block freq_transition; | |
4f1f653a LKA |
131 | struct s3c2410_wdt_variant *drv_data; |
132 | struct regmap *pmureg; | |
133 | }; | |
134 | ||
135 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
136 | .quirks = 0 | |
137 | }; | |
138 | ||
139 | #ifdef CONFIG_OF | |
140 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { | |
141 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
142 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
143 | .mask_bit = 20, | |
cffc9a60 DA |
144 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
145 | .rst_stat_bit = 20, | |
146 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
147 | }; |
148 | ||
149 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
150 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
151 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
152 | .mask_bit = 0, | |
cffc9a60 DA |
153 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
154 | .rst_stat_bit = 9, | |
155 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
156 | }; |
157 | ||
2b9366b6 NKC |
158 | static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
159 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
160 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
161 | .mask_bit = 0, | |
162 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, | |
163 | .rst_stat_bit = 23, /* A57 WDTRESET */ | |
164 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
165 | }; | |
166 | ||
4f1f653a LKA |
167 | static const struct of_device_id s3c2410_wdt_match[] = { |
168 | { .compatible = "samsung,s3c2410-wdt", | |
169 | .data = &drv_data_s3c2410 }, | |
170 | { .compatible = "samsung,exynos5250-wdt", | |
171 | .data = &drv_data_exynos5250 }, | |
172 | { .compatible = "samsung,exynos5420-wdt", | |
173 | .data = &drv_data_exynos5420 }, | |
2b9366b6 NKC |
174 | { .compatible = "samsung,exynos7-wdt", |
175 | .data = &drv_data_exynos7 }, | |
4f1f653a | 176 | {}, |
af4ea631 | 177 | }; |
4f1f653a LKA |
178 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
179 | #endif | |
180 | ||
181 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
182 | { | |
183 | .name = "s3c2410-wdt", | |
184 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
185 | }, | |
186 | {} | |
187 | }; | |
188 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 LT |
189 | |
190 | /* watchdog control routines */ | |
191 | ||
27c766aa JP |
192 | #define DBG(fmt, ...) \ |
193 | do { \ | |
194 | if (debug) \ | |
195 | pr_info(fmt, ##__VA_ARGS__); \ | |
196 | } while (0) | |
1da177e4 LT |
197 | |
198 | /* functions */ | |
199 | ||
af4ea631 LKA |
200 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
201 | { | |
202 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
203 | } | |
204 | ||
4f1f653a LKA |
205 | static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
206 | { | |
207 | int ret; | |
208 | u32 mask_val = 1 << wdt->drv_data->mask_bit; | |
209 | u32 val = 0; | |
210 | ||
211 | /* No need to do anything if no PMU CONFIG needed */ | |
212 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) | |
213 | return 0; | |
214 | ||
215 | if (mask) | |
216 | val = mask_val; | |
217 | ||
218 | ret = regmap_update_bits(wdt->pmureg, | |
219 | wdt->drv_data->disable_reg, | |
220 | mask_val, val); | |
221 | if (ret < 0) | |
222 | goto error; | |
223 | ||
224 | ret = regmap_update_bits(wdt->pmureg, | |
225 | wdt->drv_data->mask_reset_reg, | |
226 | mask_val, val); | |
227 | error: | |
228 | if (ret < 0) | |
229 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
25dc46e3 | 234 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 235 | { |
af4ea631 LKA |
236 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
237 | ||
238 | spin_lock(&wdt->lock); | |
239 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
240 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
241 | |
242 | return 0; | |
1da177e4 LT |
243 | } |
244 | ||
af4ea631 | 245 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
246 | { |
247 | unsigned long wtcon; | |
248 | ||
af4ea631 | 249 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 250 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 251 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
252 | } |
253 | ||
25dc46e3 | 254 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 255 | { |
af4ea631 LKA |
256 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
257 | ||
258 | spin_lock(&wdt->lock); | |
259 | __s3c2410wdt_stop(wdt); | |
260 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
261 | |
262 | return 0; | |
1da177e4 LT |
263 | } |
264 | ||
25dc46e3 | 265 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
266 | { |
267 | unsigned long wtcon; | |
af4ea631 | 268 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 269 | |
af4ea631 | 270 | spin_lock(&wdt->lock); |
41dc8b72 | 271 | |
af4ea631 | 272 | __s3c2410wdt_stop(wdt); |
1da177e4 | 273 | |
af4ea631 | 274 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
275 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
276 | ||
277 | if (soft_noboot) { | |
278 | wtcon |= S3C2410_WTCON_INTEN; | |
279 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
280 | } else { | |
281 | wtcon &= ~S3C2410_WTCON_INTEN; | |
282 | wtcon |= S3C2410_WTCON_RSTEN; | |
283 | } | |
284 | ||
af4ea631 LKA |
285 | DBG("%s: count=0x%08x, wtcon=%08lx\n", |
286 | __func__, wdt->count, wtcon); | |
1da177e4 | 287 | |
af4ea631 LKA |
288 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
289 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
290 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
291 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
292 | |
293 | return 0; | |
1da177e4 LT |
294 | } |
295 | ||
af4ea631 | 296 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 297 | { |
af4ea631 | 298 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
299 | } |
300 | ||
25dc46e3 | 301 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 302 | { |
af4ea631 LKA |
303 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
304 | unsigned long freq = clk_get_rate(wdt->clock); | |
1da177e4 LT |
305 | unsigned int count; |
306 | unsigned int divisor = 1; | |
307 | unsigned long wtcon; | |
308 | ||
309 | if (timeout < 1) | |
310 | return -EINVAL; | |
311 | ||
17862440 | 312 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
313 | count = timeout * freq; |
314 | ||
e02f838e | 315 | DBG("%s: count=%d, timeout=%d, freq=%lu\n", |
fa9363c5 | 316 | __func__, count, timeout, freq); |
1da177e4 LT |
317 | |
318 | /* if the count is bigger than the watchdog register, | |
319 | then work out what we need to do (and if) we can | |
320 | actually make this value | |
321 | */ | |
322 | ||
323 | if (count >= 0x10000) { | |
17862440 | 324 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 325 | |
17862440 | 326 | if (divisor > 0x100) { |
af4ea631 | 327 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
328 | return -EINVAL; |
329 | } | |
330 | } | |
331 | ||
1da177e4 | 332 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", |
17862440 | 333 | __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor)); |
1da177e4 | 334 | |
17862440 | 335 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 336 | wdt->count = count; |
1da177e4 LT |
337 | |
338 | /* update the pre-scaler */ | |
af4ea631 | 339 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
340 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
341 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
342 | ||
af4ea631 LKA |
343 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
344 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 345 | |
5f2430f5 | 346 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 347 | |
1da177e4 LT |
348 | return 0; |
349 | } | |
350 | ||
a77dba7e | 351 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 352 | |
41dc8b72 | 353 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
354 | .options = OPTIONS, |
355 | .firmware_version = 0, | |
356 | .identity = "S3C2410 Watchdog", | |
357 | }; | |
358 | ||
25dc46e3 WS |
359 | static struct watchdog_ops s3c2410wdt_ops = { |
360 | .owner = THIS_MODULE, | |
361 | .start = s3c2410wdt_start, | |
362 | .stop = s3c2410wdt_stop, | |
363 | .ping = s3c2410wdt_keepalive, | |
364 | .set_timeout = s3c2410wdt_set_heartbeat, | |
1da177e4 LT |
365 | }; |
366 | ||
25dc46e3 WS |
367 | static struct watchdog_device s3c2410_wdd = { |
368 | .info = &s3c2410_wdt_ident, | |
369 | .ops = &s3c2410wdt_ops, | |
c1fd5f64 | 370 | .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
371 | }; |
372 | ||
1da177e4 LT |
373 | /* interrupt handler code */ |
374 | ||
7d12e780 | 375 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 376 | { |
af4ea631 | 377 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 378 | |
af4ea631 LKA |
379 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
380 | ||
381 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
1da177e4 LT |
382 | return IRQ_HANDLED; |
383 | } | |
e02f838e | 384 | |
0f1dd98d | 385 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
386 | |
387 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
388 | unsigned long val, void *data) | |
389 | { | |
390 | int ret; | |
af4ea631 | 391 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 392 | |
af4ea631 | 393 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
394 | goto done; |
395 | ||
396 | if (val == CPUFREQ_PRECHANGE) { | |
397 | /* To ensure that over the change we don't cause the | |
398 | * watchdog to trigger, we perform an keep-alive if | |
399 | * the watchdog is running. | |
400 | */ | |
401 | ||
af4ea631 | 402 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 403 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 404 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 405 | |
af4ea631 LKA |
406 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
407 | wdt->wdt_device.timeout); | |
e02f838e BD |
408 | |
409 | if (ret >= 0) | |
af4ea631 | 410 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
411 | else |
412 | goto err; | |
413 | } | |
414 | ||
415 | done: | |
416 | return 0; | |
417 | ||
418 | err: | |
af4ea631 LKA |
419 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
420 | wdt->wdt_device.timeout); | |
e02f838e BD |
421 | return ret; |
422 | } | |
423 | ||
af4ea631 | 424 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 425 | { |
af4ea631 LKA |
426 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
427 | ||
428 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
429 | CPUFREQ_TRANSITION_NOTIFIER); |
430 | } | |
431 | ||
af4ea631 | 432 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 433 | { |
af4ea631 LKA |
434 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
435 | ||
436 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
437 | CPUFREQ_TRANSITION_NOTIFIER); |
438 | } | |
439 | ||
440 | #else | |
af4ea631 LKA |
441 | |
442 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
443 | { |
444 | return 0; | |
445 | } | |
446 | ||
af4ea631 | 447 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
448 | { |
449 | } | |
450 | #endif | |
451 | ||
cffc9a60 DA |
452 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
453 | { | |
454 | unsigned int rst_stat; | |
455 | int ret; | |
456 | ||
457 | if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) | |
458 | return 0; | |
459 | ||
460 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
461 | if (ret) | |
462 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
463 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
464 | return WDIOF_CARDRESET; | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
4f1f653a LKA |
469 | /* s3c2410_get_wdt_driver_data */ |
470 | static inline struct s3c2410_wdt_variant * | |
471 | get_wdt_drv_data(struct platform_device *pdev) | |
472 | { | |
473 | if (pdev->dev.of_node) { | |
474 | const struct of_device_id *match; | |
475 | match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node); | |
476 | return (struct s3c2410_wdt_variant *)match->data; | |
477 | } else { | |
478 | return (struct s3c2410_wdt_variant *) | |
479 | platform_get_device_id(pdev)->driver_data; | |
480 | } | |
481 | } | |
482 | ||
2d991a16 | 483 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 484 | { |
e8ef92b8 | 485 | struct device *dev; |
af4ea631 LKA |
486 | struct s3c2410_wdt *wdt; |
487 | struct resource *wdt_mem; | |
488 | struct resource *wdt_irq; | |
46b814d6 | 489 | unsigned int wtcon; |
1da177e4 LT |
490 | int started = 0; |
491 | int ret; | |
1da177e4 | 492 | |
fa9363c5 | 493 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 494 | |
e8ef92b8 | 495 | dev = &pdev->dev; |
e8ef92b8 | 496 | |
af4ea631 LKA |
497 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
498 | if (!wdt) | |
499 | return -ENOMEM; | |
500 | ||
501 | wdt->dev = &pdev->dev; | |
502 | spin_lock_init(&wdt->lock); | |
503 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 504 | |
4f1f653a | 505 | wdt->drv_data = get_wdt_drv_data(pdev); |
cffc9a60 | 506 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
507 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
508 | "samsung,syscon-phandle"); | |
509 | if (IS_ERR(wdt->pmureg)) { | |
510 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
511 | return PTR_ERR(wdt->pmureg); | |
512 | } | |
513 | } | |
514 | ||
78d3e00b MH |
515 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
516 | if (wdt_irq == NULL) { | |
517 | dev_err(dev, "no irq resource specified\n"); | |
518 | ret = -ENOENT; | |
519 | goto err; | |
520 | } | |
521 | ||
522 | /* get the memory region for the watchdog timer */ | |
bd5cc119 | 523 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
af4ea631 LKA |
524 | wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); |
525 | if (IS_ERR(wdt->reg_base)) { | |
526 | ret = PTR_ERR(wdt->reg_base); | |
04ecc7dc | 527 | goto err; |
1da177e4 LT |
528 | } |
529 | ||
af4ea631 | 530 | DBG("probe: mapped reg_base=%p\n", wdt->reg_base); |
1da177e4 | 531 | |
af4ea631 LKA |
532 | wdt->clock = devm_clk_get(dev, "watchdog"); |
533 | if (IS_ERR(wdt->clock)) { | |
e8ef92b8 | 534 | dev_err(dev, "failed to find watchdog clock source\n"); |
af4ea631 | 535 | ret = PTR_ERR(wdt->clock); |
04ecc7dc | 536 | goto err; |
1da177e4 LT |
537 | } |
538 | ||
01b6af91 SK |
539 | ret = clk_prepare_enable(wdt->clock); |
540 | if (ret < 0) { | |
541 | dev_err(dev, "failed to enable clock\n"); | |
542 | return ret; | |
543 | } | |
1da177e4 | 544 | |
af4ea631 | 545 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 546 | if (ret < 0) { |
3828924a | 547 | dev_err(dev, "failed to register cpufreq\n"); |
e02f838e BD |
548 | goto err_clk; |
549 | } | |
550 | ||
af4ea631 LKA |
551 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
552 | ||
1da177e4 LT |
553 | /* see if we can actually set the requested timer margin, and if |
554 | * not, try the default value */ | |
555 | ||
af4ea631 LKA |
556 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); |
557 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
558 | wdt->wdt_device.timeout); | |
559 | if (ret) { | |
560 | started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
41dc8b72 | 561 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 562 | |
41dc8b72 AC |
563 | if (started == 0) |
564 | dev_info(dev, | |
565 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 566 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 567 | else |
a77dba7e WVS |
568 | dev_info(dev, "default timer value is out of range, " |
569 | "cannot start\n"); | |
1da177e4 LT |
570 | } |
571 | ||
04ecc7dc JH |
572 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
573 | pdev->name, pdev); | |
78d3e00b MH |
574 | if (ret != 0) { |
575 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
576 | goto err_cpufreq; | |
577 | } | |
578 | ||
af4ea631 | 579 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
ff0b3cd4 | 580 | |
cffc9a60 DA |
581 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
582 | ||
af4ea631 | 583 | ret = watchdog_register_device(&wdt->wdt_device); |
1da177e4 | 584 | if (ret) { |
25dc46e3 | 585 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 586 | goto err_cpufreq; |
1da177e4 LT |
587 | } |
588 | ||
4f1f653a LKA |
589 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
590 | if (ret < 0) | |
591 | goto err_unregister; | |
592 | ||
1da177e4 | 593 | if (tmr_atboot && started == 0) { |
e8ef92b8 | 594 | dev_info(dev, "starting watchdog timer\n"); |
af4ea631 | 595 | s3c2410wdt_start(&wdt->wdt_device); |
655516c8 BD |
596 | } else if (!tmr_atboot) { |
597 | /* if we're not enabling the watchdog, then ensure it is | |
598 | * disabled if it has been left running from the bootloader | |
599 | * or other source */ | |
600 | ||
af4ea631 | 601 | s3c2410wdt_stop(&wdt->wdt_device); |
1da177e4 LT |
602 | } |
603 | ||
af4ea631 LKA |
604 | platform_set_drvdata(pdev, wdt); |
605 | ||
46b814d6 BD |
606 | /* print out a statement of readiness */ |
607 | ||
af4ea631 | 608 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 609 | |
e8ef92b8 | 610 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 611 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
612 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
613 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 614 | |
1da177e4 | 615 | return 0; |
0b6dd8a6 | 616 | |
4f1f653a LKA |
617 | err_unregister: |
618 | watchdog_unregister_device(&wdt->wdt_device); | |
619 | ||
e02f838e | 620 | err_cpufreq: |
af4ea631 | 621 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 622 | |
0b6dd8a6 | 623 | err_clk: |
af4ea631 | 624 | clk_disable_unprepare(wdt->clock); |
0b6dd8a6 | 625 | |
78d3e00b | 626 | err: |
0b6dd8a6 | 627 | return ret; |
1da177e4 LT |
628 | } |
629 | ||
4b12b896 | 630 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 631 | { |
4f1f653a | 632 | int ret; |
af4ea631 LKA |
633 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
634 | ||
4f1f653a LKA |
635 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
636 | if (ret < 0) | |
637 | return ret; | |
638 | ||
af4ea631 | 639 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 640 | |
af4ea631 | 641 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 642 | |
af4ea631 | 643 | clk_disable_unprepare(wdt->clock); |
1da177e4 | 644 | |
1da177e4 LT |
645 | return 0; |
646 | } | |
647 | ||
3ae5eaec | 648 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 649 | { |
af4ea631 LKA |
650 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
651 | ||
4f1f653a LKA |
652 | s3c2410wdt_mask_and_disable_reset(wdt, true); |
653 | ||
af4ea631 | 654 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
655 | } |
656 | ||
0183984c | 657 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 658 | |
0183984c | 659 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 660 | { |
4f1f653a | 661 | int ret; |
af4ea631 LKA |
662 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
663 | ||
9480e307 | 664 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
665 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
666 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 667 | |
4f1f653a LKA |
668 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
669 | if (ret < 0) | |
670 | return ret; | |
671 | ||
9480e307 | 672 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 673 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
674 | |
675 | return 0; | |
676 | } | |
677 | ||
0183984c | 678 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 679 | { |
4f1f653a | 680 | int ret; |
af4ea631 | 681 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 682 | |
af4ea631 LKA |
683 | /* Restore watchdog state. */ |
684 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
685 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
686 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 687 | |
4f1f653a LKA |
688 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
689 | if (ret < 0) | |
690 | return ret; | |
691 | ||
0183984c | 692 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 693 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
694 | |
695 | return 0; | |
696 | } | |
0183984c | 697 | #endif |
af4bb822 | 698 | |
0183984c JH |
699 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
700 | s3c2410wdt_resume); | |
af4bb822 | 701 | |
3ae5eaec | 702 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 703 | .probe = s3c2410wdt_probe, |
82268714 | 704 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 705 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 706 | .id_table = s3c2410_wdt_ids, |
3ae5eaec RK |
707 | .driver = { |
708 | .owner = THIS_MODULE, | |
709 | .name = "s3c2410-wdt", | |
0183984c | 710 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 711 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 712 | }, |
1da177e4 LT |
713 | }; |
714 | ||
6b761b29 | 715 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 716 | |
af4bb822 BD |
717 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
718 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
719 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
720 | MODULE_LICENSE("GPL"); |