]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/timer.h> | |
25dc46e3 | 32 | #include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */ |
1da177e4 | 33 | #include <linux/watchdog.h> |
1da177e4 | 34 | #include <linux/init.h> |
d052d1be | 35 | #include <linux/platform_device.h> |
1da177e4 | 36 | #include <linux/interrupt.h> |
f8ce2547 | 37 | #include <linux/clk.h> |
41dc8b72 AC |
38 | #include <linux/uaccess.h> |
39 | #include <linux/io.h> | |
e02f838e | 40 | #include <linux/cpufreq.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
25dc46e3 | 42 | #include <linux/err.h> |
3016a552 | 43 | #include <linux/of.h> |
1da177e4 | 44 | |
a09e64fb | 45 | #include <mach/map.h> |
1da177e4 | 46 | |
b430708a BD |
47 | #undef S3C_VA_WATCHDOG |
48 | #define S3C_VA_WATCHDOG (0) | |
1da177e4 | 49 | |
180ee700 | 50 | #include <plat/regs-watchdog.h> |
1da177e4 | 51 | |
1da177e4 LT |
52 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) |
53 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
54 | ||
86a1e189 | 55 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 56 | static int tmr_margin; |
1da177e4 | 57 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 AC |
58 | static int soft_noboot; |
59 | static int debug; | |
1da177e4 LT |
60 | |
61 | module_param(tmr_margin, int, 0); | |
62 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 63 | module_param(nowayout, bool, 0); |
1da177e4 LT |
64 | module_param(soft_noboot, int, 0); |
65 | module_param(debug, int, 0); | |
66 | ||
76550d32 | 67 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
41dc8b72 AC |
68 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
69 | MODULE_PARM_DESC(tmr_atboot, | |
70 | "Watchdog is started at boot time if set to 1, default=" | |
71 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
72 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
73 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 74 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 RD |
75 | "0 to reboot (default 0)"); |
76 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); | |
1da177e4 | 77 | |
e8ef92b8 | 78 | static struct device *wdt_dev; /* platform device attached to */ |
1da177e4 LT |
79 | static struct resource *wdt_mem; |
80 | static struct resource *wdt_irq; | |
81 | static struct clk *wdt_clock; | |
82 | static void __iomem *wdt_base; | |
83 | static unsigned int wdt_count; | |
41dc8b72 | 84 | static DEFINE_SPINLOCK(wdt_lock); |
1da177e4 LT |
85 | |
86 | /* watchdog control routines */ | |
87 | ||
27c766aa JP |
88 | #define DBG(fmt, ...) \ |
89 | do { \ | |
90 | if (debug) \ | |
91 | pr_info(fmt, ##__VA_ARGS__); \ | |
92 | } while (0) | |
1da177e4 LT |
93 | |
94 | /* functions */ | |
95 | ||
25dc46e3 | 96 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 97 | { |
41dc8b72 | 98 | spin_lock(&wdt_lock); |
1da177e4 | 99 | writel(wdt_count, wdt_base + S3C2410_WTCNT); |
41dc8b72 | 100 | spin_unlock(&wdt_lock); |
25dc46e3 WS |
101 | |
102 | return 0; | |
1da177e4 LT |
103 | } |
104 | ||
41dc8b72 AC |
105 | static void __s3c2410wdt_stop(void) |
106 | { | |
107 | unsigned long wtcon; | |
108 | ||
109 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
110 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); | |
111 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
112 | } | |
113 | ||
25dc46e3 | 114 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 AC |
115 | { |
116 | spin_lock(&wdt_lock); | |
117 | __s3c2410wdt_stop(); | |
118 | spin_unlock(&wdt_lock); | |
25dc46e3 WS |
119 | |
120 | return 0; | |
1da177e4 LT |
121 | } |
122 | ||
25dc46e3 | 123 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
124 | { |
125 | unsigned long wtcon; | |
126 | ||
41dc8b72 AC |
127 | spin_lock(&wdt_lock); |
128 | ||
129 | __s3c2410wdt_stop(); | |
1da177e4 LT |
130 | |
131 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
132 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; | |
133 | ||
134 | if (soft_noboot) { | |
135 | wtcon |= S3C2410_WTCON_INTEN; | |
136 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
137 | } else { | |
138 | wtcon &= ~S3C2410_WTCON_INTEN; | |
139 | wtcon |= S3C2410_WTCON_RSTEN; | |
140 | } | |
141 | ||
142 | DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n", | |
fa9363c5 | 143 | __func__, wdt_count, wtcon); |
1da177e4 LT |
144 | |
145 | writel(wdt_count, wdt_base + S3C2410_WTDAT); | |
146 | writel(wdt_count, wdt_base + S3C2410_WTCNT); | |
147 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
41dc8b72 | 148 | spin_unlock(&wdt_lock); |
25dc46e3 WS |
149 | |
150 | return 0; | |
1da177e4 LT |
151 | } |
152 | ||
e02f838e BD |
153 | static inline int s3c2410wdt_is_running(void) |
154 | { | |
155 | return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; | |
156 | } | |
157 | ||
25dc46e3 | 158 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 159 | { |
e02f838e | 160 | unsigned long freq = clk_get_rate(wdt_clock); |
1da177e4 LT |
161 | unsigned int count; |
162 | unsigned int divisor = 1; | |
163 | unsigned long wtcon; | |
164 | ||
165 | if (timeout < 1) | |
166 | return -EINVAL; | |
167 | ||
168 | freq /= 128; | |
169 | count = timeout * freq; | |
170 | ||
e02f838e | 171 | DBG("%s: count=%d, timeout=%d, freq=%lu\n", |
fa9363c5 | 172 | __func__, count, timeout, freq); |
1da177e4 LT |
173 | |
174 | /* if the count is bigger than the watchdog register, | |
175 | then work out what we need to do (and if) we can | |
176 | actually make this value | |
177 | */ | |
178 | ||
179 | if (count >= 0x10000) { | |
180 | for (divisor = 1; divisor <= 0x100; divisor++) { | |
181 | if ((count / divisor) < 0x10000) | |
182 | break; | |
183 | } | |
184 | ||
185 | if ((count / divisor) >= 0x10000) { | |
e8ef92b8 | 186 | dev_err(wdt_dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
187 | return -EINVAL; |
188 | } | |
189 | } | |
190 | ||
1da177e4 | 191 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", |
fa9363c5 | 192 | __func__, timeout, divisor, count, count/divisor); |
1da177e4 LT |
193 | |
194 | count /= divisor; | |
195 | wdt_count = count; | |
196 | ||
197 | /* update the pre-scaler */ | |
198 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
199 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; | |
200 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
201 | ||
202 | writel(count, wdt_base + S3C2410_WTDAT); | |
203 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
204 | ||
5f2430f5 | 205 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 206 | |
1da177e4 LT |
207 | return 0; |
208 | } | |
209 | ||
a77dba7e | 210 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 211 | |
41dc8b72 | 212 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
213 | .options = OPTIONS, |
214 | .firmware_version = 0, | |
215 | .identity = "S3C2410 Watchdog", | |
216 | }; | |
217 | ||
25dc46e3 WS |
218 | static struct watchdog_ops s3c2410wdt_ops = { |
219 | .owner = THIS_MODULE, | |
220 | .start = s3c2410wdt_start, | |
221 | .stop = s3c2410wdt_stop, | |
222 | .ping = s3c2410wdt_keepalive, | |
223 | .set_timeout = s3c2410wdt_set_heartbeat, | |
1da177e4 LT |
224 | }; |
225 | ||
25dc46e3 WS |
226 | static struct watchdog_device s3c2410_wdd = { |
227 | .info = &s3c2410_wdt_ident, | |
228 | .ops = &s3c2410wdt_ops, | |
c1fd5f64 | 229 | .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
230 | }; |
231 | ||
1da177e4 LT |
232 | /* interrupt handler code */ |
233 | ||
7d12e780 | 234 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 235 | { |
e8ef92b8 | 236 | dev_info(wdt_dev, "watchdog timer expired (irq)\n"); |
1da177e4 | 237 | |
25dc46e3 | 238 | s3c2410wdt_keepalive(&s3c2410_wdd); |
1da177e4 LT |
239 | return IRQ_HANDLED; |
240 | } | |
e02f838e BD |
241 | |
242 | ||
243 | #ifdef CONFIG_CPU_FREQ | |
244 | ||
245 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
246 | unsigned long val, void *data) | |
247 | { | |
248 | int ret; | |
249 | ||
250 | if (!s3c2410wdt_is_running()) | |
251 | goto done; | |
252 | ||
253 | if (val == CPUFREQ_PRECHANGE) { | |
254 | /* To ensure that over the change we don't cause the | |
255 | * watchdog to trigger, we perform an keep-alive if | |
256 | * the watchdog is running. | |
257 | */ | |
258 | ||
25dc46e3 | 259 | s3c2410wdt_keepalive(&s3c2410_wdd); |
e02f838e | 260 | } else if (val == CPUFREQ_POSTCHANGE) { |
25dc46e3 | 261 | s3c2410wdt_stop(&s3c2410_wdd); |
e02f838e | 262 | |
25dc46e3 | 263 | ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout); |
e02f838e BD |
264 | |
265 | if (ret >= 0) | |
25dc46e3 | 266 | s3c2410wdt_start(&s3c2410_wdd); |
e02f838e BD |
267 | else |
268 | goto err; | |
269 | } | |
270 | ||
271 | done: | |
272 | return 0; | |
273 | ||
274 | err: | |
25dc46e3 WS |
275 | dev_err(wdt_dev, "cannot set new value for timeout %d\n", |
276 | s3c2410_wdd.timeout); | |
e02f838e BD |
277 | return ret; |
278 | } | |
279 | ||
280 | static struct notifier_block s3c2410wdt_cpufreq_transition_nb = { | |
281 | .notifier_call = s3c2410wdt_cpufreq_transition, | |
282 | }; | |
283 | ||
284 | static inline int s3c2410wdt_cpufreq_register(void) | |
285 | { | |
286 | return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb, | |
287 | CPUFREQ_TRANSITION_NOTIFIER); | |
288 | } | |
289 | ||
290 | static inline void s3c2410wdt_cpufreq_deregister(void) | |
291 | { | |
292 | cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb, | |
293 | CPUFREQ_TRANSITION_NOTIFIER); | |
294 | } | |
295 | ||
296 | #else | |
297 | static inline int s3c2410wdt_cpufreq_register(void) | |
298 | { | |
299 | return 0; | |
300 | } | |
301 | ||
302 | static inline void s3c2410wdt_cpufreq_deregister(void) | |
303 | { | |
304 | } | |
305 | #endif | |
306 | ||
2d991a16 | 307 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 308 | { |
e8ef92b8 | 309 | struct device *dev; |
46b814d6 | 310 | unsigned int wtcon; |
1da177e4 LT |
311 | int started = 0; |
312 | int ret; | |
1da177e4 | 313 | |
fa9363c5 | 314 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 315 | |
e8ef92b8 BD |
316 | dev = &pdev->dev; |
317 | wdt_dev = &pdev->dev; | |
318 | ||
f72401e9 JL |
319 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
320 | if (wdt_mem == NULL) { | |
e8ef92b8 | 321 | dev_err(dev, "no memory resource specified\n"); |
1da177e4 LT |
322 | return -ENOENT; |
323 | } | |
324 | ||
78d3e00b MH |
325 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
326 | if (wdt_irq == NULL) { | |
327 | dev_err(dev, "no irq resource specified\n"); | |
328 | ret = -ENOENT; | |
329 | goto err; | |
330 | } | |
331 | ||
332 | /* get the memory region for the watchdog timer */ | |
6330c707 SK |
333 | wdt_base = devm_ioremap_resource(dev, wdt_mem); |
334 | if (IS_ERR(wdt_base)) { | |
335 | ret = PTR_ERR(wdt_base); | |
04ecc7dc | 336 | goto err; |
1da177e4 LT |
337 | } |
338 | ||
339 | DBG("probe: mapped wdt_base=%p\n", wdt_base); | |
340 | ||
04ecc7dc | 341 | wdt_clock = devm_clk_get(dev, "watchdog"); |
9cd44619 | 342 | if (IS_ERR(wdt_clock)) { |
e8ef92b8 | 343 | dev_err(dev, "failed to find watchdog clock source\n"); |
9cd44619 | 344 | ret = PTR_ERR(wdt_clock); |
04ecc7dc | 345 | goto err; |
1da177e4 LT |
346 | } |
347 | ||
50d854c8 | 348 | clk_prepare_enable(wdt_clock); |
1da177e4 | 349 | |
78d3e00b MH |
350 | ret = s3c2410wdt_cpufreq_register(); |
351 | if (ret < 0) { | |
27c766aa | 352 | pr_err("failed to register cpufreq\n"); |
e02f838e BD |
353 | goto err_clk; |
354 | } | |
355 | ||
1da177e4 LT |
356 | /* see if we can actually set the requested timer margin, and if |
357 | * not, try the default value */ | |
358 | ||
c1fd5f64 FP |
359 | watchdog_init_timeout(&s3c2410_wdd, tmr_margin, &pdev->dev); |
360 | if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout)) { | |
25dc46e3 | 361 | started = s3c2410wdt_set_heartbeat(&s3c2410_wdd, |
41dc8b72 | 362 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 363 | |
41dc8b72 AC |
364 | if (started == 0) |
365 | dev_info(dev, | |
366 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 367 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 368 | else |
a77dba7e WVS |
369 | dev_info(dev, "default timer value is out of range, " |
370 | "cannot start\n"); | |
1da177e4 LT |
371 | } |
372 | ||
04ecc7dc JH |
373 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
374 | pdev->name, pdev); | |
78d3e00b MH |
375 | if (ret != 0) { |
376 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
377 | goto err_cpufreq; | |
378 | } | |
379 | ||
ff0b3cd4 WVS |
380 | watchdog_set_nowayout(&s3c2410_wdd, nowayout); |
381 | ||
25dc46e3 | 382 | ret = watchdog_register_device(&s3c2410_wdd); |
1da177e4 | 383 | if (ret) { |
25dc46e3 | 384 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 385 | goto err_cpufreq; |
1da177e4 LT |
386 | } |
387 | ||
388 | if (tmr_atboot && started == 0) { | |
e8ef92b8 | 389 | dev_info(dev, "starting watchdog timer\n"); |
25dc46e3 | 390 | s3c2410wdt_start(&s3c2410_wdd); |
655516c8 BD |
391 | } else if (!tmr_atboot) { |
392 | /* if we're not enabling the watchdog, then ensure it is | |
393 | * disabled if it has been left running from the bootloader | |
394 | * or other source */ | |
395 | ||
25dc46e3 | 396 | s3c2410wdt_stop(&s3c2410_wdd); |
1da177e4 LT |
397 | } |
398 | ||
46b814d6 BD |
399 | /* print out a statement of readiness */ |
400 | ||
401 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
402 | ||
e8ef92b8 | 403 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 404 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
405 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
406 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 407 | |
1da177e4 | 408 | return 0; |
0b6dd8a6 | 409 | |
e02f838e BD |
410 | err_cpufreq: |
411 | s3c2410wdt_cpufreq_deregister(); | |
412 | ||
0b6dd8a6 | 413 | err_clk: |
50d854c8 | 414 | clk_disable_unprepare(wdt_clock); |
78d3e00b | 415 | wdt_clock = NULL; |
0b6dd8a6 | 416 | |
78d3e00b MH |
417 | err: |
418 | wdt_irq = NULL; | |
419 | wdt_mem = NULL; | |
0b6dd8a6 | 420 | return ret; |
1da177e4 LT |
421 | } |
422 | ||
4b12b896 | 423 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 424 | { |
25dc46e3 | 425 | watchdog_unregister_device(&s3c2410_wdd); |
1da177e4 | 426 | |
9a372563 | 427 | s3c2410wdt_cpufreq_deregister(); |
1da177e4 | 428 | |
50d854c8 | 429 | clk_disable_unprepare(wdt_clock); |
0b6dd8a6 | 430 | wdt_clock = NULL; |
1da177e4 | 431 | |
78d3e00b | 432 | wdt_irq = NULL; |
9a372563 | 433 | wdt_mem = NULL; |
1da177e4 LT |
434 | return 0; |
435 | } | |
436 | ||
3ae5eaec | 437 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 438 | { |
25dc46e3 | 439 | s3c2410wdt_stop(&s3c2410_wdd); |
94f1e9f3 BD |
440 | } |
441 | ||
af4bb822 BD |
442 | #ifdef CONFIG_PM |
443 | ||
444 | static unsigned long wtcon_save; | |
445 | static unsigned long wtdat_save; | |
446 | ||
3ae5eaec | 447 | static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state) |
af4bb822 | 448 | { |
9480e307 RK |
449 | /* Save watchdog state, and turn it off. */ |
450 | wtcon_save = readl(wdt_base + S3C2410_WTCON); | |
451 | wtdat_save = readl(wdt_base + S3C2410_WTDAT); | |
af4bb822 | 452 | |
9480e307 | 453 | /* Note that WTCNT doesn't need to be saved. */ |
25dc46e3 | 454 | s3c2410wdt_stop(&s3c2410_wdd); |
af4bb822 BD |
455 | |
456 | return 0; | |
457 | } | |
458 | ||
3ae5eaec | 459 | static int s3c2410wdt_resume(struct platform_device *dev) |
af4bb822 | 460 | { |
9480e307 | 461 | /* Restore watchdog state. */ |
af4bb822 | 462 | |
9480e307 RK |
463 | writel(wtdat_save, wdt_base + S3C2410_WTDAT); |
464 | writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */ | |
465 | writel(wtcon_save, wdt_base + S3C2410_WTCON); | |
af4bb822 | 466 | |
27c766aa JP |
467 | pr_info("watchdog %sabled\n", |
468 | (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); | |
af4bb822 BD |
469 | |
470 | return 0; | |
471 | } | |
472 | ||
473 | #else | |
474 | #define s3c2410wdt_suspend NULL | |
475 | #define s3c2410wdt_resume NULL | |
476 | #endif /* CONFIG_PM */ | |
477 | ||
9487a9cc TA |
478 | #ifdef CONFIG_OF |
479 | static const struct of_device_id s3c2410_wdt_match[] = { | |
480 | { .compatible = "samsung,s3c2410-wdt" }, | |
481 | {}, | |
482 | }; | |
483 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); | |
9487a9cc | 484 | #endif |
af4bb822 | 485 | |
3ae5eaec | 486 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 487 | .probe = s3c2410wdt_probe, |
82268714 | 488 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 489 | .shutdown = s3c2410wdt_shutdown, |
af4bb822 BD |
490 | .suspend = s3c2410wdt_suspend, |
491 | .resume = s3c2410wdt_resume, | |
3ae5eaec RK |
492 | .driver = { |
493 | .owner = THIS_MODULE, | |
494 | .name = "s3c2410-wdt", | |
3016a552 | 495 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 496 | }, |
1da177e4 LT |
497 | }; |
498 | ||
6b761b29 | 499 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 500 | |
af4bb822 BD |
501 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
502 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
503 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
504 | MODULE_LICENSE("GPL"); | |
505 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
f37d193c | 506 | MODULE_ALIAS("platform:s3c2410-wdt"); |