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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/timer.h> | |
1da177e4 | 32 | #include <linux/watchdog.h> |
d052d1be | 33 | #include <linux/platform_device.h> |
1da177e4 | 34 | #include <linux/interrupt.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
41dc8b72 AC |
36 | #include <linux/uaccess.h> |
37 | #include <linux/io.h> | |
e02f838e | 38 | #include <linux/cpufreq.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
25dc46e3 | 40 | #include <linux/err.h> |
3016a552 | 41 | #include <linux/of.h> |
4f1f653a LKA |
42 | #include <linux/mfd/syscon.h> |
43 | #include <linux/regmap.h> | |
1da177e4 | 44 | |
a8f5401a TF |
45 | #define S3C2410_WTCON 0x00 |
46 | #define S3C2410_WTDAT 0x04 | |
47 | #define S3C2410_WTCNT 0x08 | |
1da177e4 | 48 | |
a8f5401a TF |
49 | #define S3C2410_WTCON_RSTEN (1 << 0) |
50 | #define S3C2410_WTCON_INTEN (1 << 2) | |
51 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 52 | |
a8f5401a TF |
53 | #define S3C2410_WTCON_DIV16 (0 << 3) |
54 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
55 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
56 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
57 | ||
58 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) | |
59 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
1da177e4 | 60 | |
1da177e4 LT |
61 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) |
62 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
63 | ||
cffc9a60 | 64 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
65 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
66 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
67 | #define QUIRK_HAS_PMU_CONFIG (1 << 0) | |
cffc9a60 DA |
68 | #define QUIRK_HAS_RST_STAT (1 << 1) |
69 | ||
70 | /* These quirks require that we have a PMU register map */ | |
71 | #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ | |
72 | QUIRK_HAS_RST_STAT) | |
4f1f653a | 73 | |
86a1e189 | 74 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 75 | static int tmr_margin; |
1da177e4 | 76 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 AC |
77 | static int soft_noboot; |
78 | static int debug; | |
1da177e4 LT |
79 | |
80 | module_param(tmr_margin, int, 0); | |
81 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 82 | module_param(nowayout, bool, 0); |
1da177e4 LT |
83 | module_param(soft_noboot, int, 0); |
84 | module_param(debug, int, 0); | |
85 | ||
76550d32 | 86 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
41dc8b72 AC |
87 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
88 | MODULE_PARM_DESC(tmr_atboot, | |
89 | "Watchdog is started at boot time if set to 1, default=" | |
90 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
91 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
92 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 93 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 RD |
94 | "0 to reboot (default 0)"); |
95 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); | |
1da177e4 | 96 | |
4f1f653a LKA |
97 | /** |
98 | * struct s3c2410_wdt_variant - Per-variant config data | |
99 | * | |
100 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
101 | * timer reset functionality. | |
102 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
103 | * timer reset functionality. | |
104 | * @mask_bit: Bit number for the watchdog timer in the disable register and the | |
105 | * mask reset register. | |
cffc9a60 DA |
106 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
107 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
108 | * reset. | |
4f1f653a LKA |
109 | * @quirks: A bitfield of quirks. |
110 | */ | |
111 | ||
112 | struct s3c2410_wdt_variant { | |
113 | int disable_reg; | |
114 | int mask_reset_reg; | |
115 | int mask_bit; | |
cffc9a60 DA |
116 | int rst_stat_reg; |
117 | int rst_stat_bit; | |
4f1f653a LKA |
118 | u32 quirks; |
119 | }; | |
120 | ||
af4ea631 LKA |
121 | struct s3c2410_wdt { |
122 | struct device *dev; | |
123 | struct clk *clock; | |
124 | void __iomem *reg_base; | |
125 | unsigned int count; | |
126 | spinlock_t lock; | |
127 | unsigned long wtcon_save; | |
128 | unsigned long wtdat_save; | |
129 | struct watchdog_device wdt_device; | |
130 | struct notifier_block freq_transition; | |
4f1f653a LKA |
131 | struct s3c2410_wdt_variant *drv_data; |
132 | struct regmap *pmureg; | |
133 | }; | |
134 | ||
135 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
136 | .quirks = 0 | |
137 | }; | |
138 | ||
139 | #ifdef CONFIG_OF | |
140 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { | |
141 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
142 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
143 | .mask_bit = 20, | |
cffc9a60 DA |
144 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
145 | .rst_stat_bit = 20, | |
146 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
147 | }; |
148 | ||
149 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
150 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
151 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
152 | .mask_bit = 0, | |
cffc9a60 DA |
153 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
154 | .rst_stat_bit = 9, | |
155 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
156 | }; |
157 | ||
158 | static const struct of_device_id s3c2410_wdt_match[] = { | |
159 | { .compatible = "samsung,s3c2410-wdt", | |
160 | .data = &drv_data_s3c2410 }, | |
161 | { .compatible = "samsung,exynos5250-wdt", | |
162 | .data = &drv_data_exynos5250 }, | |
163 | { .compatible = "samsung,exynos5420-wdt", | |
164 | .data = &drv_data_exynos5420 }, | |
165 | {}, | |
af4ea631 | 166 | }; |
4f1f653a LKA |
167 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
168 | #endif | |
169 | ||
170 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
171 | { | |
172 | .name = "s3c2410-wdt", | |
173 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
174 | }, | |
175 | {} | |
176 | }; | |
177 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 LT |
178 | |
179 | /* watchdog control routines */ | |
180 | ||
27c766aa JP |
181 | #define DBG(fmt, ...) \ |
182 | do { \ | |
183 | if (debug) \ | |
184 | pr_info(fmt, ##__VA_ARGS__); \ | |
185 | } while (0) | |
1da177e4 LT |
186 | |
187 | /* functions */ | |
188 | ||
af4ea631 LKA |
189 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
190 | { | |
191 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
192 | } | |
193 | ||
4f1f653a LKA |
194 | static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
195 | { | |
196 | int ret; | |
197 | u32 mask_val = 1 << wdt->drv_data->mask_bit; | |
198 | u32 val = 0; | |
199 | ||
200 | /* No need to do anything if no PMU CONFIG needed */ | |
201 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) | |
202 | return 0; | |
203 | ||
204 | if (mask) | |
205 | val = mask_val; | |
206 | ||
207 | ret = regmap_update_bits(wdt->pmureg, | |
208 | wdt->drv_data->disable_reg, | |
209 | mask_val, val); | |
210 | if (ret < 0) | |
211 | goto error; | |
212 | ||
213 | ret = regmap_update_bits(wdt->pmureg, | |
214 | wdt->drv_data->mask_reset_reg, | |
215 | mask_val, val); | |
216 | error: | |
217 | if (ret < 0) | |
218 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
219 | ||
220 | return ret; | |
221 | } | |
222 | ||
25dc46e3 | 223 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 224 | { |
af4ea631 LKA |
225 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
226 | ||
227 | spin_lock(&wdt->lock); | |
228 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
229 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
230 | |
231 | return 0; | |
1da177e4 LT |
232 | } |
233 | ||
af4ea631 | 234 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
235 | { |
236 | unsigned long wtcon; | |
237 | ||
af4ea631 | 238 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 239 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 240 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
241 | } |
242 | ||
25dc46e3 | 243 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 244 | { |
af4ea631 LKA |
245 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
246 | ||
247 | spin_lock(&wdt->lock); | |
248 | __s3c2410wdt_stop(wdt); | |
249 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
250 | |
251 | return 0; | |
1da177e4 LT |
252 | } |
253 | ||
25dc46e3 | 254 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
255 | { |
256 | unsigned long wtcon; | |
af4ea631 | 257 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 258 | |
af4ea631 | 259 | spin_lock(&wdt->lock); |
41dc8b72 | 260 | |
af4ea631 | 261 | __s3c2410wdt_stop(wdt); |
1da177e4 | 262 | |
af4ea631 | 263 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
264 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
265 | ||
266 | if (soft_noboot) { | |
267 | wtcon |= S3C2410_WTCON_INTEN; | |
268 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
269 | } else { | |
270 | wtcon &= ~S3C2410_WTCON_INTEN; | |
271 | wtcon |= S3C2410_WTCON_RSTEN; | |
272 | } | |
273 | ||
af4ea631 LKA |
274 | DBG("%s: count=0x%08x, wtcon=%08lx\n", |
275 | __func__, wdt->count, wtcon); | |
1da177e4 | 276 | |
af4ea631 LKA |
277 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
278 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
279 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
280 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
281 | |
282 | return 0; | |
1da177e4 LT |
283 | } |
284 | ||
af4ea631 | 285 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 286 | { |
af4ea631 | 287 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
288 | } |
289 | ||
25dc46e3 | 290 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 291 | { |
af4ea631 LKA |
292 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
293 | unsigned long freq = clk_get_rate(wdt->clock); | |
1da177e4 LT |
294 | unsigned int count; |
295 | unsigned int divisor = 1; | |
296 | unsigned long wtcon; | |
297 | ||
298 | if (timeout < 1) | |
299 | return -EINVAL; | |
300 | ||
17862440 | 301 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
302 | count = timeout * freq; |
303 | ||
e02f838e | 304 | DBG("%s: count=%d, timeout=%d, freq=%lu\n", |
fa9363c5 | 305 | __func__, count, timeout, freq); |
1da177e4 LT |
306 | |
307 | /* if the count is bigger than the watchdog register, | |
308 | then work out what we need to do (and if) we can | |
309 | actually make this value | |
310 | */ | |
311 | ||
312 | if (count >= 0x10000) { | |
17862440 | 313 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 314 | |
17862440 | 315 | if (divisor > 0x100) { |
af4ea631 | 316 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
317 | return -EINVAL; |
318 | } | |
319 | } | |
320 | ||
1da177e4 | 321 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", |
17862440 | 322 | __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor)); |
1da177e4 | 323 | |
17862440 | 324 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 325 | wdt->count = count; |
1da177e4 LT |
326 | |
327 | /* update the pre-scaler */ | |
af4ea631 | 328 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
329 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
330 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
331 | ||
af4ea631 LKA |
332 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
333 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 334 | |
5f2430f5 | 335 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 336 | |
1da177e4 LT |
337 | return 0; |
338 | } | |
339 | ||
a77dba7e | 340 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 341 | |
41dc8b72 | 342 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
343 | .options = OPTIONS, |
344 | .firmware_version = 0, | |
345 | .identity = "S3C2410 Watchdog", | |
346 | }; | |
347 | ||
25dc46e3 WS |
348 | static struct watchdog_ops s3c2410wdt_ops = { |
349 | .owner = THIS_MODULE, | |
350 | .start = s3c2410wdt_start, | |
351 | .stop = s3c2410wdt_stop, | |
352 | .ping = s3c2410wdt_keepalive, | |
353 | .set_timeout = s3c2410wdt_set_heartbeat, | |
1da177e4 LT |
354 | }; |
355 | ||
25dc46e3 WS |
356 | static struct watchdog_device s3c2410_wdd = { |
357 | .info = &s3c2410_wdt_ident, | |
358 | .ops = &s3c2410wdt_ops, | |
c1fd5f64 | 359 | .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
360 | }; |
361 | ||
1da177e4 LT |
362 | /* interrupt handler code */ |
363 | ||
7d12e780 | 364 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 365 | { |
af4ea631 | 366 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 367 | |
af4ea631 LKA |
368 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
369 | ||
370 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
1da177e4 LT |
371 | return IRQ_HANDLED; |
372 | } | |
e02f838e | 373 | |
0f1dd98d | 374 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
375 | |
376 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
377 | unsigned long val, void *data) | |
378 | { | |
379 | int ret; | |
af4ea631 | 380 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 381 | |
af4ea631 | 382 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
383 | goto done; |
384 | ||
385 | if (val == CPUFREQ_PRECHANGE) { | |
386 | /* To ensure that over the change we don't cause the | |
387 | * watchdog to trigger, we perform an keep-alive if | |
388 | * the watchdog is running. | |
389 | */ | |
390 | ||
af4ea631 | 391 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 392 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 393 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 394 | |
af4ea631 LKA |
395 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
396 | wdt->wdt_device.timeout); | |
e02f838e BD |
397 | |
398 | if (ret >= 0) | |
af4ea631 | 399 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
400 | else |
401 | goto err; | |
402 | } | |
403 | ||
404 | done: | |
405 | return 0; | |
406 | ||
407 | err: | |
af4ea631 LKA |
408 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
409 | wdt->wdt_device.timeout); | |
e02f838e BD |
410 | return ret; |
411 | } | |
412 | ||
af4ea631 | 413 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 414 | { |
af4ea631 LKA |
415 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
416 | ||
417 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
418 | CPUFREQ_TRANSITION_NOTIFIER); |
419 | } | |
420 | ||
af4ea631 | 421 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 422 | { |
af4ea631 LKA |
423 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
424 | ||
425 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
426 | CPUFREQ_TRANSITION_NOTIFIER); |
427 | } | |
428 | ||
429 | #else | |
af4ea631 LKA |
430 | |
431 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
432 | { |
433 | return 0; | |
434 | } | |
435 | ||
af4ea631 | 436 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
437 | { |
438 | } | |
439 | #endif | |
440 | ||
cffc9a60 DA |
441 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
442 | { | |
443 | unsigned int rst_stat; | |
444 | int ret; | |
445 | ||
446 | if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) | |
447 | return 0; | |
448 | ||
449 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
450 | if (ret) | |
451 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
452 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
453 | return WDIOF_CARDRESET; | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
4f1f653a LKA |
458 | /* s3c2410_get_wdt_driver_data */ |
459 | static inline struct s3c2410_wdt_variant * | |
460 | get_wdt_drv_data(struct platform_device *pdev) | |
461 | { | |
462 | if (pdev->dev.of_node) { | |
463 | const struct of_device_id *match; | |
464 | match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node); | |
465 | return (struct s3c2410_wdt_variant *)match->data; | |
466 | } else { | |
467 | return (struct s3c2410_wdt_variant *) | |
468 | platform_get_device_id(pdev)->driver_data; | |
469 | } | |
470 | } | |
471 | ||
2d991a16 | 472 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 473 | { |
e8ef92b8 | 474 | struct device *dev; |
af4ea631 LKA |
475 | struct s3c2410_wdt *wdt; |
476 | struct resource *wdt_mem; | |
477 | struct resource *wdt_irq; | |
46b814d6 | 478 | unsigned int wtcon; |
1da177e4 LT |
479 | int started = 0; |
480 | int ret; | |
1da177e4 | 481 | |
fa9363c5 | 482 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 483 | |
e8ef92b8 | 484 | dev = &pdev->dev; |
e8ef92b8 | 485 | |
af4ea631 LKA |
486 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
487 | if (!wdt) | |
488 | return -ENOMEM; | |
489 | ||
490 | wdt->dev = &pdev->dev; | |
491 | spin_lock_init(&wdt->lock); | |
492 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 493 | |
4f1f653a | 494 | wdt->drv_data = get_wdt_drv_data(pdev); |
cffc9a60 | 495 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
496 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
497 | "samsung,syscon-phandle"); | |
498 | if (IS_ERR(wdt->pmureg)) { | |
499 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
500 | return PTR_ERR(wdt->pmureg); | |
501 | } | |
502 | } | |
503 | ||
78d3e00b MH |
504 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
505 | if (wdt_irq == NULL) { | |
506 | dev_err(dev, "no irq resource specified\n"); | |
507 | ret = -ENOENT; | |
508 | goto err; | |
509 | } | |
510 | ||
511 | /* get the memory region for the watchdog timer */ | |
bd5cc119 | 512 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
af4ea631 LKA |
513 | wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); |
514 | if (IS_ERR(wdt->reg_base)) { | |
515 | ret = PTR_ERR(wdt->reg_base); | |
04ecc7dc | 516 | goto err; |
1da177e4 LT |
517 | } |
518 | ||
af4ea631 | 519 | DBG("probe: mapped reg_base=%p\n", wdt->reg_base); |
1da177e4 | 520 | |
af4ea631 LKA |
521 | wdt->clock = devm_clk_get(dev, "watchdog"); |
522 | if (IS_ERR(wdt->clock)) { | |
e8ef92b8 | 523 | dev_err(dev, "failed to find watchdog clock source\n"); |
af4ea631 | 524 | ret = PTR_ERR(wdt->clock); |
04ecc7dc | 525 | goto err; |
1da177e4 LT |
526 | } |
527 | ||
af4ea631 | 528 | clk_prepare_enable(wdt->clock); |
1da177e4 | 529 | |
af4ea631 | 530 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 531 | if (ret < 0) { |
3828924a | 532 | dev_err(dev, "failed to register cpufreq\n"); |
e02f838e BD |
533 | goto err_clk; |
534 | } | |
535 | ||
af4ea631 LKA |
536 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
537 | ||
1da177e4 LT |
538 | /* see if we can actually set the requested timer margin, and if |
539 | * not, try the default value */ | |
540 | ||
af4ea631 LKA |
541 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); |
542 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
543 | wdt->wdt_device.timeout); | |
544 | if (ret) { | |
545 | started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
41dc8b72 | 546 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 547 | |
41dc8b72 AC |
548 | if (started == 0) |
549 | dev_info(dev, | |
550 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 551 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 552 | else |
a77dba7e WVS |
553 | dev_info(dev, "default timer value is out of range, " |
554 | "cannot start\n"); | |
1da177e4 LT |
555 | } |
556 | ||
04ecc7dc JH |
557 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
558 | pdev->name, pdev); | |
78d3e00b MH |
559 | if (ret != 0) { |
560 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
561 | goto err_cpufreq; | |
562 | } | |
563 | ||
af4ea631 | 564 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
ff0b3cd4 | 565 | |
cffc9a60 DA |
566 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
567 | ||
af4ea631 | 568 | ret = watchdog_register_device(&wdt->wdt_device); |
1da177e4 | 569 | if (ret) { |
25dc46e3 | 570 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 571 | goto err_cpufreq; |
1da177e4 LT |
572 | } |
573 | ||
4f1f653a LKA |
574 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
575 | if (ret < 0) | |
576 | goto err_unregister; | |
577 | ||
1da177e4 | 578 | if (tmr_atboot && started == 0) { |
e8ef92b8 | 579 | dev_info(dev, "starting watchdog timer\n"); |
af4ea631 | 580 | s3c2410wdt_start(&wdt->wdt_device); |
655516c8 BD |
581 | } else if (!tmr_atboot) { |
582 | /* if we're not enabling the watchdog, then ensure it is | |
583 | * disabled if it has been left running from the bootloader | |
584 | * or other source */ | |
585 | ||
af4ea631 | 586 | s3c2410wdt_stop(&wdt->wdt_device); |
1da177e4 LT |
587 | } |
588 | ||
af4ea631 LKA |
589 | platform_set_drvdata(pdev, wdt); |
590 | ||
46b814d6 BD |
591 | /* print out a statement of readiness */ |
592 | ||
af4ea631 | 593 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 594 | |
e8ef92b8 | 595 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 596 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
597 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
598 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 599 | |
1da177e4 | 600 | return 0; |
0b6dd8a6 | 601 | |
4f1f653a LKA |
602 | err_unregister: |
603 | watchdog_unregister_device(&wdt->wdt_device); | |
604 | ||
e02f838e | 605 | err_cpufreq: |
af4ea631 | 606 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 607 | |
0b6dd8a6 | 608 | err_clk: |
af4ea631 | 609 | clk_disable_unprepare(wdt->clock); |
0b6dd8a6 | 610 | |
78d3e00b | 611 | err: |
0b6dd8a6 | 612 | return ret; |
1da177e4 LT |
613 | } |
614 | ||
4b12b896 | 615 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 616 | { |
4f1f653a | 617 | int ret; |
af4ea631 LKA |
618 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
619 | ||
4f1f653a LKA |
620 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
621 | if (ret < 0) | |
622 | return ret; | |
623 | ||
af4ea631 | 624 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 625 | |
af4ea631 | 626 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 627 | |
af4ea631 | 628 | clk_disable_unprepare(wdt->clock); |
1da177e4 | 629 | |
1da177e4 LT |
630 | return 0; |
631 | } | |
632 | ||
3ae5eaec | 633 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 634 | { |
af4ea631 LKA |
635 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
636 | ||
4f1f653a LKA |
637 | s3c2410wdt_mask_and_disable_reset(wdt, true); |
638 | ||
af4ea631 | 639 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
640 | } |
641 | ||
0183984c | 642 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 643 | |
0183984c | 644 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 645 | { |
4f1f653a | 646 | int ret; |
af4ea631 LKA |
647 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
648 | ||
9480e307 | 649 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
650 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
651 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 652 | |
4f1f653a LKA |
653 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
654 | if (ret < 0) | |
655 | return ret; | |
656 | ||
9480e307 | 657 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 658 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
659 | |
660 | return 0; | |
661 | } | |
662 | ||
0183984c | 663 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 664 | { |
4f1f653a | 665 | int ret; |
af4ea631 | 666 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 667 | |
af4ea631 LKA |
668 | /* Restore watchdog state. */ |
669 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
670 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
671 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 672 | |
4f1f653a LKA |
673 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
674 | if (ret < 0) | |
675 | return ret; | |
676 | ||
0183984c | 677 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 678 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
679 | |
680 | return 0; | |
681 | } | |
0183984c | 682 | #endif |
af4bb822 | 683 | |
0183984c JH |
684 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
685 | s3c2410wdt_resume); | |
af4bb822 | 686 | |
3ae5eaec | 687 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 688 | .probe = s3c2410wdt_probe, |
82268714 | 689 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 690 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 691 | .id_table = s3c2410_wdt_ids, |
3ae5eaec RK |
692 | .driver = { |
693 | .owner = THIS_MODULE, | |
694 | .name = "s3c2410-wdt", | |
0183984c | 695 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 696 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 697 | }, |
1da177e4 LT |
698 | }; |
699 | ||
6b761b29 | 700 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 701 | |
af4bb822 BD |
702 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
703 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
704 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
705 | MODULE_LICENSE("GPL"); |