[mirror_ubuntu-jammy-kernel.git] / drivers / watchdog / sama5d4_wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Atmel SAMA5D4 Watchdog Timer
 *
 * Copyright (C) 2015-2019 Microchip Technology Inc. and its subsidiaries
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/watchdog.h>

#include "at91sam9_wdt.h"

/* minimum and maximum watchdog timeout, in seconds */
#define MIN_WDT_TIMEOUT		1
#define MAX_WDT_TIMEOUT		16
#define WDT_DEFAULT_TIMEOUT	MAX_WDT_TIMEOUT

#define WDT_SEC2TICKS(s)	((s) ? (((s) << 8) - 1) : 0)

struct sama5d4_wdt {
	struct watchdog_device	wdd;
	void __iomem		*reg_base;
	u32			mr;
	u32			ir;
	unsigned long		last_ping;
	bool			need_irq;
	bool			sam9x60_support;
};

static int wdt_timeout;
static bool nowayout = WATCHDOG_NOWAYOUT;

module_param(wdt_timeout, int, 0);
MODULE_PARM_DESC(wdt_timeout,
	"Watchdog timeout in seconds. (default = "
	__MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

#define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))

#define wdt_read(wdt, field) \
	readl_relaxed((wdt)->reg_base + (field))

/* 4 slow clock periods is 4/32768 = 122.07µs*/
#define WDT_DELAY	usecs_to_jiffies(123)

static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
{
	/*
	 * WDT_CR and WDT_MR must not be modified within three slow clock
	 * periods following a restart of the watchdog performed by a write
	 * access in WDT_CR.
	 */
	while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
		usleep_range(30, 125);
	writel_relaxed(val, wdt->reg_base + field);
	wdt->last_ping = jiffies;
}

static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
{
	if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
		udelay(123);
	writel_relaxed(val, wdt->reg_base + field);
	wdt->last_ping = jiffies;
}

static int sama5d4_wdt_start(struct watchdog_device *wdd)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);

	if (wdt->sam9x60_support) {
		writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER);
		wdt->mr &= ~AT91_SAM9X60_WDDIS;
	} else {
		wdt->mr &= ~AT91_WDT_WDDIS;
	}
	wdt_write(wdt, AT91_WDT_MR, wdt->mr);

	return 0;
}

static int sama5d4_wdt_stop(struct watchdog_device *wdd)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);

	if (wdt->sam9x60_support) {
		writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR);
		wdt->mr |= AT91_SAM9X60_WDDIS;
	} else {
		wdt->mr |= AT91_WDT_WDDIS;
	}
	wdt_write(wdt, AT91_WDT_MR, wdt->mr);

	return 0;
}

static int sama5d4_wdt_ping(struct watchdog_device *wdd)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);

	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);

	return 0;
}

static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd,
				 unsigned int timeout)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
	u32 value = WDT_SEC2TICKS(timeout);

	if (wdt->sam9x60_support) {
		wdt_write(wdt, AT91_SAM9X60_WLR,
			  AT91_SAM9X60_SET_COUNTER(value));

		wdd->timeout = timeout;
		return 0;
	}

	wdt->mr &= ~AT91_WDT_WDV;
	wdt->mr |= AT91_WDT_SET_WDV(value);

	/*
	 * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When
	 * setting the WDDIS bit, and while it is set, the fields WDV and WDD
	 * must not be modified.
	 * If the watchdog is enabled, then the timeout can be updated. Else,
	 * wait that the user enables it.
	 */
	if (wdt_enabled)
		wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);

	wdd->timeout = timeout;

	return 0;
}

static const struct watchdog_info sama5d4_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
	.identity = "Atmel SAMA5D4 Watchdog",
};

static const struct watchdog_ops sama5d4_wdt_ops = {
	.owner = THIS_MODULE,
	.start = sama5d4_wdt_start,
	.stop = sama5d4_wdt_stop,
	.ping = sama5d4_wdt_ping,
	.set_timeout = sama5d4_wdt_set_timeout,
};

static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id)
{
	struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);
	u32 reg;

	if (wdt->sam9x60_support)
		reg = wdt_read(wdt, AT91_SAM9X60_ISR);
	else
		reg = wdt_read(wdt, AT91_WDT_SR);

	if (reg) {
		pr_crit("Atmel Watchdog Software Reset\n");
		emergency_restart();
		pr_crit("Reboot didn't succeed\n");
	}

	return IRQ_HANDLED;
}

static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt)
{
	const char *tmp;

	if (wdt->sam9x60_support)
		wdt->mr = AT91_SAM9X60_WDDIS;
	else
		wdt->mr = AT91_WDT_WDDIS;

	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
	    !strcmp(tmp, "software"))
		wdt->need_irq = true;

	if (of_property_read_bool(np, "atmel,idle-halt"))
		wdt->mr |= AT91_WDT_WDIDLEHLT;

	if (of_property_read_bool(np, "atmel,dbg-halt"))
		wdt->mr |= AT91_WDT_WDDBGHLT;

	return 0;
}

static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
{
	u32 reg, val;

	val = WDT_SEC2TICKS(WDT_DEFAULT_TIMEOUT);
	/*
	 * When booting and resuming, the bootloader may have changed the
	 * watchdog configuration.
	 * If the watchdog is already running, we can safely update it.
	 * Else, we have to disable it properly.
	 */
	if (!wdt_enabled) {
		reg = wdt_read(wdt, AT91_WDT_MR);
		if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS)))
			wdt_write_nosleep(wdt, AT91_WDT_MR,
					  reg | AT91_SAM9X60_WDDIS);
		else if (!wdt->sam9x60_support &&
			 (!(reg & AT91_WDT_WDDIS)))
			wdt_write_nosleep(wdt, AT91_WDT_MR,
					  reg | AT91_WDT_WDDIS);
	}

	if (wdt->sam9x60_support) {
		if (wdt->need_irq)
			wdt->ir = AT91_SAM9X60_PERINT;
		else
			wdt->mr |= AT91_SAM9X60_PERIODRST;

		wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir);
		wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(val));
	} else {
		wdt->mr |= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT));
		wdt->mr |= AT91_WDT_SET_WDV(val);

		if (wdt->need_irq)
			wdt->mr |= AT91_WDT_WDFIEN;
		else
			wdt->mr |= AT91_WDT_WDRSTEN;
	}

	wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);

	return 0;
}

static int sama5d4_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct sama5d4_wdt *wdt;
	void __iomem *regs;
	u32 irq = 0;
	int ret;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdd = &wdt->wdd;
	wdd->timeout = WDT_DEFAULT_TIMEOUT;
	wdd->info = &sama5d4_wdt_info;
	wdd->ops = &sama5d4_wdt_ops;
	wdd->min_timeout = MIN_WDT_TIMEOUT;
	wdd->max_timeout = MAX_WDT_TIMEOUT;
	wdt->last_ping = jiffies;

	if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") ||
	    of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt"))
		wdt->sam9x60_support = true;

	watchdog_set_drvdata(wdd, wdt);

	regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	wdt->reg_base = regs;

	ret = of_sama5d4_wdt_init(dev->of_node, wdt);
	if (ret)
		return ret;

	if (wdt->need_irq) {
		irq = irq_of_parse_and_map(dev->of_node, 0);
		if (!irq) {
			dev_warn(dev, "failed to get IRQ from DT\n");
			wdt->need_irq = false;
		}
	}

	if (wdt->need_irq) {
		ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler,
				       IRQF_SHARED | IRQF_IRQPOLL |
				       IRQF_NO_SUSPEND, pdev->name, pdev);
		if (ret) {
			dev_err(dev, "cannot register interrupt handler\n");
			return ret;
		}
	}

	watchdog_init_timeout(wdd, wdt_timeout, dev);

	ret = sama5d4_wdt_init(wdt);
	if (ret)
		return ret;

	watchdog_set_nowayout(wdd, nowayout);

	watchdog_stop_on_unregister(wdd);
	ret = devm_watchdog_register_device(dev, wdd);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, wdt);

	dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
		 wdd->timeout, nowayout);

	return 0;
}

static const struct of_device_id sama5d4_wdt_of_match[] = {
	{
		.compatible = "atmel,sama5d4-wdt",
	},
	{
		.compatible = "microchip,sam9x60-wdt",
	},
	{
		.compatible = "microchip,sama7g5-wdt",
	},

	{ }
};
MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);

#ifdef CONFIG_PM_SLEEP
static int sama5d4_wdt_suspend_late(struct device *dev)
{
	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		sama5d4_wdt_stop(&wdt->wdd);

	return 0;
}

static int sama5d4_wdt_resume_early(struct device *dev)
{
	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);

	/*
	 * FIXME: writing MR also pings the watchdog which may not be desired.
	 * This should only be done when the registers are lost on suspend but
	 * there is no way to get this information right now.
	 */
	sama5d4_wdt_init(wdt);

	if (watchdog_active(&wdt->wdd))
		sama5d4_wdt_start(&wdt->wdd);

	return 0;
}
#endif

static const struct dev_pm_ops sama5d4_wdt_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late,
			sama5d4_wdt_resume_early)
};

static struct platform_driver sama5d4_wdt_driver = {
	.probe		= sama5d4_wdt_probe,
	.driver		= {
		.name	= "sama5d4_wdt",
		.pm	= &sama5d4_wdt_pm_ops,
		.of_match_table = sama5d4_wdt_of_match,
	}
};
module_platform_driver(sama5d4_wdt_driver);

MODULE_AUTHOR("Atmel Corporation");
MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f50a7f3d	1	// SPDX-License-Identifier: GPL-2.0-only
76534860 WY	2	/*
	3	* Driver for Atmel SAMA5D4 Watchdog Timer
	4	*
bb44aa09	5	* Copyright (C) 2015-2019 Microchip Technology Inc. and its subsidiaries
76534860 WY	6	*/
76534860 WY	7
ddd6d240	8	#include <linux/delay.h>
76534860 WY	9	#include <linux/interrupt.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
bb44aa09	14	#include <linux/of_device.h>
76534860 WY	15	#include <linux/of_irq.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/reboot.h>
	18	#include <linux/watchdog.h>
	19
	20	#include "at91sam9_wdt.h"
	21
	22	/* minimum and maximum watchdog timeout, in seconds */
	23	#define MIN_WDT_TIMEOUT 1
	24	#define MAX_WDT_TIMEOUT 16
	25	#define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT
	26
	27	#define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0)
	28
	29	struct sama5d4_wdt {
	30	struct watchdog_device wdd;
	31	void __iomem *reg_base;
722ce635	32	u32 mr;
bb44aa09	33	u32 ir;
ddd6d240	34	unsigned long last_ping;
bb44aa09 EH	35	bool need_irq;
bb44aa09 EH	36	bool sam9x60_support;
76534860 WY	37	};
76534860 WY	38
976932e4	39	static int wdt_timeout;
76534860 WY	40	static bool nowayout = WATCHDOG_NOWAYOUT;
	41
	42	module_param(wdt_timeout, int, 0);
	43	MODULE_PARM_DESC(wdt_timeout,
	44	"Watchdog timeout in seconds. (default = "
	45	__MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
	46
	47	module_param(nowayout, bool, 0);
	48	MODULE_PARM_DESC(nowayout,
	49	"Watchdog cannot be stopped once started (default="
	50	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	51
015b5286 AB	52	#define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
015b5286 AB	53
76534860 WY	54	#define wdt_read(wdt, field) \
	55	readl_relaxed((wdt)->reg_base + (field))
	56
ddd6d240 AB	57	/* 4 slow clock periods is 4/32768 = 122.07µs*/
	58	#define WDT_DELAY usecs_to_jiffies(123)
	59
	60	static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
	61	{
	62	/*
	63	* WDT_CR and WDT_MR must not be modified within three slow clock
	64	* periods following a restart of the watchdog performed by a write
	65	* access in WDT_CR.
	66	*/
	67	while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
	68	usleep_range(30, 125);
	69	writel_relaxed(val, wdt->reg_base + field);
	70	wdt->last_ping = jiffies;
	71	}
	72
	73	static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
	74	{
	75	if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
	76	udelay(123);
	77	writel_relaxed(val, wdt->reg_base + field);
	78	wdt->last_ping = jiffies;
	79	}
76534860 WY	80
	81	static int sama5d4_wdt_start(struct watchdog_device *wdd)
	82	{
	83	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
76534860	84
bb44aa09 EH	85	if (wdt->sam9x60_support) {
	86	writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER);
	87	wdt->mr &= ~AT91_SAM9X60_WDDIS;
	88	} else {
	89	wdt->mr &= ~AT91_WDT_WDDIS;
	90	}
722ce635	91	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
76534860 WY	92
	93	return 0;
	94	}
	95
	96	static int sama5d4_wdt_stop(struct watchdog_device *wdd)
	97	{
	98	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
76534860	99
bb44aa09 EH	100	if (wdt->sam9x60_support) {
	101	writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR);
	102	wdt->mr \|= AT91_SAM9X60_WDDIS;
	103	} else {
	104	wdt->mr \|= AT91_WDT_WDDIS;
	105	}
722ce635	106	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
76534860 WY	107
	108	return 0;
	109	}
	110
	111	static int sama5d4_wdt_ping(struct watchdog_device *wdd)
	112	{
	113	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
	114
	115	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY \| AT91_WDT_WDRSTT);
	116
	117	return 0;
	118	}
	119
	120	static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd,
	121	unsigned int timeout)
	122	{
	123	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
	124	u32 value = WDT_SEC2TICKS(timeout);
76534860	125
bb44aa09 EH	126	if (wdt->sam9x60_support) {
	127	wdt_write(wdt, AT91_SAM9X60_WLR,
	128	AT91_SAM9X60_SET_COUNTER(value));
	129
	130	wdd->timeout = timeout;
	131	return 0;
	132	}
	133
722ce635	134	wdt->mr &= ~AT91_WDT_WDV;
722ce635	135	wdt->mr \|= AT91_WDT_SET_WDV(value);
015b5286 AB	136
	137	/*
	138	* WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When
	139	* setting the WDDIS bit, and while it is set, the fields WDV and WDD
	140	* must not be modified.
	141	* If the watchdog is enabled, then the timeout can be updated. Else,
	142	* wait that the user enables it.
	143	*/
	144	if (wdt_enabled)
	145	wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);
76534860 WY	146
	147	wdd->timeout = timeout;
	148
	149	return 0;
	150	}
	151
	152	static const struct watchdog_info sama5d4_wdt_info = {
	153	.options = WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING,
	154	.identity = "Atmel SAMA5D4 Watchdog",
	155	};
	156
b893e344	157	static const struct watchdog_ops sama5d4_wdt_ops = {
76534860 WY	158	.owner = THIS_MODULE,
	159	.start = sama5d4_wdt_start,
	160	.stop = sama5d4_wdt_stop,
	161	.ping = sama5d4_wdt_ping,
	162	.set_timeout = sama5d4_wdt_set_timeout,
	163	};
	164
	165	static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id)
	166	{
	167	struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);
bb44aa09	168	u32 reg;
76534860	169
bb44aa09 EH	170	if (wdt->sam9x60_support)
	171	reg = wdt_read(wdt, AT91_SAM9X60_ISR);
	172	else
	173	reg = wdt_read(wdt, AT91_WDT_SR);
	174
	175	if (reg) {
76534860 WY	176	pr_crit("Atmel Watchdog Software Reset\n");
	177	emergency_restart();
	178	pr_crit("Reboot didn't succeed\n");
	179	}
	180
	181	return IRQ_HANDLED;
	182	}
	183
	184	static int of_sama5d4_wdt_init(struct device_node np, struct sama5d4_wdt wdt)
	185	{
	186	const char *tmp;
	187
bb44aa09 EH	188	if (wdt->sam9x60_support)
	189	wdt->mr = AT91_SAM9X60_WDDIS;
	190	else
	191	wdt->mr = AT91_WDT_WDDIS;
76534860 WY	192
	193	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
	194	!strcmp(tmp, "software"))
bb44aa09	195	wdt->need_irq = true;
76534860 WY	196
76534860 WY	197	if (of_property_read_bool(np, "atmel,idle-halt"))
722ce635	198	wdt->mr \|= AT91_WDT_WDIDLEHLT;
76534860 WY	199
76534860 WY	200	if (of_property_read_bool(np, "atmel,dbg-halt"))
722ce635	201	wdt->mr \|= AT91_WDT_WDDBGHLT;
76534860 WY	202
	203	return 0;
	204	}
	205
	206	static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
	207	{
bb44aa09 EH	208	u32 reg, val;
	209
	210	val = WDT_SEC2TICKS(WDT_DEFAULT_TIMEOUT);
76534860	211	/*
015b5286 AB	212	* When booting and resuming, the bootloader may have changed the
	213	* watchdog configuration.
	214	* If the watchdog is already running, we can safely update it.
	215	* Else, we have to disable it properly.
76534860	216	*/
bb44aa09	217	if (!wdt_enabled) {
015b5286	218	reg = wdt_read(wdt, AT91_WDT_MR);
bb44aa09 EH	219	if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS)))
	220	wdt_write_nosleep(wdt, AT91_WDT_MR,
	221	reg \| AT91_SAM9X60_WDDIS);
	222	else if (!wdt->sam9x60_support &&
	223	(!(reg & AT91_WDT_WDDIS)))
ddd6d240 AB	224	wdt_write_nosleep(wdt, AT91_WDT_MR,
ddd6d240 AB	225	reg \| AT91_WDT_WDDIS);
015b5286	226	}
bb44aa09 EH	227
	228	if (wdt->sam9x60_support) {
	229	if (wdt->need_irq)
	230	wdt->ir = AT91_SAM9X60_PERINT;
	231	else
	232	wdt->mr \|= AT91_SAM9X60_PERIODRST;
	233
	234	wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir);
	235	wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(val));
	236	} else {
	237	wdt->mr \|= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT));
	238	wdt->mr \|= AT91_WDT_SET_WDV(val);
	239
	240	if (wdt->need_irq)
	241	wdt->mr \|= AT91_WDT_WDFIEN;
	242	else
	243	wdt->mr \|= AT91_WDT_WDRSTEN;
	244	}
	245
	246	wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);
	247
76534860 WY	248	return 0;
	249	}
	250
	251	static int sama5d4_wdt_probe(struct platform_device *pdev)
	252	{
dcc3ce0b	253	struct device *dev = &pdev->dev;
76534860 WY	254	struct watchdog_device *wdd;
76534860 WY	255	struct sama5d4_wdt *wdt;
76534860 WY	256	void __iomem *regs;
	257	u32 irq = 0;
	258	int ret;
	259
dcc3ce0b	260	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
76534860 WY	261	if (!wdt)
	262	return -ENOMEM;
	263
	264	wdd = &wdt->wdd;
976932e4	265	wdd->timeout = WDT_DEFAULT_TIMEOUT;
76534860 WY	266	wdd->info = &sama5d4_wdt_info;
	267	wdd->ops = &sama5d4_wdt_ops;
	268	wdd->min_timeout = MIN_WDT_TIMEOUT;
	269	wdd->max_timeout = MAX_WDT_TIMEOUT;
ddd6d240	270	wdt->last_ping = jiffies;
5ae233fb EH	271
	272	if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") \|\|
	273	of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt"))
	274	wdt->sam9x60_support = true;
76534860 WY	275
	276	watchdog_set_drvdata(wdd, wdt);
	277
0f0a6a28	278	regs = devm_platform_ioremap_resource(pdev, 0);
76534860 WY	279	if (IS_ERR(regs))
	280	return PTR_ERR(regs);
	281
	282	wdt->reg_base = regs;
	283
dcc3ce0b	284	ret = of_sama5d4_wdt_init(dev->of_node, wdt);
39bd56df AB	285	if (ret)
39bd56df AB	286	return ret;
76534860	287
bb44aa09 EH	288	if (wdt->need_irq) {
	289	irq = irq_of_parse_and_map(dev->of_node, 0);
	290	if (!irq) {
	291	dev_warn(dev, "failed to get IRQ from DT\n");
	292	wdt->need_irq = false;
	293	}
	294	}
	295
	296	if (wdt->need_irq) {
dcc3ce0b	297	ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler,
76534860 WY	298	IRQF_SHARED \| IRQF_IRQPOLL \|
	299	IRQF_NO_SUSPEND, pdev->name, pdev);
	300	if (ret) {
dcc3ce0b	301	dev_err(dev, "cannot register interrupt handler\n");
76534860 WY	302	return ret;
	303	}
	304	}
	305
dcc3ce0b	306	watchdog_init_timeout(wdd, wdt_timeout, dev);
76534860 WY	307
	308	ret = sama5d4_wdt_init(wdt);
	309	if (ret)
	310	return ret;
	311
	312	watchdog_set_nowayout(wdd, nowayout);
	313
dcc3ce0b GR	314	watchdog_stop_on_unregister(wdd);
dcc3ce0b GR	315	ret = devm_watchdog_register_device(dev, wdd);
24b8eb74	316	if (ret)
76534860	317	return ret;
76534860 WY	318
	319	platform_set_drvdata(pdev, wdt);
	320
dcc3ce0b	321	dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
976932e4	322	wdd->timeout, nowayout);
76534860 WY	323
	324	return 0;
	325	}
	326
76534860	327	static const struct of_device_id sama5d4_wdt_of_match[] = {
bb44aa09 EH	328	{
	329	.compatible = "atmel,sama5d4-wdt",
	330	},
	331	{
	332	.compatible = "microchip,sam9x60-wdt",
	333	},
5ae233fb EH	334	{
	335	.compatible = "microchip,sama7g5-wdt",
	336	},
	337
76534860 WY	338	{ }
	339	};
	340	MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);
	341
f2013532	342	#ifdef CONFIG_PM_SLEEP
8d209eb0 KS	343	static int sama5d4_wdt_suspend_late(struct device *dev)
	344	{
	345	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
	346
	347	if (watchdog_active(&wdt->wdd))
	348	sama5d4_wdt_stop(&wdt->wdd);
	349
	350	return 0;
	351	}
	352
	353	static int sama5d4_wdt_resume_early(struct device *dev)
f2013532 AB	354	{
	355	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
	356
5dca80f6 AB	357	/*
	358	* FIXME: writing MR also pings the watchdog which may not be desired.
	359	* This should only be done when the registers are lost on suspend but
	360	* there is no way to get this information right now.
	361	*/
015b5286	362	sama5d4_wdt_init(wdt);
f2013532	363
8d209eb0 KS	364	if (watchdog_active(&wdt->wdd))
	365	sama5d4_wdt_start(&wdt->wdd);
	366
f2013532 AB	367	return 0;
	368	}
	369	#endif
	370
8d209eb0 KS	371	static const struct dev_pm_ops sama5d4_wdt_pm_ops = {
	372	SET_LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late,
	373	sama5d4_wdt_resume_early)
	374	};
f2013532	375
76534860 WY	376	static struct platform_driver sama5d4_wdt_driver = {
76534860 WY	377	.probe = sama5d4_wdt_probe,
76534860 WY	378	.driver = {
76534860 WY	379	.name = "sama5d4_wdt",
f2013532	380	.pm = &sama5d4_wdt_pm_ops,
76534860 WY	381	.of_match_table = sama5d4_wdt_of_match,
	382	}
	383	};
	384	module_platform_driver(sama5d4_wdt_driver);
	385
	386	MODULE_AUTHOR("Atmel Corporation");
	387	MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver");
	388	MODULE_LICENSE("GPL v2");