[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / sbsa_gwdt.c

/*
 * SBSA(Server Base System Architecture) Generic Watchdog driver
 *
 * Copyright (c) 2015, Linaro Ltd.
 * Author: Fu Wei <fu.wei@linaro.org>
 *         Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
 *         Al Stone <al.stone@linaro.org>
 *         Timur Tabi <timur@codeaurora.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License 2 as published
 * by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * ARM SBSA Generic Watchdog has two stage timeouts:
 * the first signal (WS0) is for alerting the system by interrupt,
 * the second one (WS1) is a real hardware reset.
 * More details about the hardware specification of this device:
 * ARM DEN0029B - Server Base System Architecture (SBSA)
 *
 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
 * or a two stages watchdog, it's set up by the module parameter "action".
 * In the single stage mode, when the timeout is reached, your system
 * will be reset by WS1. The first signal (WS0) is ignored.
 * In the two stages mode, when the timeout is reached, the first signal (WS0)
 * will trigger panic. If the system is getting into trouble and cannot be reset
 * by panic or restart properly by the kdump kernel(if supported), then the
 * second stage (as long as the first stage) will be reached, system will be
 * reset by WS1. This function can help administrator to backup the system
 * context info by panic console output or kdump.
 *
 * SBSA GWDT:
 * if action is 1 (the two stages mode):
 * |--------WOR-------WS0--------WOR-------WS1
 * |----timeout-----(panic)----timeout-----reset
 *
 * if action is 0 (the single stage mode):
 * |------WOR-----WS0(ignored)-----WOR------WS1
 * |--------------timeout-------------------reset
 *
 * Note: Since this watchdog timer has two stages, and each stage is determined
 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
 * stages mode, the timeout is WOR. The maximum timeout in the two stages mode
 * is half of that in the single stage mode.
 *
 */

#include <linux/io.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/watchdog.h>
#include <asm/arch_timer.h>

#define DRV_NAME		"sbsa-gwdt"
#define WATCHDOG_NAME		"SBSA Generic Watchdog"

/* SBSA Generic Watchdog register definitions */
/* refresh frame */
#define SBSA_GWDT_WRR		0x000

/* control frame */
#define SBSA_GWDT_WCS		0x000
#define SBSA_GWDT_WOR		0x008
#define SBSA_GWDT_WCV		0x010

/* refresh/control frame */
#define SBSA_GWDT_W_IIDR	0xfcc
#define SBSA_GWDT_IDR		0xfd0

/* Watchdog Control and Status Register */
#define SBSA_GWDT_WCS_EN	BIT(0)
#define SBSA_GWDT_WCS_WS0	BIT(1)
#define SBSA_GWDT_WCS_WS1	BIT(2)

/**
 * struct sbsa_gwdt - Internal representation of the SBSA GWDT
 * @wdd:		kernel watchdog_device structure
 * @clk:		store the System Counter clock frequency, in Hz.
 * @refresh_base:	Virtual address of the watchdog refresh frame
 * @control_base:	Virtual address of the watchdog control frame
 */
struct sbsa_gwdt {
	struct watchdog_device	wdd;
	u32			clk;
	void __iomem		*refresh_base;
	void __iomem		*control_base;
};

#define DEFAULT_TIMEOUT		10 /* seconds */

static unsigned int timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout,
		 "Watchdog timeout in seconds. (>=0, default="
		 __MODULE_STRING(DEFAULT_TIMEOUT) ")");

/*
 * action refers to action taken when watchdog gets WS0
 * 0 = skip
 * 1 = panic
 * defaults to skip (0)
 */
static int action;
module_param(action, int, 0);
MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
		 "0 = skip(*)  1 = panic");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, S_IRUGO);
MODULE_PARM_DESC(nowayout,
		 "Watchdog cannot be stopped once started (default="
		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/*
 * watchdog operation functions
 */
static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
				 unsigned int timeout)
{
	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);

	wdd->timeout = timeout;

	if (action)
		writel(gwdt->clk * timeout,
		       gwdt->control_base + SBSA_GWDT_WOR);
	else
		/*
		 * In the single stage mode, The first signal (WS0) is ignored,
		 * the timeout is (WOR * 2), so the WOR should be configured
		 * to half value of timeout.
		 */
		writel(gwdt->clk / 2 * timeout,
		       gwdt->control_base + SBSA_GWDT_WOR);

	return 0;
}

static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
{
	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
	u64 timeleft = 0;

	/*
	 * In the single stage mode, if WS0 is deasserted
	 * (watchdog is in the first stage),
	 * timeleft = WOR + (WCV - system counter)
	 */
	if (!action &&
	    !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
		timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);

	timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) -
		    arch_timer_read_counter();

	do_div(timeleft, gwdt->clk);

	return timeleft;
}

static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
{
	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);

	/*
	 * Writing WRR for an explicit watchdog refresh.
	 * You can write anyting (like 0).
	 */
	writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);

	return 0;
}

static int sbsa_gwdt_start(struct watchdog_device *wdd)
{
	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);

	/* writing WCS will cause an explicit watchdog refresh */
	writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);

	return 0;
}

static int sbsa_gwdt_stop(struct watchdog_device *wdd)
{
	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);

	/* Simply write 0 to WCS to clean WCS_EN bit */
	writel(0, gwdt->control_base + SBSA_GWDT_WCS);

	return 0;
}

static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
{
	panic(WATCHDOG_NAME " timeout");

	return IRQ_HANDLED;
}

static const struct watchdog_info sbsa_gwdt_info = {
	.identity	= WATCHDOG_NAME,
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE |
			  WDIOF_CARDRESET,
};

static const struct watchdog_ops sbsa_gwdt_ops = {
	.owner		= THIS_MODULE,
	.start		= sbsa_gwdt_start,
	.stop		= sbsa_gwdt_stop,
	.ping		= sbsa_gwdt_keepalive,
	.set_timeout	= sbsa_gwdt_set_timeout,
	.get_timeleft	= sbsa_gwdt_get_timeleft,
};

static int sbsa_gwdt_probe(struct platform_device *pdev)
{
	void __iomem *rf_base, *cf_base;
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct sbsa_gwdt *gwdt;
	int ret, irq;
	u32 status;

	gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
	if (!gwdt)
		return -ENOMEM;
	platform_set_drvdata(pdev, gwdt);

	cf_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(cf_base))
		return PTR_ERR(cf_base);

	rf_base = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(rf_base))
		return PTR_ERR(rf_base);

	/*
	 * Get the frequency of system counter from the cp15 interface of ARM
	 * Generic timer. We don't need to check it, because if it returns "0",
	 * system would panic in very early stage.
	 */
	gwdt->clk = arch_timer_get_cntfrq();
	gwdt->refresh_base = rf_base;
	gwdt->control_base = cf_base;

	wdd = &gwdt->wdd;
	wdd->parent = dev;
	wdd->info = &sbsa_gwdt_info;
	wdd->ops = &sbsa_gwdt_ops;
	wdd->min_timeout = 1;
	wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
	wdd->timeout = DEFAULT_TIMEOUT;
	watchdog_set_drvdata(wdd, gwdt);
	watchdog_set_nowayout(wdd, nowayout);

	status = readl(cf_base + SBSA_GWDT_WCS);
	if (status & SBSA_GWDT_WCS_WS1) {
		dev_warn(dev, "System reset by WDT.\n");
		wdd->bootstatus |= WDIOF_CARDRESET;
	}
	if (status & SBSA_GWDT_WCS_EN)
		set_bit(WDOG_HW_RUNNING, &wdd->status);

	if (action) {
		irq = platform_get_irq(pdev, 0);
		if (irq < 0) {
			action = 0;
			dev_warn(dev, "unable to get ws0 interrupt.\n");
		} else {
			/*
			 * In case there is a pending ws0 interrupt, just ping
			 * the watchdog before registering the interrupt routine
			 */
			writel(0, rf_base + SBSA_GWDT_WRR);
			if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
					     pdev->name, gwdt)) {
				action = 0;
				dev_warn(dev, "unable to request IRQ %d.\n",
					 irq);
			}
		}
		if (!action)
			dev_warn(dev, "falling back to single stage mode.\n");
	}
	/*
	 * In the single stage mode, The first signal (WS0) is ignored,
	 * the timeout is (WOR * 2), so the maximum timeout should be doubled.
	 */
	if (!action)
		wdd->max_hw_heartbeat_ms *= 2;

	watchdog_init_timeout(wdd, timeout, dev);
	/*
	 * Update timeout to WOR.
	 * Because of the explicit watchdog refresh mechanism,
	 * it's also a ping, if watchdog is enabled.
	 */
	sbsa_gwdt_set_timeout(wdd, wdd->timeout);

	watchdog_stop_on_reboot(wdd);
	ret = devm_watchdog_register_device(dev, wdd);
	if (ret)
		return ret;

	dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
		 wdd->timeout, gwdt->clk, action,
		 status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");

	return 0;
}

/* Disable watchdog if it is active during suspend */
static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
{
	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);

	if (watchdog_active(&gwdt->wdd))
		sbsa_gwdt_stop(&gwdt->wdd);

	return 0;
}

/* Enable watchdog if necessary */
static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
{
	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);

	if (watchdog_active(&gwdt->wdd))
		sbsa_gwdt_start(&gwdt->wdd);

	return 0;
}

static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
};

static const struct of_device_id sbsa_gwdt_of_match[] = {
	{ .compatible = "arm,sbsa-gwdt", },
	{},
};
MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);

static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
	{ .name = DRV_NAME, },
	{},
};
MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);

static struct platform_driver sbsa_gwdt_driver = {
	.driver = {
		.name = DRV_NAME,
		.pm = &sbsa_gwdt_pm_ops,
		.of_match_table = sbsa_gwdt_of_match,
	},
	.probe = sbsa_gwdt_probe,
	.id_table = sbsa_gwdt_pdev_match,
};

module_platform_driver(sbsa_gwdt_driver);

MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
57d2caaa FW	1	/*
	2	* SBSA(Server Base System Architecture) Generic Watchdog driver
	3	*
	4	* Copyright (c) 2015, Linaro Ltd.
	5	* Author: Fu Wei <fu.wei@linaro.org>
	6	* Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
	7	* Al Stone <al.stone@linaro.org>
	8	* Timur Tabi <timur@codeaurora.org>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License 2 as published
	12	* by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* ARM SBSA Generic Watchdog has two stage timeouts:
	20	* the first signal (WS0) is for alerting the system by interrupt,
	21	* the second one (WS1) is a real hardware reset.
	22	* More details about the hardware specification of this device:
	23	* ARM DEN0029B - Server Base System Architecture (SBSA)
	24	*
	25	* This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
	26	* or a two stages watchdog, it's set up by the module parameter "action".
	27	* In the single stage mode, when the timeout is reached, your system
	28	* will be reset by WS1. The first signal (WS0) is ignored.
	29	* In the two stages mode, when the timeout is reached, the first signal (WS0)
	30	* will trigger panic. If the system is getting into trouble and cannot be reset
	31	* by panic or restart properly by the kdump kernel(if supported), then the
	32	* second stage (as long as the first stage) will be reached, system will be
	33	* reset by WS1. This function can help administrator to backup the system
	34	* context info by panic console output or kdump.
	35	*
	36	* SBSA GWDT:
	37	* if action is 1 (the two stages mode):
	38	* \|--------WOR-------WS0--------WOR-------WS1
	39	* \|----timeout-----(panic)----timeout-----reset
	40	*
	41	* if action is 0 (the single stage mode):
	42	* \|------WOR-----WS0(ignored)-----WOR------WS1
	43	* \|--------------timeout-------------------reset
	44	*
	45	* Note: Since this watchdog timer has two stages, and each stage is determined
	46	* by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
	47	* stages mode, the timeout is WOR. The maximum timeout in the two stages mode
	48	* is half of that in the single stage mode.
	49	*
	50	*/
	51
	52	#include <linux/io.h>
93ac3deb	53	#include <linux/io-64-nonatomic-lo-hi.h>
57d2caaa FW	54	#include <linux/interrupt.h>
	55	#include <linux/module.h>
	56	#include <linux/moduleparam.h>
	57	#include <linux/of.h>
	58	#include <linux/of_device.h>
	59	#include <linux/platform_device.h>
	60	#include <linux/uaccess.h>
	61	#include <linux/watchdog.h>
	62	#include <asm/arch_timer.h>
	63
	64	#define DRV_NAME "sbsa-gwdt"
	65	#define WATCHDOG_NAME "SBSA Generic Watchdog"
	66
	67	/* SBSA Generic Watchdog register definitions */
	68	/* refresh frame */
	69	#define SBSA_GWDT_WRR 0x000
	70
	71	/* control frame */
	72	#define SBSA_GWDT_WCS 0x000
	73	#define SBSA_GWDT_WOR 0x008
	74	#define SBSA_GWDT_WCV 0x010
	75
	76	/* refresh/control frame */
	77	#define SBSA_GWDT_W_IIDR 0xfcc
	78	#define SBSA_GWDT_IDR 0xfd0
	79
	80	/* Watchdog Control and Status Register */
	81	#define SBSA_GWDT_WCS_EN BIT(0)
	82	#define SBSA_GWDT_WCS_WS0 BIT(1)
	83	#define SBSA_GWDT_WCS_WS1 BIT(2)
	84
	85	/**
	86	* struct sbsa_gwdt - Internal representation of the SBSA GWDT
	87	* @wdd: kernel watchdog_device structure
	88	* @clk: store the System Counter clock frequency, in Hz.
	89	* @refresh_base: Virtual address of the watchdog refresh frame
	90	* @control_base: Virtual address of the watchdog control frame
	91	*/
	92	struct sbsa_gwdt {
	93	struct watchdog_device wdd;
	94	u32 clk;
	95	void __iomem *refresh_base;
	96	void __iomem *control_base;
	97	};
	98
	99	#define DEFAULT_TIMEOUT 10 /* seconds */
	100
	101	static unsigned int timeout;
	102	module_param(timeout, uint, 0);
	103	MODULE_PARM_DESC(timeout,
	104	"Watchdog timeout in seconds. (>=0, default="
	105	__MODULE_STRING(DEFAULT_TIMEOUT) ")");
	106
	107	/*
	108	* action refers to action taken when watchdog gets WS0
	109	* 0 = skip
	110	* 1 = panic
	111	* defaults to skip (0)
	112	*/
	113	static int action;
	114	module_param(action, int, 0);
	115	MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
	116	"0 = skip(*) 1 = panic");
	117
118	static bool nowayout = WATCHDOG_NOWAYOUT;
119	module_param(nowayout, bool, S_IRUGO);
120	MODULE_PARM_DESC(nowayout,
121	"Watchdog cannot be stopped once started (default="
122	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
123
124	/*
125	* watchdog operation functions
126	*/
127	static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
128	unsigned int timeout)
129	{
130	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
131
132	wdd->timeout = timeout;
133
134	if (action)
135	writel(gwdt->clk * timeout,
136	gwdt->control_base + SBSA_GWDT_WOR);
137	else
138	/*
139	* In the single stage mode, The first signal (WS0) is ignored,
140	* the timeout is (WOR * 2), so the WOR should be configured
141	* to half value of timeout.
142	*/
143	writel(gwdt->clk / 2 * timeout,
144	gwdt->control_base + SBSA_GWDT_WOR);
145
146	return 0;
147	}
148
149	static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
150	{
151	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
152	u64 timeleft = 0;
153
154	/*
155	* In the single stage mode, if WS0 is deasserted
156	* (watchdog is in the first stage),
157	* timeleft = WOR + (WCV - system counter)
158	*/
159	if (!action &&
160	!(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
161	timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);
162
93ac3deb	163	timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) -
eae1ddc6	164	arch_timer_read_counter();
57d2caaa FW	165
	166	do_div(timeleft, gwdt->clk);
	167
	168	return timeleft;
	169	}
	170
	171	static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
	172	{
	173	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
	174
	175	/*
	176	* Writing WRR for an explicit watchdog refresh.
	177	* You can write anyting (like 0).
	178	*/
	179	writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);
	180
	181	return 0;
	182	}
	183
57d2caaa FW	184	static int sbsa_gwdt_start(struct watchdog_device *wdd)
	185	{
	186	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
	187
	188	/* writing WCS will cause an explicit watchdog refresh */
	189	writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);
	190
	191	return 0;
	192	}
	193
	194	static int sbsa_gwdt_stop(struct watchdog_device *wdd)
	195	{
	196	struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
	197
	198	/* Simply write 0 to WCS to clean WCS_EN bit */
	199	writel(0, gwdt->control_base + SBSA_GWDT_WCS);
	200
	201	return 0;
	202	}
	203
	204	static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
	205	{
	206	panic(WATCHDOG_NAME " timeout");
	207
	208	return IRQ_HANDLED;
	209	}
	210
6c368932	211	static const struct watchdog_info sbsa_gwdt_info = {
57d2caaa FW	212	.identity = WATCHDOG_NAME,
	213	.options = WDIOF_SETTIMEOUT \|
	214	WDIOF_KEEPALIVEPING \|
	215	WDIOF_MAGICCLOSE \|
	216	WDIOF_CARDRESET,
	217	};
	218
b893e344	219	static const struct watchdog_ops sbsa_gwdt_ops = {
57d2caaa FW	220	.owner = THIS_MODULE,
	221	.start = sbsa_gwdt_start,
	222	.stop = sbsa_gwdt_stop,
57d2caaa FW	223	.ping = sbsa_gwdt_keepalive,
	224	.set_timeout = sbsa_gwdt_set_timeout,
	225	.get_timeleft = sbsa_gwdt_get_timeleft,
	226	};
	227
	228	static int sbsa_gwdt_probe(struct platform_device *pdev)
	229	{
	230	void __iomem rf_base, cf_base;
	231	struct device *dev = &pdev->dev;
	232	struct watchdog_device *wdd;
	233	struct sbsa_gwdt *gwdt;
57d2caaa FW	234	int ret, irq;
	235	u32 status;
	236
	237	gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
	238	if (!gwdt)
	239	return -ENOMEM;
	240	platform_set_drvdata(pdev, gwdt);
	241
0f0a6a28	242	cf_base = devm_platform_ioremap_resource(pdev, 0);
57d2caaa FW	243	if (IS_ERR(cf_base))
	244	return PTR_ERR(cf_base);
	245
0f0a6a28	246	rf_base = devm_platform_ioremap_resource(pdev, 1);
57d2caaa FW	247	if (IS_ERR(rf_base))
	248	return PTR_ERR(rf_base);
	249
	250	/*
	251	* Get the frequency of system counter from the cp15 interface of ARM
	252	* Generic timer. We don't need to check it, because if it returns "0",
	253	* system would panic in very early stage.
	254	*/
	255	gwdt->clk = arch_timer_get_cntfrq();
	256	gwdt->refresh_base = rf_base;
	257	gwdt->control_base = cf_base;
	258
	259	wdd = &gwdt->wdd;
	260	wdd->parent = dev;
	261	wdd->info = &sbsa_gwdt_info;
	262	wdd->ops = &sbsa_gwdt_ops;
	263	wdd->min_timeout = 1;
e05e80eb	264	wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
57d2caaa FW	265	wdd->timeout = DEFAULT_TIMEOUT;
	266	watchdog_set_drvdata(wdd, gwdt);
	267	watchdog_set_nowayout(wdd, nowayout);
	268
	269	status = readl(cf_base + SBSA_GWDT_WCS);
	270	if (status & SBSA_GWDT_WCS_WS1) {
	271	dev_warn(dev, "System reset by WDT.\n");
	272	wdd->bootstatus \|= WDIOF_CARDRESET;
	273	}
c3c1e29c PA	274	if (status & SBSA_GWDT_WCS_EN)
c3c1e29c PA	275	set_bit(WDOG_HW_RUNNING, &wdd->status);
57d2caaa FW	276
	277	if (action) {
	278	irq = platform_get_irq(pdev, 0);
	279	if (irq < 0) {
	280	action = 0;
	281	dev_warn(dev, "unable to get ws0 interrupt.\n");
	282	} else {
	283	/*
	284	* In case there is a pending ws0 interrupt, just ping
	285	* the watchdog before registering the interrupt routine
	286	*/
	287	writel(0, rf_base + SBSA_GWDT_WRR);
	288	if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
	289	pdev->name, gwdt)) {
	290	action = 0;
	291	dev_warn(dev, "unable to request IRQ %d.\n",
	292	irq);
	293	}
	294	}
	295	if (!action)
	296	dev_warn(dev, "falling back to single stage mode.\n");
	297	}
	298	/*
	299	* In the single stage mode, The first signal (WS0) is ignored,
	300	* the timeout is (WOR * 2), so the maximum timeout should be doubled.
	301	*/
	302	if (!action)
e05e80eb	303	wdd->max_hw_heartbeat_ms *= 2;
57d2caaa FW	304
	305	watchdog_init_timeout(wdd, timeout, dev);
	306	/*
	307	* Update timeout to WOR.
	308	* Because of the explicit watchdog refresh mechanism,
	309	* it's also a ping, if watchdog is enabled.
	310	*/
	311	sbsa_gwdt_set_timeout(wdd, wdd->timeout);
	312
f7daaa8d GR	313	watchdog_stop_on_reboot(wdd);
f7daaa8d GR	314	ret = devm_watchdog_register_device(dev, wdd);
57d2caaa FW	315	if (ret)
	316	return ret;
	317
	318	dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
	319	wdd->timeout, gwdt->clk, action,
	320	status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");
	321
	322	return 0;
	323	}
	324
57d2caaa FW	325	/* Disable watchdog if it is active during suspend */
	326	static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
	327	{
	328	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
	329
	330	if (watchdog_active(&gwdt->wdd))
	331	sbsa_gwdt_stop(&gwdt->wdd);
	332
	333	return 0;
	334	}
	335
	336	/* Enable watchdog if necessary */
	337	static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
	338	{
	339	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
	340
	341	if (watchdog_active(&gwdt->wdd))
	342	sbsa_gwdt_start(&gwdt->wdd);
	343
	344	return 0;
	345	}
	346
	347	static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
	348	SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
	349	};
	350
	351	static const struct of_device_id sbsa_gwdt_of_match[] = {
	352	{ .compatible = "arm,sbsa-gwdt", },
	353	{},
	354	};
	355	MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
	356
	357	static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
	358	{ .name = DRV_NAME, },
	359	{},
	360	};
	361	MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
	362
	363	static struct platform_driver sbsa_gwdt_driver = {
	364	.driver = {
	365	.name = DRV_NAME,
	366	.pm = &sbsa_gwdt_pm_ops,
	367	.of_match_table = sbsa_gwdt_of_match,
	368	},
	369	.probe = sbsa_gwdt_probe,
57d2caaa FW	370	.id_table = sbsa_gwdt_pdev_match,
	371	};
	372
	373	module_platform_driver(sbsa_gwdt_driver);
	374
	375	MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
	376	MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
	377	MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
	378	MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
	379	MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
	380	MODULE_LICENSE("GPL v2");
	381	MODULE_ALIAS("platform:" DRV_NAME);