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Commit | Line | Data |
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1da177e4 | 1 | /* |
b1fa888e | 2 | * drivers/watchdog/shwdt.c |
1da177e4 LT |
3 | * |
4 | * Watchdog driver for integrated watchdog in the SuperH processors. | |
5 | * | |
40968126 | 6 | * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org> |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com> | |
14 | * Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT | |
15 | * | |
16 | * 19-Apr-2002 Rob Radez <rob@osinvestor.com> | |
17 | * Added expect close support, made emulated timeout runtime changeable | |
18 | * general cleanups, add some ioctls | |
19 | */ | |
27c766aa JP |
20 | |
21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/moduleparam.h> | |
8f5585ec | 25 | #include <linux/platform_device.h> |
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/types.h> | |
f9fb360c | 28 | #include <linux/spinlock.h> |
1da177e4 | 29 | #include <linux/watchdog.h> |
8c013d96 | 30 | #include <linux/pm_runtime.h> |
1da177e4 | 31 | #include <linux/fs.h> |
f118420b | 32 | #include <linux/mm.h> |
8f5585ec | 33 | #include <linux/slab.h> |
70b814ec | 34 | #include <linux/io.h> |
9ea64046 | 35 | #include <linux/clk.h> |
6330c707 | 36 | #include <linux/err.h> |
58cf4198 | 37 | #include <asm/watchdog.h> |
1da177e4 | 38 | |
8f5585ec | 39 | #define DRV_NAME "sh-wdt" |
1da177e4 LT |
40 | |
41 | /* | |
42 | * Default clock division ratio is 5.25 msecs. For an additional table of | |
43 | * values, consult the asm-sh/watchdog.h. Overload this at module load | |
44 | * time. | |
45 | * | |
46 | * In order for this to work reliably we need to have HZ set to 1000 or | |
47 | * something quite higher than 100 (or we need a proper high-res timer | |
48 | * implementation that will deal with this properly), otherwise the 10ms | |
49 | * resolution of a jiffy is enough to trigger the overflow. For things like | |
50 | * the SH-4 and SH-5, this isn't necessarily that big of a problem, though | |
51 | * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely | |
52 | * necssary. | |
53 | * | |
54 | * As a result of this timing problem, the only modes that are particularly | |
25985edc | 55 | * feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms |
1da177e4 LT |
56 | * overflow periods respectively. |
57 | * | |
58 | * Also, since we can't really expect userspace to be responsive enough | |
ee0fc097 | 59 | * before the overflow happens, we maintain two separate timers .. One in |
1da177e4 LT |
60 | * the kernel for clearing out WOVF every 2ms or so (again, this depends on |
61 | * HZ == 1000), and another for monitoring userspace writes to the WDT device. | |
62 | * | |
63 | * As such, we currently use a configurable heartbeat interval which defaults | |
64 | * to 30s. In this case, the userspace daemon is only responsible for periodic | |
65 | * writes to the device before the next heartbeat is scheduled. If the daemon | |
66 | * misses its deadline, the kernel timer will allow the WDT to overflow. | |
67 | */ | |
68 | static int clock_division_ratio = WTCSR_CKS_4096; | |
bea19066 | 69 | #define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4)) |
1da177e4 | 70 | |
1da177e4 LT |
71 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ |
72 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ | |
86a1e189 | 73 | static bool nowayout = WATCHDOG_NOWAYOUT; |
8f5585ec PM |
74 | static unsigned long next_heartbeat; |
75 | ||
76 | struct sh_wdt { | |
77 | void __iomem *base; | |
78 | struct device *dev; | |
9ea64046 | 79 | struct clk *clk; |
f9fb360c | 80 | spinlock_t lock; |
1da177e4 | 81 | |
8f5585ec | 82 | struct timer_list timer; |
8f5585ec PM |
83 | }; |
84 | ||
1950f499 | 85 | static int sh_wdt_start(struct watchdog_device *wdt_dev) |
1da177e4 | 86 | { |
1950f499 | 87 | struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); |
70b814ec | 88 | unsigned long flags; |
8f5585ec | 89 | u8 csr; |
70b814ec | 90 | |
8c013d96 | 91 | pm_runtime_get_sync(wdt->dev); |
d42c9744 | 92 | clk_enable(wdt->clk); |
8c013d96 | 93 | |
f9fb360c | 94 | spin_lock_irqsave(&wdt->lock, flags); |
1da177e4 LT |
95 | |
96 | next_heartbeat = jiffies + (heartbeat * HZ); | |
8f5585ec | 97 | mod_timer(&wdt->timer, next_ping_period(clock_division_ratio)); |
1da177e4 LT |
98 | |
99 | csr = sh_wdt_read_csr(); | |
100 | csr |= WTCSR_WT | clock_division_ratio; | |
101 | sh_wdt_write_csr(csr); | |
102 | ||
103 | sh_wdt_write_cnt(0); | |
104 | ||
105 | /* | |
106 | * These processors have a bit of an inconsistent initialization | |
107 | * process.. starting with SH-3, RSTS was moved to WTCSR, and the | |
108 | * RSTCSR register was removed. | |
109 | * | |
110 | * On the SH-2 however, in addition with bits being in different | |
111 | * locations, we must deal with RSTCSR outright.. | |
112 | */ | |
113 | csr = sh_wdt_read_csr(); | |
114 | csr |= WTCSR_TME; | |
115 | csr &= ~WTCSR_RSTS; | |
116 | sh_wdt_write_csr(csr); | |
117 | ||
118 | #ifdef CONFIG_CPU_SH2 | |
1da177e4 LT |
119 | csr = sh_wdt_read_rstcsr(); |
120 | csr &= ~RSTCSR_RSTS; | |
121 | sh_wdt_write_rstcsr(csr); | |
122 | #endif | |
f9fb360c | 123 | spin_unlock_irqrestore(&wdt->lock, flags); |
1950f499 PM |
124 | |
125 | return 0; | |
1da177e4 LT |
126 | } |
127 | ||
1950f499 | 128 | static int sh_wdt_stop(struct watchdog_device *wdt_dev) |
1da177e4 | 129 | { |
1950f499 | 130 | struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); |
70b814ec | 131 | unsigned long flags; |
8f5585ec | 132 | u8 csr; |
70b814ec | 133 | |
f9fb360c | 134 | spin_lock_irqsave(&wdt->lock, flags); |
1da177e4 | 135 | |
8f5585ec | 136 | del_timer(&wdt->timer); |
1da177e4 LT |
137 | |
138 | csr = sh_wdt_read_csr(); | |
139 | csr &= ~WTCSR_TME; | |
140 | sh_wdt_write_csr(csr); | |
8f5585ec | 141 | |
f9fb360c | 142 | spin_unlock_irqrestore(&wdt->lock, flags); |
1950f499 | 143 | |
d42c9744 | 144 | clk_disable(wdt->clk); |
8c013d96 PM |
145 | pm_runtime_put_sync(wdt->dev); |
146 | ||
1950f499 | 147 | return 0; |
1da177e4 LT |
148 | } |
149 | ||
1950f499 | 150 | static int sh_wdt_keepalive(struct watchdog_device *wdt_dev) |
1da177e4 | 151 | { |
f9fb360c | 152 | struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); |
70b814ec AC |
153 | unsigned long flags; |
154 | ||
f9fb360c | 155 | spin_lock_irqsave(&wdt->lock, flags); |
1da177e4 | 156 | next_heartbeat = jiffies + (heartbeat * HZ); |
f9fb360c | 157 | spin_unlock_irqrestore(&wdt->lock, flags); |
1950f499 PM |
158 | |
159 | return 0; | |
1da177e4 LT |
160 | } |
161 | ||
1950f499 | 162 | static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t) |
1da177e4 | 163 | { |
f9fb360c | 164 | struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); |
70b814ec AC |
165 | unsigned long flags; |
166 | ||
167 | if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */ | |
1da177e4 LT |
168 | return -EINVAL; |
169 | ||
f9fb360c | 170 | spin_lock_irqsave(&wdt->lock, flags); |
1da177e4 | 171 | heartbeat = t; |
1950f499 | 172 | wdt_dev->timeout = t; |
f9fb360c | 173 | spin_unlock_irqrestore(&wdt->lock, flags); |
1950f499 | 174 | |
1da177e4 LT |
175 | return 0; |
176 | } | |
177 | ||
e99e88a9 | 178 | static void sh_wdt_ping(struct timer_list *t) |
1da177e4 | 179 | { |
e99e88a9 | 180 | struct sh_wdt *wdt = from_timer(wdt, t, timer); |
70b814ec AC |
181 | unsigned long flags; |
182 | ||
f9fb360c | 183 | spin_lock_irqsave(&wdt->lock, flags); |
1da177e4 | 184 | if (time_before(jiffies, next_heartbeat)) { |
8f5585ec | 185 | u8 csr; |
1da177e4 LT |
186 | |
187 | csr = sh_wdt_read_csr(); | |
188 | csr &= ~WTCSR_IOVF; | |
189 | sh_wdt_write_csr(csr); | |
190 | ||
191 | sh_wdt_write_cnt(0); | |
192 | ||
8f5585ec | 193 | mod_timer(&wdt->timer, next_ping_period(clock_division_ratio)); |
e4c2cfee | 194 | } else |
8f5585ec PM |
195 | dev_warn(wdt->dev, "Heartbeat lost! Will not ping " |
196 | "the watchdog\n"); | |
f9fb360c | 197 | spin_unlock_irqrestore(&wdt->lock, flags); |
1da177e4 LT |
198 | } |
199 | ||
70b814ec | 200 | static const struct watchdog_info sh_wdt_info = { |
e4c2cfee PM |
201 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
202 | WDIOF_MAGICCLOSE, | |
1da177e4 LT |
203 | .firmware_version = 1, |
204 | .identity = "SH WDT", | |
205 | }; | |
206 | ||
1950f499 PM |
207 | static const struct watchdog_ops sh_wdt_ops = { |
208 | .owner = THIS_MODULE, | |
209 | .start = sh_wdt_start, | |
210 | .stop = sh_wdt_stop, | |
211 | .ping = sh_wdt_keepalive, | |
212 | .set_timeout = sh_wdt_set_heartbeat, | |
213 | }; | |
214 | ||
215 | static struct watchdog_device sh_wdt_dev = { | |
216 | .info = &sh_wdt_info, | |
217 | .ops = &sh_wdt_ops, | |
1da177e4 LT |
218 | }; |
219 | ||
2d991a16 | 220 | static int sh_wdt_probe(struct platform_device *pdev) |
1da177e4 | 221 | { |
8f5585ec | 222 | struct sh_wdt *wdt; |
1da177e4 LT |
223 | int rc; |
224 | ||
8f5585ec PM |
225 | /* |
226 | * As this driver only covers the global watchdog case, reject | |
227 | * any attempts to register per-CPU watchdogs. | |
228 | */ | |
229 | if (pdev->id != -1) | |
230 | return -EINVAL; | |
231 | ||
8f5585ec | 232 | wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL); |
9ea64046 PM |
233 | if (unlikely(!wdt)) |
234 | return -ENOMEM; | |
1da177e4 | 235 | |
8f5585ec PM |
236 | wdt->dev = &pdev->dev; |
237 | ||
2f7b9b48 | 238 | wdt->clk = devm_clk_get(&pdev->dev, NULL); |
9ea64046 PM |
239 | if (IS_ERR(wdt->clk)) { |
240 | /* | |
241 | * Clock framework support is optional, continue on | |
242 | * anyways if we don't find a matching clock. | |
243 | */ | |
244 | wdt->clk = NULL; | |
245 | } | |
f9fb360c | 246 | |
0f0a6a28 | 247 | wdt->base = devm_platform_ioremap_resource(pdev, 0); |
2f7b9b48 JH |
248 | if (IS_ERR(wdt->base)) |
249 | return PTR_ERR(wdt->base); | |
1da177e4 | 250 | |
9ea64046 PM |
251 | watchdog_set_nowayout(&sh_wdt_dev, nowayout); |
252 | watchdog_set_drvdata(&sh_wdt_dev, wdt); | |
6551881c | 253 | sh_wdt_dev.parent = &pdev->dev; |
9ea64046 | 254 | |
f9fb360c PM |
255 | spin_lock_init(&wdt->lock); |
256 | ||
1950f499 PM |
257 | rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat); |
258 | if (unlikely(rc)) { | |
259 | /* Default timeout if invalid */ | |
260 | sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT); | |
261 | ||
262 | dev_warn(&pdev->dev, | |
263 | "heartbeat value must be 1<=x<=3600, using %d\n", | |
264 | sh_wdt_dev.timeout); | |
265 | } | |
266 | ||
267 | dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n", | |
268 | sh_wdt_dev.timeout, nowayout); | |
8f5585ec | 269 | |
1950f499 | 270 | rc = watchdog_register_device(&sh_wdt_dev); |
e4c2cfee | 271 | if (unlikely(rc)) { |
1950f499 | 272 | dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc); |
2f7b9b48 | 273 | return rc; |
1da177e4 LT |
274 | } |
275 | ||
e99e88a9 | 276 | timer_setup(&wdt->timer, sh_wdt_ping, 0); |
8f5585ec PM |
277 | wdt->timer.expires = next_ping_period(clock_division_ratio); |
278 | ||
8f5585ec | 279 | dev_info(&pdev->dev, "initialized.\n"); |
1da177e4 | 280 | |
8c013d96 PM |
281 | pm_runtime_enable(&pdev->dev); |
282 | ||
1da177e4 LT |
283 | return 0; |
284 | } | |
285 | ||
4b12b896 | 286 | static int sh_wdt_remove(struct platform_device *pdev) |
1da177e4 | 287 | { |
1950f499 | 288 | watchdog_unregister_device(&sh_wdt_dev); |
8f5585ec | 289 | |
8c013d96 | 290 | pm_runtime_disable(&pdev->dev); |
8f5585ec PM |
291 | |
292 | return 0; | |
293 | } | |
294 | ||
40968126 PM |
295 | static void sh_wdt_shutdown(struct platform_device *pdev) |
296 | { | |
1950f499 | 297 | sh_wdt_stop(&sh_wdt_dev); |
40968126 PM |
298 | } |
299 | ||
8f5585ec PM |
300 | static struct platform_driver sh_wdt_driver = { |
301 | .driver = { | |
302 | .name = DRV_NAME, | |
8f5585ec PM |
303 | }, |
304 | ||
40968126 | 305 | .probe = sh_wdt_probe, |
82268714 | 306 | .remove = sh_wdt_remove, |
40968126 | 307 | .shutdown = sh_wdt_shutdown, |
8f5585ec PM |
308 | }; |
309 | ||
310 | static int __init sh_wdt_init(void) | |
311 | { | |
8f5585ec PM |
312 | if (unlikely(clock_division_ratio < 0x5 || |
313 | clock_division_ratio > 0x7)) { | |
314 | clock_division_ratio = WTCSR_CKS_4096; | |
315 | ||
27c766aa JP |
316 | pr_info("divisor must be 0x5<=x<=0x7, using %d\n", |
317 | clock_division_ratio); | |
8f5585ec PM |
318 | } |
319 | ||
8f5585ec | 320 | return platform_driver_register(&sh_wdt_driver); |
1da177e4 LT |
321 | } |
322 | ||
8f5585ec PM |
323 | static void __exit sh_wdt_exit(void) |
324 | { | |
325 | platform_driver_unregister(&sh_wdt_driver); | |
326 | } | |
327 | module_init(sh_wdt_init); | |
328 | module_exit(sh_wdt_exit); | |
329 | ||
1da177e4 LT |
330 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>"); |
331 | MODULE_DESCRIPTION("SuperH watchdog driver"); | |
332 | MODULE_LICENSE("GPL"); | |
8f5585ec | 333 | MODULE_ALIAS("platform:" DRV_NAME); |
1da177e4 LT |
334 | |
335 | module_param(clock_division_ratio, int, 0); | |
a77dba7e WVS |
336 | MODULE_PARM_DESC(clock_division_ratio, |
337 | "Clock division ratio. Valid ranges are from 0x5 (1.31ms) " | |
76550d32 | 338 | "to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")"); |
1da177e4 LT |
339 | |
340 | module_param(heartbeat, int, 0); | |
70b814ec AC |
341 | MODULE_PARM_DESC(heartbeat, |
342 | "Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default=" | |
343 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | |
1da177e4 | 344 | |
86a1e189 | 345 | module_param(nowayout, bool, 0); |
70b814ec AC |
346 | MODULE_PARM_DESC(nowayout, |
347 | "Watchdog cannot be stopped once started (default=" | |
348 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |