[mirror_ubuntu-focal-kernel.git] / drivers / watchdog / sirfsoc_wdt.c

/*
 * Watchdog driver for CSR SiRFprimaII and SiRFatlasVI
 *
 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/io.h>
#include <linux/uaccess.h>

#define CLOCK_FREQ	1000000

#define SIRFSOC_TIMER_COUNTER_LO	0x0000
#define SIRFSOC_TIMER_MATCH_0		0x0008
#define SIRFSOC_TIMER_INT_EN		0x0024
#define SIRFSOC_TIMER_WATCHDOG_EN	0x0028
#define SIRFSOC_TIMER_LATCH		0x0030
#define SIRFSOC_TIMER_LATCHED_LO	0x0034

#define SIRFSOC_TIMER_WDT_INDEX		5

#define SIRFSOC_WDT_MIN_TIMEOUT		30		/* 30 secs */
#define SIRFSOC_WDT_MAX_TIMEOUT		(10 * 60)	/* 10 mins */
#define SIRFSOC_WDT_DEFAULT_TIMEOUT	30		/* 30 secs */

static unsigned int timeout;
static bool nowayout = WATCHDOG_NOWAYOUT;

module_param(timeout, uint, 0);
module_param(nowayout, bool, 0);

MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)");
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
			__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static void __iomem *sirfsoc_wdt_base(struct watchdog_device *wdd)
{
	return (void __iomem __force *)watchdog_get_drvdata(wdd);
}

static unsigned int sirfsoc_wdt_gettimeleft(struct watchdog_device *wdd)
{
	u32 counter, match;
	void __iomem *wdt_base;
	int time_left;

	wdt_base = sirfsoc_wdt_base(wdd);
	counter = readl(wdt_base + SIRFSOC_TIMER_COUNTER_LO);
	match = readl(wdt_base +
		SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));

	time_left = match - counter;

	return time_left / CLOCK_FREQ;
}

static int sirfsoc_wdt_updatetimeout(struct watchdog_device *wdd)
{
	u32 counter, timeout_ticks;
	void __iomem *wdt_base;

	timeout_ticks = wdd->timeout * CLOCK_FREQ;
	wdt_base = sirfsoc_wdt_base(wdd);

	/* Enable the latch before reading the LATCH_LO register */
	writel(1, wdt_base + SIRFSOC_TIMER_LATCH);

	/* Set the TO value */
	counter = readl(wdt_base + SIRFSOC_TIMER_LATCHED_LO);

	counter += timeout_ticks;

	writel(counter, wdt_base +
		SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));

	return 0;
}

static int sirfsoc_wdt_enable(struct watchdog_device *wdd)
{
	void __iomem *wdt_base = sirfsoc_wdt_base(wdd);
	sirfsoc_wdt_updatetimeout(wdd);

	/*
	 * NOTE: If interrupt is not enabled
	 * then WD-Reset doesn't get generated at all.
	 */
	writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
		| (1 << SIRFSOC_TIMER_WDT_INDEX),
		wdt_base + SIRFSOC_TIMER_INT_EN);
	writel(1, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);

	return 0;
}

static int sirfsoc_wdt_disable(struct watchdog_device *wdd)
{
	void __iomem *wdt_base = sirfsoc_wdt_base(wdd);

	writel(0, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
	writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
		& (~(1 << SIRFSOC_TIMER_WDT_INDEX)),
		wdt_base + SIRFSOC_TIMER_INT_EN);

	return 0;
}

static int sirfsoc_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
{
	wdd->timeout = to;
	sirfsoc_wdt_updatetimeout(wdd);

	return 0;
}

#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)

static const struct watchdog_info sirfsoc_wdt_ident = {
	.options          =     OPTIONS,
	.firmware_version =	0,
	.identity         =	"SiRFSOC Watchdog",
};

static const struct watchdog_ops sirfsoc_wdt_ops = {
	.owner = THIS_MODULE,
	.start = sirfsoc_wdt_enable,
	.stop = sirfsoc_wdt_disable,
	.get_timeleft = sirfsoc_wdt_gettimeleft,
	.ping = sirfsoc_wdt_updatetimeout,
	.set_timeout = sirfsoc_wdt_settimeout,
};

static struct watchdog_device sirfsoc_wdd = {
	.info = &sirfsoc_wdt_ident,
	.ops = &sirfsoc_wdt_ops,
	.timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT,
	.min_timeout = SIRFSOC_WDT_MIN_TIMEOUT,
	.max_timeout = SIRFSOC_WDT_MAX_TIMEOUT,
};

static int sirfsoc_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;
	void __iomem *base;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	watchdog_set_drvdata(&sirfsoc_wdd, (__force void *)base);

	watchdog_init_timeout(&sirfsoc_wdd, timeout, dev);
	watchdog_set_nowayout(&sirfsoc_wdd, nowayout);
	sirfsoc_wdd.parent = dev;

	watchdog_stop_on_reboot(&sirfsoc_wdd);
	watchdog_stop_on_unregister(&sirfsoc_wdd);
	ret = devm_watchdog_register_device(dev, &sirfsoc_wdd);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, &sirfsoc_wdd);

	return 0;
}

#ifdef	CONFIG_PM_SLEEP
static int sirfsoc_wdt_suspend(struct device *dev)
{
	return 0;
}

static int sirfsoc_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdd = dev_get_drvdata(dev);

	/*
	 * NOTE: Since timer controller registers settings are saved
	 * and restored back by the timer-prima2.c, so we need not
	 * update WD settings except refreshing timeout.
	 */
	sirfsoc_wdt_updatetimeout(wdd);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(sirfsoc_wdt_pm_ops,
		sirfsoc_wdt_suspend, sirfsoc_wdt_resume);

static const struct of_device_id sirfsoc_wdt_of_match[] = {
	{ .compatible = "sirf,prima2-tick"},
	{},
};
MODULE_DEVICE_TABLE(of, sirfsoc_wdt_of_match);

static struct platform_driver sirfsoc_wdt_driver = {
	.driver = {
		.name = "sirfsoc-wdt",
		.pm = &sirfsoc_wdt_pm_ops,
		.of_match_table	= sirfsoc_wdt_of_match,
	},
	.probe = sirfsoc_wdt_probe,
};
module_platform_driver(sirfsoc_wdt_driver);

MODULE_DESCRIPTION("SiRF SoC watchdog driver");
MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:sirfsoc-wdt");
Commit	Line	Data
f0fcbdbf XD	1	/*
	2	* Watchdog driver for CSR SiRFprimaII and SiRFatlasVI
	3	*
	4	* Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/watchdog.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/moduleparam.h>
	13	#include <linux/of.h>
	14	#include <linux/io.h>
	15	#include <linux/uaccess.h>
	16
b0df38dd UKK	17	#define CLOCK_FREQ 1000000
b0df38dd UKK	18
f0fcbdbf XD	19	#define SIRFSOC_TIMER_COUNTER_LO 0x0000
	20	#define SIRFSOC_TIMER_MATCH_0 0x0008
	21	#define SIRFSOC_TIMER_INT_EN 0x0024
	22	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
	23	#define SIRFSOC_TIMER_LATCH 0x0030
	24	#define SIRFSOC_TIMER_LATCHED_LO 0x0034
	25
	26	#define SIRFSOC_TIMER_WDT_INDEX 5
	27
	28	#define SIRFSOC_WDT_MIN_TIMEOUT 30 /* 30 secs */
	29	#define SIRFSOC_WDT_MAX_TIMEOUT (10 * 60) /* 10 mins */
	30	#define SIRFSOC_WDT_DEFAULT_TIMEOUT 30 /* 30 secs */
	31
f70b1454	32	static unsigned int timeout;
f0fcbdbf XD	33	static bool nowayout = WATCHDOG_NOWAYOUT;
	34
	35	module_param(timeout, uint, 0);
	36	module_param(nowayout, bool, 0);
	37
	38	MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)");
	39	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	40	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	41
b99c8774 BD	42	static void __iomem sirfsoc_wdt_base(struct watchdog_device wdd)
	43	{
	44	return (void __iomem __force *)watchdog_get_drvdata(wdd);
	45	}
	46
f0fcbdbf XD	47	static unsigned int sirfsoc_wdt_gettimeleft(struct watchdog_device *wdd)
	48	{
	49	u32 counter, match;
	50	void __iomem *wdt_base;
	51	int time_left;
	52
b99c8774	53	wdt_base = sirfsoc_wdt_base(wdd);
f0fcbdbf XD	54	counter = readl(wdt_base + SIRFSOC_TIMER_COUNTER_LO);
	55	match = readl(wdt_base +
	56	SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
	57
	58	time_left = match - counter;
	59
b0df38dd	60	return time_left / CLOCK_FREQ;
f0fcbdbf XD	61	}
	62
	63	static int sirfsoc_wdt_updatetimeout(struct watchdog_device *wdd)
	64	{
	65	u32 counter, timeout_ticks;
	66	void __iomem *wdt_base;
	67
b0df38dd	68	timeout_ticks = wdd->timeout * CLOCK_FREQ;
b99c8774	69	wdt_base = sirfsoc_wdt_base(wdd);
f0fcbdbf XD	70
	71	/* Enable the latch before reading the LATCH_LO register */
	72	writel(1, wdt_base + SIRFSOC_TIMER_LATCH);
	73
	74	/* Set the TO value */
	75	counter = readl(wdt_base + SIRFSOC_TIMER_LATCHED_LO);
	76
	77	counter += timeout_ticks;
	78
	79	writel(counter, wdt_base +
	80	SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
	81
	82	return 0;
	83	}
	84
	85	static int sirfsoc_wdt_enable(struct watchdog_device *wdd)
	86	{
b99c8774	87	void __iomem *wdt_base = sirfsoc_wdt_base(wdd);
f0fcbdbf XD	88	sirfsoc_wdt_updatetimeout(wdd);
	89
	90	/*
	91	* NOTE: If interrupt is not enabled
	92	* then WD-Reset doesn't get generated at all.
	93	*/
	94	writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
	95	\| (1 << SIRFSOC_TIMER_WDT_INDEX),
	96	wdt_base + SIRFSOC_TIMER_INT_EN);
	97	writel(1, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
	98
	99	return 0;
	100	}
	101
	102	static int sirfsoc_wdt_disable(struct watchdog_device *wdd)
	103	{
b99c8774	104	void __iomem *wdt_base = sirfsoc_wdt_base(wdd);
f0fcbdbf XD	105
	106	writel(0, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
	107	writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
	108	& (~(1 << SIRFSOC_TIMER_WDT_INDEX)),
	109	wdt_base + SIRFSOC_TIMER_INT_EN);
	110
	111	return 0;
	112	}
	113
	114	static int sirfsoc_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
	115	{
	116	wdd->timeout = to;
	117	sirfsoc_wdt_updatetimeout(wdd);
	118
	119	return 0;
	120	}
	121
	122	#define OPTIONS (WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE)
	123
	124	static const struct watchdog_info sirfsoc_wdt_ident = {
	125	.options = OPTIONS,
	126	.firmware_version = 0,
	127	.identity = "SiRFSOC Watchdog",
	128	};
	129
b893e344	130	static const struct watchdog_ops sirfsoc_wdt_ops = {
f0fcbdbf XD	131	.owner = THIS_MODULE,
	132	.start = sirfsoc_wdt_enable,
	133	.stop = sirfsoc_wdt_disable,
	134	.get_timeleft = sirfsoc_wdt_gettimeleft,
	135	.ping = sirfsoc_wdt_updatetimeout,
	136	.set_timeout = sirfsoc_wdt_settimeout,
	137	};
	138
	139	static struct watchdog_device sirfsoc_wdd = {
	140	.info = &sirfsoc_wdt_ident,
	141	.ops = &sirfsoc_wdt_ops,
	142	.timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT,
	143	.min_timeout = SIRFSOC_WDT_MIN_TIMEOUT,
	144	.max_timeout = SIRFSOC_WDT_MAX_TIMEOUT,
	145	};
	146
	147	static int sirfsoc_wdt_probe(struct platform_device *pdev)
	148	{
72dbc27c	149	struct device *dev = &pdev->dev;
f0fcbdbf XD	150	int ret;
	151	void __iomem *base;
	152
0f0a6a28	153	base = devm_platform_ioremap_resource(pdev, 0);
f0fcbdbf XD	154	if (IS_ERR(base))
	155	return PTR_ERR(base);
	156
b99c8774	157	watchdog_set_drvdata(&sirfsoc_wdd, (__force void *)base);
f0fcbdbf	158
72dbc27c	159	watchdog_init_timeout(&sirfsoc_wdd, timeout, dev);
f0fcbdbf	160	watchdog_set_nowayout(&sirfsoc_wdd, nowayout);
72dbc27c	161	sirfsoc_wdd.parent = dev;
f0fcbdbf	162
72dbc27c GR	163	watchdog_stop_on_reboot(&sirfsoc_wdd);
	164	watchdog_stop_on_unregister(&sirfsoc_wdd);
	165	ret = devm_watchdog_register_device(dev, &sirfsoc_wdd);
f0fcbdbf XD	166	if (ret)
	167	return ret;
	168
	169	platform_set_drvdata(pdev, &sirfsoc_wdd);
	170
	171	return 0;
	172	}
	173
f0fcbdbf XD	174	#ifdef CONFIG_PM_SLEEP
	175	static int sirfsoc_wdt_suspend(struct device *dev)
	176	{
	177	return 0;
	178	}
	179
	180	static int sirfsoc_wdt_resume(struct device *dev)
	181	{
	182	struct watchdog_device *wdd = dev_get_drvdata(dev);
	183
	184	/*
	185	* NOTE: Since timer controller registers settings are saved
	186	* and restored back by the timer-prima2.c, so we need not
	187	* update WD settings except refreshing timeout.
	188	*/
	189	sirfsoc_wdt_updatetimeout(wdd);
	190
	191	return 0;
	192	}
	193	#endif
	194
	195	static SIMPLE_DEV_PM_OPS(sirfsoc_wdt_pm_ops,
	196	sirfsoc_wdt_suspend, sirfsoc_wdt_resume);
	197
	198	static const struct of_device_id sirfsoc_wdt_of_match[] = {
	199	{ .compatible = "sirf,prima2-tick"},
	200	{},
	201	};
	202	MODULE_DEVICE_TABLE(of, sirfsoc_wdt_of_match);
	203
	204	static struct platform_driver sirfsoc_wdt_driver = {
	205	.driver = {
	206	.name = "sirfsoc-wdt",
f0fcbdbf	207	.pm = &sirfsoc_wdt_pm_ops,
15edd9ee	208	.of_match_table = sirfsoc_wdt_of_match,
f0fcbdbf XD	209	},
f0fcbdbf XD	210	.probe = sirfsoc_wdt_probe,
f0fcbdbf XD	211	};
	212	module_platform_driver(sirfsoc_wdt_driver);
	213
	214	MODULE_DESCRIPTION("SiRF SoC watchdog driver");
	215	MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
	216	MODULE_LICENSE("GPL v2");
	217	MODULE_ALIAS("platform:sirfsoc-wdt");