[mirror_ubuntu-eoan-kernel.git] / drivers / watchdog / sp5100_tco.c

/*
 *	sp5100_tco :	TCO timer driver for sp5100 chipsets
 *
 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
 *
 *	Based on i8xx_tco.c:
 *	(c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
 *	Reserved.
 *				http://www.kernelconcepts.de
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
 *	    AMD Publication 45482 "AMD SB800-Series Southbridges Register
 *	                                                      Reference Guide"
 *	    AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
 *				for AMD Family 16h Models 00h-0Fh Processors"
 *	    AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
 *	    AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
 *				for AMD Family 16h Models 30h-3Fh Processors"
 */

/*
 *	Includes, defines, variables, module parameters, ...
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>

#include "sp5100_tco.h"

#define TCO_DRIVER_NAME	"sp5100-tco"

/* internal variables */

enum tco_reg_layout {
	sp5100, sb800, efch
};

struct sp5100_tco {
	struct watchdog_device wdd;
	void __iomem *tcobase;
	enum tco_reg_layout tco_reg_layout;
};

/* the watchdog platform device */
static struct platform_device *sp5100_tco_platform_device;
/* the associated PCI device */
static struct pci_dev *sp5100_tco_pci;

/* module parameters */

#define WATCHDOG_HEARTBEAT 60	/* 60 sec default heartbeat. */
static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
		 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
		" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/*
 * Some TCO specific functions
 */

static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
{
	if (dev->vendor == PCI_VENDOR_ID_ATI &&
	    dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	    dev->revision < 0x40) {
		return sp5100;
	} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
	     dev->revision >= 0x41) ||
	    (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	     dev->revision >= 0x49))) {
		return efch;
	}
	return sb800;
}

static int tco_timer_start(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val |= SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_stop(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val &= ~SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_ping(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val |= SP5100_WDT_TRIGGER_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_set_timeout(struct watchdog_device *wdd,
				 unsigned int t)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);

	/* Write new heartbeat to watchdog */
	writel(t, SP5100_WDT_COUNT(tco->tcobase));

	wdd->timeout = t;

	return 0;
}

static u8 sp5100_tco_read_pm_reg8(u8 index)
{
	outb(index, SP5100_IO_PM_INDEX_REG);
	return inb(SP5100_IO_PM_DATA_REG);
}

static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
{
	u8 val;

	outb(index, SP5100_IO_PM_INDEX_REG);
	val = inb(SP5100_IO_PM_DATA_REG);
	val &= reset;
	val |= set;
	outb(val, SP5100_IO_PM_DATA_REG);
}

static void tco_timer_enable(struct sp5100_tco *tco)
{
	u32 val;

	switch (tco->tco_reg_layout) {
	case sb800:
		/* For SB800 or later */
		/* Set the Watchdog timer resolution to 1 sec */
		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
					  0xff, SB800_PM_WATCHDOG_SECOND_RES);

		/* Enable watchdog decode bit and watchdog timer */
		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
					  ~SB800_PM_WATCHDOG_DISABLE,
					  SB800_PCI_WATCHDOG_DECODE_EN);
		break;
	case sp5100:
		/* For SP5100 or SB7x0 */
		/* Enable watchdog decode bit */
		pci_read_config_dword(sp5100_tco_pci,
				      SP5100_PCI_WATCHDOG_MISC_REG,
				      &val);

		val |= SP5100_PCI_WATCHDOG_DECODE_EN;

		pci_write_config_dword(sp5100_tco_pci,
				       SP5100_PCI_WATCHDOG_MISC_REG,
				       val);

		/* Enable Watchdog timer and set the resolution to 1 sec */
		sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
					  ~SP5100_PM_WATCHDOG_DISABLE,
					  SP5100_PM_WATCHDOG_SECOND_RES);
		break;
	case efch:
		/* Set the Watchdog timer resolution to 1 sec and enable */
		sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
					  ~EFCH_PM_WATCHDOG_DISABLE,
					  EFCH_PM_DECODEEN_SECOND_RES);
		break;
	}
}

static u32 sp5100_tco_read_pm_reg32(u8 index)
{
	u32 val = 0;
	int i;

	for (i = 3; i >= 0; i--)
		val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);

	return val;
}

static int sp5100_tco_setupdevice(struct device *dev,
				  struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	const char *dev_name;
	u32 mmio_addr = 0, val;
	int ret;

	/* Request the IO ports used by this driver */
	if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
				  SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
		dev_err(dev, "I/O address 0x%04x already in use\n",
			SP5100_IO_PM_INDEX_REG);
		return -EBUSY;
	}

	/*
	 * Determine type of southbridge chipset.
	 */
	switch (tco->tco_reg_layout) {
	case sp5100:
		dev_name = SP5100_DEVNAME;
		mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
								0xfffffff8;
		break;
	case sb800:
		dev_name = SB800_DEVNAME;
		mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
								0xfffffff8;
		break;
	case efch:
		dev_name = SB800_DEVNAME;
		val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
		if (val & EFCH_PM_DECODEEN_WDT_TMREN)
			mmio_addr = EFCH_PM_WDT_ADDR;
		break;
	default:
		return -ENODEV;
	}

	/* Check MMIO address conflict */
	if (!mmio_addr ||
	    !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
				     dev_name)) {
		if (mmio_addr)
			dev_dbg(dev, "MMIO address 0x%08x already in use\n",
				mmio_addr);
		switch (tco->tco_reg_layout) {
		case sp5100:
			/*
			 * Secondly, Find the watchdog timer MMIO address
			 * from SBResource_MMIO register.
			 */
			/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
			pci_read_config_dword(sp5100_tco_pci,
					      SP5100_SB_RESOURCE_MMIO_BASE,
					      &mmio_addr);
			if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
					  SB800_ACPI_MMIO_SEL)) !=
						  SB800_ACPI_MMIO_DECODE_EN) {
				ret = -ENODEV;
				goto unreg_region;
			}
			mmio_addr &= ~0xFFF;
			mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
			break;
		case sb800:
			/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
			mmio_addr =
				sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
			if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
					  SB800_ACPI_MMIO_SEL)) !=
						  SB800_ACPI_MMIO_DECODE_EN) {
				ret = -ENODEV;
				goto unreg_region;
			}
			mmio_addr &= ~0xFFF;
			mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
			break;
		case efch:
			val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
			if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
				ret = -ENODEV;
				goto unreg_region;
			}
			mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
				    EFCH_PM_ACPI_MMIO_WDT_OFFSET;
			break;
		}
		dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
			mmio_addr);
		if (!devm_request_mem_region(dev, mmio_addr,
					     SP5100_WDT_MEM_MAP_SIZE,
					     dev_name)) {
			dev_dbg(dev, "MMIO address 0x%08x already in use\n",
				mmio_addr);
			ret = -EBUSY;
			goto unreg_region;
		}
	}

	tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
	if (!tco->tcobase) {
		dev_err(dev, "failed to get tcobase address\n");
		ret = -ENOMEM;
		goto unreg_region;
	}

	dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);

	/* Setup the watchdog timer */
	tco_timer_enable(tco);

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	if (val & SP5100_WDT_DISABLED) {
		dev_err(dev, "Watchdog hardware is disabled\n");
		ret = -ENODEV;
		goto unreg_region;
	}

	/*
	 * Save WatchDogFired status, because WatchDogFired flag is
	 * cleared here.
	 */
	if (val & SP5100_WDT_FIRED)
		wdd->bootstatus = WDIOF_CARDRESET;
	/* Set watchdog action to reset the system */
	val &= ~SP5100_WDT_ACTION_RESET;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	/* Set a reasonable heartbeat before we stop the timer */
	tco_timer_set_timeout(wdd, wdd->timeout);

	/*
	 * Stop the TCO before we change anything so we don't race with
	 * a zeroed timer.
	 */
	tco_timer_stop(wdd);

	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);

	return 0;

unreg_region:
	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
	return ret;
}

static struct watchdog_info sp5100_tco_wdt_info = {
	.identity = "SP5100 TCO timer",
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops sp5100_tco_wdt_ops = {
	.owner = THIS_MODULE,
	.start = tco_timer_start,
	.stop = tco_timer_stop,
	.ping = tco_timer_ping,
	.set_timeout = tco_timer_set_timeout,
};

static int sp5100_tco_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct sp5100_tco *tco;
	int ret;

	tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
	if (!tco)
		return -ENOMEM;

	tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);

	wdd = &tco->wdd;
	wdd->parent = dev;
	wdd->info = &sp5100_tco_wdt_info;
	wdd->ops = &sp5100_tco_wdt_ops;
	wdd->timeout = WATCHDOG_HEARTBEAT;
	wdd->min_timeout = 1;
	wdd->max_timeout = 0xffff;

	watchdog_init_timeout(wdd, heartbeat, NULL);
	watchdog_set_nowayout(wdd, nowayout);
	watchdog_stop_on_reboot(wdd);
	watchdog_stop_on_unregister(wdd);
	watchdog_set_drvdata(wdd, tco);

	ret = sp5100_tco_setupdevice(dev, wdd);
	if (ret)
		return ret;

	ret = devm_watchdog_register_device(dev, wdd);
	if (ret) {
		dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
		return ret;
	}

	/* Show module parameters */
	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
		 wdd->timeout, nowayout);

	return 0;
}

static struct platform_driver sp5100_tco_driver = {
	.probe		= sp5100_tco_probe,
	.driver		= {
		.name	= TCO_DRIVER_NAME,
	},
};

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might
 * want to register another driver on the same PCI id.
 */
static const struct pci_device_id sp5100_tco_pci_tbl[] = {
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ 0, },			/* End of list */
};
MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);

static int __init sp5100_tco_init(void)
{
	struct pci_dev *dev = NULL;
	int err;

	/* Match the PCI device */
	for_each_pci_dev(dev) {
		if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
			sp5100_tco_pci = dev;
			break;
		}
	}

	if (!sp5100_tco_pci)
		return -ENODEV;

	pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");

	err = platform_driver_register(&sp5100_tco_driver);
	if (err)
		return err;

	sp5100_tco_platform_device =
		platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
	if (IS_ERR(sp5100_tco_platform_device)) {
		err = PTR_ERR(sp5100_tco_platform_device);
		goto unreg_platform_driver;
	}

	return 0;

unreg_platform_driver:
	platform_driver_unregister(&sp5100_tco_driver);
	return err;
}

static void __exit sp5100_tco_exit(void)
{
	platform_device_unregister(sp5100_tco_platform_device);
	platform_driver_unregister(&sp5100_tco_driver);
}

module_init(sp5100_tco_init);
module_exit(sp5100_tco_exit);

MODULE_AUTHOR("Priyanka Gupta");
MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
MODULE_LICENSE("GPL");
Commit	Line	Data
15e28bf1 PG	1	/*
	2	* sp5100_tco : TCO timer driver for sp5100 chipsets
	3	*
	4	* (c) Copyright 2009 Google Inc., All Rights Reserved.
	5	*
	6	* Based on i8xx_tco.c:
	7	* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
	8	* Reserved.
	9	* http://www.kernelconcepts.de
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* as published by the Free Software Foundation; either version
	14	* 2 of the License, or (at your option) any later version.
	15	*
740fbddf TT	16	* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
	17	* AMD Publication 45482 "AMD SB800-Series Southbridges Register
	18	* Reference Guide"
887d2ec5 GR	19	* AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
	20	* for AMD Family 16h Models 00h-0Fh Processors"
	21	* AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
	22	* AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
	23	* for AMD Family 16h Models 30h-3Fh Processors"
15e28bf1 PG	24	*/
	25
	26	/*
	27	* Includes, defines, variables, module parameters, ...
	28	*/
	29
27c766aa JP	30	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	31
7cd9d5ff GR	32	#include <linux/init.h>
	33	#include <linux/io.h>
	34	#include <linux/ioport.h>
15e28bf1 PG	35	#include <linux/module.h>
15e28bf1 PG	36	#include <linux/moduleparam.h>
15e28bf1	37	#include <linux/pci.h>
15e28bf1	38	#include <linux/platform_device.h>
7cd9d5ff GR	39	#include <linux/types.h>
7cd9d5ff GR	40	#include <linux/watchdog.h>
15e28bf1 PG	41
	42	#include "sp5100_tco.h"
	43
7cd9d5ff	44	#define TCO_DRIVER_NAME "sp5100-tco"
15e28bf1 PG	45
15e28bf1 PG	46	/* internal variables */
7cd9d5ff	47
887d2ec5 GR	48	enum tco_reg_layout {
	49	sp5100, sb800, efch
	50	};
	51
7cd9d5ff GR	52	struct sp5100_tco {
	53	struct watchdog_device wdd;
	54	void __iomem *tcobase;
887d2ec5	55	enum tco_reg_layout tco_reg_layout;
7cd9d5ff	56	};
15e28bf1 PG	57
	58	/* the watchdog platform device */
	59	static struct platform_device *sp5100_tco_platform_device;
7cd9d5ff GR	60	/* the associated PCI device */
7cd9d5ff GR	61	static struct pci_dev *sp5100_tco_pci;
15e28bf1 PG	62
	63	/* module parameters */
	64
	65	#define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
	66	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
	67	module_param(heartbeat, int, 0);
	68	MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
	69	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
	70
86a1e189 WVS	71	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	72	module_param(nowayout, bool, 0);
740fbddf	73	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
15e28bf1 PG	74	" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	75
	76	/*
	77	* Some TCO specific functions
	78	*/
46856fab	79
887d2ec5	80	static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
46856fab	81	{
887d2ec5 GR	82	if (dev->vendor == PCI_VENDOR_ID_ATI &&
	83	dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	84	dev->revision < 0x40) {
	85	return sp5100;
	86	} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	87	((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
	88	dev->revision >= 0x41) \|\|
	89	(dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	90	dev->revision >= 0x49))) {
	91	return efch;
	92	}
	93	return sb800;
46856fab LS	94	}
46856fab LS	95
7cd9d5ff	96	static int tco_timer_start(struct watchdog_device *wdd)
15e28bf1	97	{
7cd9d5ff	98	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	99	u32 val;
15e28bf1	100
7cd9d5ff	101	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	102	val \|= SP5100_WDT_START_STOP_BIT;
7cd9d5ff GR	103	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	104
	105	return 0;
15e28bf1 PG	106	}
15e28bf1 PG	107
7cd9d5ff	108	static int tco_timer_stop(struct watchdog_device *wdd)
15e28bf1	109	{
7cd9d5ff	110	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	111	u32 val;
15e28bf1	112
7cd9d5ff	113	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	114	val &= ~SP5100_WDT_START_STOP_BIT;
7cd9d5ff GR	115	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	116
	117	return 0;
15e28bf1 PG	118	}
15e28bf1 PG	119
7cd9d5ff	120	static int tco_timer_ping(struct watchdog_device *wdd)
15e28bf1	121	{
7cd9d5ff	122	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	123	u32 val;
15e28bf1	124
7cd9d5ff	125	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	126	val \|= SP5100_WDT_TRIGGER_BIT;
7cd9d5ff GR	127	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	128
	129	return 0;
15e28bf1 PG	130	}
15e28bf1 PG	131
7cd9d5ff GR	132	static int tco_timer_set_timeout(struct watchdog_device *wdd,
7cd9d5ff GR	133	unsigned int t)
15e28bf1	134	{
7cd9d5ff	135	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1 PG	136
15e28bf1 PG	137	/* Write new heartbeat to watchdog */
7cd9d5ff GR	138	writel(t, SP5100_WDT_COUNT(tco->tcobase));
	139
	140	wdd->timeout = t;
15e28bf1	141
15e28bf1 PG	142	return 0;
	143	}
	144
2b750cff GR	145	static u8 sp5100_tco_read_pm_reg8(u8 index)
	146	{
	147	outb(index, SP5100_IO_PM_INDEX_REG);
	148	return inb(SP5100_IO_PM_DATA_REG);
	149	}
	150
	151	static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
740fbddf	152	{
2b750cff	153	u8 val;
740fbddf	154
2b750cff GR	155	outb(index, SP5100_IO_PM_INDEX_REG);
	156	val = inb(SP5100_IO_PM_DATA_REG);
	157	val &= reset;
	158	val \|= set;
	159	outb(val, SP5100_IO_PM_DATA_REG);
	160	}
	161
887d2ec5	162	static void tco_timer_enable(struct sp5100_tco *tco)
2b750cff	163	{
887d2ec5 GR	164	u32 val;
	165
	166	switch (tco->tco_reg_layout) {
	167	case sb800:
740fbddf TT	168	/* For SB800 or later */
740fbddf TT	169	/* Set the Watchdog timer resolution to 1 sec */
2b750cff GR	170	sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
2b750cff GR	171	0xff, SB800_PM_WATCHDOG_SECOND_RES);
740fbddf TT	172
740fbddf TT	173	/* Enable watchdog decode bit and watchdog timer */
2b750cff GR	174	sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
	175	~SB800_PM_WATCHDOG_DISABLE,
	176	SB800_PCI_WATCHDOG_DECODE_EN);
887d2ec5 GR	177	break;
887d2ec5 GR	178	case sp5100:
740fbddf TT	179	/* For SP5100 or SB7x0 */
	180	/* Enable watchdog decode bit */
	181	pci_read_config_dword(sp5100_tco_pci,
	182	SP5100_PCI_WATCHDOG_MISC_REG,
	183	&val);
	184
	185	val \|= SP5100_PCI_WATCHDOG_DECODE_EN;
	186
	187	pci_write_config_dword(sp5100_tco_pci,
	188	SP5100_PCI_WATCHDOG_MISC_REG,
	189	val);
	190
	191	/* Enable Watchdog timer and set the resolution to 1 sec */
2b750cff GR	192	sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
	193	~SP5100_PM_WATCHDOG_DISABLE,
	194	SP5100_PM_WATCHDOG_SECOND_RES);
887d2ec5 GR	195	break;
	196	case efch:
	197	/* Set the Watchdog timer resolution to 1 sec and enable */
	198	sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
	199	~EFCH_PM_WATCHDOG_DISABLE,
	200	EFCH_PM_DECODEEN_SECOND_RES);
	201	break;
740fbddf TT	202	}
	203	}
	204
7cd9d5ff	205	static u32 sp5100_tco_read_pm_reg32(u8 index)
2b750cff GR	206	{
	207	u32 val = 0;
	208	int i;
	209
	210	for (i = 3; i >= 0; i--)
	211	val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
	212
	213	return val;
	214	}
	215
7cd9d5ff GR	216	static int sp5100_tco_setupdevice(struct device *dev,
7cd9d5ff GR	217	struct watchdog_device *wdd)
15e28bf1	218	{
7cd9d5ff GR	219	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
7cd9d5ff GR	220	const char *dev_name;
887d2ec5	221	u32 mmio_addr = 0, val;
23dfe140	222	int ret;
15e28bf1	223
15e28bf1	224	/* Request the IO ports used by this driver */
16e7730b	225	if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
887d2ec5	226	SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
fd8f9093 GR	227	dev_err(dev, "I/O address 0x%04x already in use\n",
fd8f9093 GR	228	SP5100_IO_PM_INDEX_REG);
23dfe140	229	return -EBUSY;
15e28bf1 PG	230	}
15e28bf1 PG	231
740fbddf	232	/*
887d2ec5	233	* Determine type of southbridge chipset.
740fbddf	234	*/
887d2ec5 GR	235	switch (tco->tco_reg_layout) {
	236	case sp5100:
	237	dev_name = SP5100_DEVNAME;
	238	mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
	239	0xfffffff8;
	240	break;
	241	case sb800:
	242	dev_name = SB800_DEVNAME;
	243	mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
	244	0xfffffff8;
	245	break;
	246	case efch:
	247	dev_name = SB800_DEVNAME;
	248	val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
	249	if (val & EFCH_PM_DECODEEN_WDT_TMREN)
	250	mmio_addr = EFCH_PM_WDT_ADDR;
	251	break;
	252	default:
	253	return -ENODEV;
	254	}
740fbddf TT	255
740fbddf TT	256	/* Check MMIO address conflict */
887d2ec5 GR	257	if (!mmio_addr \|\|
887d2ec5 GR	258	!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
7cd9d5ff	259	dev_name)) {
887d2ec5 GR	260	if (mmio_addr)
	261	dev_dbg(dev, "MMIO address 0x%08x already in use\n",
	262	mmio_addr);
	263	switch (tco->tco_reg_layout) {
	264	case sp5100:
	265	/*
	266	* Secondly, Find the watchdog timer MMIO address
	267	* from SBResource_MMIO register.
	268	*/
e189410c GR	269	/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
	270	pci_read_config_dword(sp5100_tco_pci,
	271	SP5100_SB_RESOURCE_MMIO_BASE,
887d2ec5 GR	272	&mmio_addr);
	273	if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN \|
	274	SB800_ACPI_MMIO_SEL)) !=
	275	SB800_ACPI_MMIO_DECODE_EN) {
	276	ret = -ENODEV;
	277	goto unreg_region;
	278	}
	279	mmio_addr &= ~0xFFF;
	280	mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
	281	break;
	282	case sb800:
e189410c	283	/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
887d2ec5 GR	284	mmio_addr =
	285	sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
	286	if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN \|
	287	SB800_ACPI_MMIO_SEL)) !=
740fbddf	288	SB800_ACPI_MMIO_DECODE_EN) {
887d2ec5 GR	289	ret = -ENODEV;
	290	goto unreg_region;
	291	}
	292	mmio_addr &= ~0xFFF;
	293	mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
	294	break;
	295	case efch:
	296	val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
	297	if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
	298	ret = -ENODEV;
	299	goto unreg_region;
	300	}
	301	mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
	302	EFCH_PM_ACPI_MMIO_WDT_OFFSET;
	303	break;
e189410c	304	}
887d2ec5 GR	305	dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
	306	mmio_addr);
	307	if (!devm_request_mem_region(dev, mmio_addr,
	308	SP5100_WDT_MEM_MAP_SIZE,
7cd9d5ff	309	dev_name)) {
887d2ec5 GR	310	dev_dbg(dev, "MMIO address 0x%08x already in use\n",
887d2ec5 GR	311	mmio_addr);
e189410c GR	312	ret = -EBUSY;
	313	goto unreg_region;
	314	}
e189410c	315	}
740fbddf	316
887d2ec5	317	tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
7cd9d5ff	318	if (!tco->tcobase) {
fd8f9093	319	dev_err(dev, "failed to get tcobase address\n");
23dfe140	320	ret = -ENOMEM;
7cd9d5ff	321	goto unreg_region;
15e28bf1 PG	322	}
15e28bf1 PG	323
887d2ec5	324	dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
15e28bf1	325
740fbddf	326	/* Setup the watchdog timer */
887d2ec5	327	tco_timer_enable(tco);
15e28bf1	328
7cd9d5ff	329	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
f7781b06 GR	330	if (val & SP5100_WDT_DISABLED) {
	331	dev_err(dev, "Watchdog hardware is disabled\n");
	332	ret = -ENODEV;
	333	goto unreg_region;
	334	}
	335
740fbddf TT	336	/*
	337	* Save WatchDogFired status, because WatchDogFired flag is
	338	* cleared here.
	339	*/
7cd9d5ff GR	340	if (val & SP5100_WDT_FIRED)
7cd9d5ff GR	341	wdd->bootstatus = WDIOF_CARDRESET;
f7781b06	342	/* Set watchdog action to reset the system */
5bbecc5d	343	val &= ~SP5100_WDT_ACTION_RESET;
7cd9d5ff	344	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1 PG	345
15e28bf1 PG	346	/* Set a reasonable heartbeat before we stop the timer */
7cd9d5ff	347	tco_timer_set_timeout(wdd, wdd->timeout);
15e28bf1 PG	348
	349	/*
	350	* Stop the TCO before we change anything so we don't race with
	351	* a zeroed timer.
	352	*/
7cd9d5ff	353	tco_timer_stop(wdd);
15e28bf1	354
16e7730b	355	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
e189410c	356
23dfe140	357	return 0;
15e28bf1	358
15e28bf1	359	unreg_region:
2b750cff	360	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
23dfe140	361	return ret;
15e28bf1 PG	362	}
15e28bf1 PG	363
7cd9d5ff GR	364	static struct watchdog_info sp5100_tco_wdt_info = {
	365	.identity = "SP5100 TCO timer",
	366	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	367	};
	368
	369	static const struct watchdog_ops sp5100_tco_wdt_ops = {
	370	.owner = THIS_MODULE,
	371	.start = tco_timer_start,
	372	.stop = tco_timer_stop,
	373	.ping = tco_timer_ping,
	374	.set_timeout = tco_timer_set_timeout,
	375	};
	376
5bbecc5d	377	static int sp5100_tco_probe(struct platform_device *pdev)
15e28bf1	378	{
fd8f9093	379	struct device *dev = &pdev->dev;
7cd9d5ff GR	380	struct watchdog_device *wdd;
7cd9d5ff GR	381	struct sp5100_tco *tco;
15e28bf1	382	int ret;
15e28bf1	383
7cd9d5ff GR	384	tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
	385	if (!tco)
	386	return -ENOMEM;
	387
887d2ec5 GR	388	tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
887d2ec5 GR	389
7cd9d5ff GR	390	wdd = &tco->wdd;
	391	wdd->parent = dev;
	392	wdd->info = &sp5100_tco_wdt_info;
	393	wdd->ops = &sp5100_tco_wdt_ops;
	394	wdd->timeout = WATCHDOG_HEARTBEAT;
	395	wdd->min_timeout = 1;
	396	wdd->max_timeout = 0xffff;
	397
2d505e3e	398	watchdog_init_timeout(wdd, heartbeat, NULL);
7cd9d5ff GR	399	watchdog_set_nowayout(wdd, nowayout);
	400	watchdog_stop_on_reboot(wdd);
	401	watchdog_stop_on_unregister(wdd);
	402	watchdog_set_drvdata(wdd, tco);
	403
	404	ret = sp5100_tco_setupdevice(dev, wdd);
23dfe140 GR	405	if (ret)
23dfe140 GR	406	return ret;
15e28bf1	407
7cd9d5ff GR	408	ret = devm_watchdog_register_device(dev, wdd);
	409	if (ret) {
	410	dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
	411	return ret;
15e28bf1 PG	412	}
15e28bf1 PG	413
740fbddf	414	/* Show module parameters */
7cd9d5ff GR	415	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
7cd9d5ff GR	416	wdd->timeout, nowayout);
15e28bf1 PG	417
15e28bf1 PG	418	return 0;
15e28bf1 PG	419	}
	420
	421	static struct platform_driver sp5100_tco_driver = {
5bbecc5d	422	.probe = sp5100_tco_probe,
15e28bf1	423	.driver = {
7cd9d5ff	424	.name = TCO_DRIVER_NAME,
15e28bf1 PG	425	},
	426	};
	427
a3483443 GR	428	/*
	429	* Data for PCI driver interface
	430	*
	431	* This data only exists for exporting the supported
	432	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	433	* register a pci_driver, because someone else might
	434	* want to register another driver on the same PCI id.
	435	*/
	436	static const struct pci_device_id sp5100_tco_pci_tbl[] = {
	437	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
	438	PCI_ANY_ID, },
	439	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
	440	PCI_ANY_ID, },
	441	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	442	PCI_ANY_ID, },
	443	{ 0, }, /* End of list */
	444	};
	445	MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
	446
5bbecc5d	447	static int __init sp5100_tco_init(void)
15e28bf1	448	{
a3483443	449	struct pci_dev *dev = NULL;
15e28bf1 PG	450	int err;
15e28bf1 PG	451
a3483443 GR	452	/* Match the PCI device */
	453	for_each_pci_dev(dev) {
	454	if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
	455	sp5100_tco_pci = dev;
	456	break;
	457	}
	458	}
	459
	460	if (!sp5100_tco_pci)
	461	return -ENODEV;
	462
7cd9d5ff	463	pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
15e28bf1 PG	464
	465	err = platform_driver_register(&sp5100_tco_driver);
	466	if (err)
	467	return err;
	468
7cd9d5ff GR	469	sp5100_tco_platform_device =
7cd9d5ff GR	470	platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
15e28bf1 PG	471	if (IS_ERR(sp5100_tco_platform_device)) {
	472	err = PTR_ERR(sp5100_tco_platform_device);
	473	goto unreg_platform_driver;
	474	}
	475
	476	return 0;
	477
	478	unreg_platform_driver:
	479	platform_driver_unregister(&sp5100_tco_driver);
	480	return err;
	481	}
	482
5bbecc5d	483	static void __exit sp5100_tco_exit(void)
15e28bf1 PG	484	{
	485	platform_device_unregister(sp5100_tco_platform_device);
	486	platform_driver_unregister(&sp5100_tco_driver);
15e28bf1 PG	487	}
15e28bf1 PG	488
5bbecc5d GR	489	module_init(sp5100_tco_init);
5bbecc5d GR	490	module_exit(sp5100_tco_exit);
15e28bf1 PG	491
15e28bf1 PG	492	MODULE_AUTHOR("Priyanka Gupta");
740fbddf	493	MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
15e28bf1	494	MODULE_LICENSE("GPL");