[mirror_ubuntu-bionic-kernel.git] / drivers / watchdog / sp5100_tco.h

/*
 *	sp5100_tco:	TCO timer driver for sp5100 chipsets.
 *
 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
 *
 *	TCO timer driver for sp5100 chipsets
 */

/*
 * Some address definitions for the Watchdog
 */

#define SP5100_WDT_MEM_MAP_SIZE		0x08
#define SP5100_WDT_CONTROL(base)	((base) + 0x00) /* Watchdog Control */
#define SP5100_WDT_COUNT(base)		((base) + 0x04) /* Watchdog Count */

#define SP5100_WDT_START_STOP_BIT	1
#define SP5100_WDT_TRIGGER_BIT		(1 << 7)

#define SP5100_PCI_WATCHDOG_MISC_REG	0x41
#define SP5100_PCI_WATCHDOG_DECODE_EN	(1 << 3)

#define SP5100_PM_IOPORTS_SIZE		0x02

/* These two IO registers are hardcoded and there doesn't seem to be a way to
 * read them from a register.
 */
#define SP5100_IO_PM_INDEX_REG		0xCD6
#define SP5100_IO_PM_DATA_REG		0xCD7

#define SP5100_PM_WATCHDOG_CONTROL	0x69
#define SP5100_PM_WATCHDOG_BASE0	0x6C
#define SP5100_PM_WATCHDOG_BASE1	0x6D
#define SP5100_PM_WATCHDOG_BASE2	0x6E
#define SP5100_PM_WATCHDOG_BASE3	0x6F

#define SP5100_PM_WATCHDOG_FIRED	(1 << 1)
#define SP5100_PM_WATCHDOG_ACTION_RESET	(1 << 2)

#define SP5100_PM_WATCHDOG_DISABLE	1
#define SP5100_PM_WATCHDOG_SECOND_RES	(3 << 1)
Commit	Line	Data
15e28bf1 PG	1	/*
	2	* sp5100_tco: TCO timer driver for sp5100 chipsets.
	3	*
	4	* (c) Copyright 2009 Google Inc., All Rights Reserved.
	5	*
	6	* TCO timer driver for sp5100 chipsets
	7	*/
	8
	9	/*
	10	* Some address definitions for the Watchdog
	11	*/
	12
	13	#define SP5100_WDT_MEM_MAP_SIZE 0x08
	14	#define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
	15	#define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
	16
	17	#define SP5100_WDT_START_STOP_BIT 1
	18	#define SP5100_WDT_TRIGGER_BIT (1 << 7)
	19
	20	#define SP5100_PCI_WATCHDOG_MISC_REG 0x41
	21	#define SP5100_PCI_WATCHDOG_DECODE_EN (1 << 3)
	22
	23	#define SP5100_PM_IOPORTS_SIZE 0x02
	24
	25	/* These two IO registers are hardcoded and there doesn't seem to be a way to
	26	* read them from a register.
	27	*/
	28	#define SP5100_IO_PM_INDEX_REG 0xCD6
	29	#define SP5100_IO_PM_DATA_REG 0xCD7
	30
	31	#define SP5100_PM_WATCHDOG_CONTROL 0x69
	32	#define SP5100_PM_WATCHDOG_BASE0 0x6C
	33	#define SP5100_PM_WATCHDOG_BASE1 0x6D
	34	#define SP5100_PM_WATCHDOG_BASE2 0x6E
	35	#define SP5100_PM_WATCHDOG_BASE3 0x6F
	36
	37	#define SP5100_PM_WATCHDOG_FIRED (1 << 1)
	38	#define SP5100_PM_WATCHDOG_ACTION_RESET (1 << 2)
	39
	40	#define SP5100_PM_WATCHDOG_DISABLE 1
	41	#define SP5100_PM_WATCHDOG_SECOND_RES (3 << 1)