]>
Commit | Line | Data |
---|---|---|
4a370278 VK |
1 | /* |
2 | * drivers/char/watchdog/sp805-wdt.c | |
3 | * | |
4 | * Watchdog driver for ARM SP805 watchdog module | |
5 | * | |
6 | * Copyright (C) 2010 ST Microelectronics | |
10d8935f | 7 | * Viresh Kumar <viresh.linux@gmail.com> |
4a370278 VK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2 or later. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/resource.h> | |
16 | #include <linux/amba/bus.h> | |
17 | #include <linux/bitops.h> | |
18 | #include <linux/clk.h> | |
4a370278 VK |
19 | #include <linux/init.h> |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/math64.h> | |
4a370278 VK |
24 | #include <linux/module.h> |
25 | #include <linux/moduleparam.h> | |
16ac4abe | 26 | #include <linux/pm.h> |
4a370278 VK |
27 | #include <linux/slab.h> |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/types.h> | |
4a370278 VK |
30 | #include <linux/watchdog.h> |
31 | ||
32 | /* default timeout in seconds */ | |
33 | #define DEFAULT_TIMEOUT 60 | |
34 | ||
35 | #define MODULE_NAME "sp805-wdt" | |
36 | ||
37 | /* watchdog register offsets and masks */ | |
38 | #define WDTLOAD 0x000 | |
39 | #define LOAD_MIN 0x00000001 | |
40 | #define LOAD_MAX 0xFFFFFFFF | |
41 | #define WDTVALUE 0x004 | |
42 | #define WDTCONTROL 0x008 | |
43 | /* control register masks */ | |
44 | #define INT_ENABLE (1 << 0) | |
45 | #define RESET_ENABLE (1 << 1) | |
46 | #define WDTINTCLR 0x00C | |
47 | #define WDTRIS 0x010 | |
48 | #define WDTMIS 0x014 | |
49 | #define INT_MASK (1 << 0) | |
50 | #define WDTLOCK 0xC00 | |
51 | #define UNLOCK 0x1ACCE551 | |
52 | #define LOCK 0x00000001 | |
53 | ||
54 | /** | |
55 | * struct sp805_wdt: sp805 wdt device structure | |
4a516539 | 56 | * @wdd: instance of struct watchdog_device |
bfae14b6 VK |
57 | * @lock: spin lock protecting dev structure and io access |
58 | * @base: base address of wdt | |
59 | * @clk: clock structure of wdt | |
60 | * @adev: amba device structure of wdt | |
61 | * @status: current status of wdt | |
62 | * @load_val: load value to be set for current timeout | |
63 | * @timeout: current programmed timeout | |
4a370278 VK |
64 | */ |
65 | struct sp805_wdt { | |
4a516539 | 66 | struct watchdog_device wdd; |
4a370278 VK |
67 | spinlock_t lock; |
68 | void __iomem *base; | |
69 | struct clk *clk; | |
70 | struct amba_device *adev; | |
4a370278 VK |
71 | unsigned int load_val; |
72 | unsigned int timeout; | |
73 | }; | |
74 | ||
86a1e189 | 75 | static bool nowayout = WATCHDOG_NOWAYOUT; |
4a516539 VK |
76 | module_param(nowayout, bool, 0); |
77 | MODULE_PARM_DESC(nowayout, | |
78 | "Set to 1 to keep watchdog running after device release"); | |
4a370278 VK |
79 | |
80 | /* This routine finds load value that will reset system in required timout */ | |
4a516539 | 81 | static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout) |
4a370278 | 82 | { |
4a516539 | 83 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 VK |
84 | u64 load, rate; |
85 | ||
86 | rate = clk_get_rate(wdt->clk); | |
87 | ||
88 | /* | |
89 | * sp805 runs counter with given value twice, after the end of first | |
90 | * counter it gives an interrupt and then starts counter again. If | |
25985edc | 91 | * interrupt already occurred then it resets the system. This is why |
4a370278 VK |
92 | * load is half of what should be required. |
93 | */ | |
94 | load = div_u64(rate, 2) * timeout - 1; | |
95 | ||
96 | load = (load > LOAD_MAX) ? LOAD_MAX : load; | |
97 | load = (load < LOAD_MIN) ? LOAD_MIN : load; | |
98 | ||
99 | spin_lock(&wdt->lock); | |
100 | wdt->load_val = load; | |
101 | /* roundup timeout to closest positive integer value */ | |
102 | wdt->timeout = div_u64((load + 1) * 2 + (rate / 2), rate); | |
103 | spin_unlock(&wdt->lock); | |
4a516539 VK |
104 | |
105 | return 0; | |
4a370278 VK |
106 | } |
107 | ||
108 | /* returns number of seconds left for reset to occur */ | |
4a516539 | 109 | static unsigned int wdt_timeleft(struct watchdog_device *wdd) |
4a370278 | 110 | { |
4a516539 | 111 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 VK |
112 | u64 load, rate; |
113 | ||
114 | rate = clk_get_rate(wdt->clk); | |
115 | ||
116 | spin_lock(&wdt->lock); | |
d2e8919b | 117 | load = readl_relaxed(wdt->base + WDTVALUE); |
4a370278 VK |
118 | |
119 | /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */ | |
d2e8919b | 120 | if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) |
4a370278 VK |
121 | load += wdt->load_val + 1; |
122 | spin_unlock(&wdt->lock); | |
123 | ||
124 | return div_u64(load, rate); | |
125 | } | |
126 | ||
4a516539 | 127 | static int wdt_config(struct watchdog_device *wdd, bool ping) |
4a370278 | 128 | { |
4a516539 VK |
129 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
130 | int ret; | |
131 | ||
132 | if (!ping) { | |
d9df0ef1 VK |
133 | ret = clk_prepare(wdt->clk); |
134 | if (ret) { | |
135 | dev_err(&wdt->adev->dev, "clock prepare fail"); | |
136 | return ret; | |
137 | } | |
138 | ||
4a516539 VK |
139 | ret = clk_enable(wdt->clk); |
140 | if (ret) { | |
141 | dev_err(&wdt->adev->dev, "clock enable fail"); | |
d9df0ef1 | 142 | clk_unprepare(wdt->clk); |
4a516539 VK |
143 | return ret; |
144 | } | |
145 | } | |
146 | ||
4a370278 VK |
147 | spin_lock(&wdt->lock); |
148 | ||
d2e8919b VK |
149 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
150 | writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); | |
4a370278 | 151 | |
4a516539 VK |
152 | if (!ping) { |
153 | writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); | |
154 | writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + | |
155 | WDTCONTROL); | |
156 | } | |
4a370278 | 157 | |
d2e8919b | 158 | writel_relaxed(LOCK, wdt->base + WDTLOCK); |
4a370278 | 159 | |
081d83a3 | 160 | /* Flush posted writes. */ |
d2e8919b | 161 | readl_relaxed(wdt->base + WDTLOCK); |
4a370278 | 162 | spin_unlock(&wdt->lock); |
4a516539 VK |
163 | |
164 | return 0; | |
4a370278 VK |
165 | } |
166 | ||
4a516539 | 167 | static int wdt_ping(struct watchdog_device *wdd) |
4a370278 | 168 | { |
4a516539 | 169 | return wdt_config(wdd, true); |
4a370278 VK |
170 | } |
171 | ||
4a516539 VK |
172 | /* enables watchdog timers reset */ |
173 | static int wdt_enable(struct watchdog_device *wdd) | |
4a370278 | 174 | { |
4a516539 | 175 | return wdt_config(wdd, false); |
4a370278 VK |
176 | } |
177 | ||
4a516539 VK |
178 | /* disables watchdog timers reset */ |
179 | static int wdt_disable(struct watchdog_device *wdd) | |
4a370278 | 180 | { |
4a516539 | 181 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 | 182 | |
4a516539 | 183 | spin_lock(&wdt->lock); |
4a370278 | 184 | |
4a516539 VK |
185 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
186 | writel_relaxed(0, wdt->base + WDTCONTROL); | |
187 | writel_relaxed(LOCK, wdt->base + WDTLOCK); | |
4a370278 | 188 | |
4a516539 VK |
189 | /* Flush posted writes. */ |
190 | readl_relaxed(wdt->base + WDTLOCK); | |
191 | spin_unlock(&wdt->lock); | |
4a370278 | 192 | |
4a370278 | 193 | clk_disable(wdt->clk); |
d9df0ef1 | 194 | clk_unprepare(wdt->clk); |
4a370278 VK |
195 | |
196 | return 0; | |
197 | } | |
198 | ||
4a516539 VK |
199 | static const struct watchdog_info wdt_info = { |
200 | .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
201 | .identity = MODULE_NAME, | |
4a370278 VK |
202 | }; |
203 | ||
4a516539 VK |
204 | static const struct watchdog_ops wdt_ops = { |
205 | .owner = THIS_MODULE, | |
206 | .start = wdt_enable, | |
207 | .stop = wdt_disable, | |
208 | .ping = wdt_ping, | |
209 | .set_timeout = wdt_setload, | |
210 | .get_timeleft = wdt_timeleft, | |
4a370278 VK |
211 | }; |
212 | ||
213 | static int __devinit | |
aa25afad | 214 | sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id) |
4a370278 | 215 | { |
4a516539 | 216 | struct sp805_wdt *wdt; |
4a370278 VK |
217 | int ret = 0; |
218 | ||
fb35a5ad VK |
219 | if (!devm_request_mem_region(&adev->dev, adev->res.start, |
220 | resource_size(&adev->res), "sp805_wdt")) { | |
4a370278 VK |
221 | dev_warn(&adev->dev, "Failed to get memory region resource\n"); |
222 | ret = -ENOENT; | |
223 | goto err; | |
224 | } | |
225 | ||
fb35a5ad | 226 | wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL); |
4a370278 VK |
227 | if (!wdt) { |
228 | dev_warn(&adev->dev, "Kzalloc failed\n"); | |
229 | ret = -ENOMEM; | |
fb35a5ad VK |
230 | goto err; |
231 | } | |
232 | ||
233 | wdt->base = devm_ioremap(&adev->dev, adev->res.start, | |
234 | resource_size(&adev->res)); | |
235 | if (!wdt->base) { | |
236 | ret = -ENOMEM; | |
237 | dev_warn(&adev->dev, "ioremap fail\n"); | |
238 | goto err; | |
4a370278 VK |
239 | } |
240 | ||
241 | wdt->clk = clk_get(&adev->dev, NULL); | |
242 | if (IS_ERR(wdt->clk)) { | |
243 | dev_warn(&adev->dev, "Clock not found\n"); | |
244 | ret = PTR_ERR(wdt->clk); | |
fb35a5ad | 245 | goto err; |
4a370278 VK |
246 | } |
247 | ||
248 | wdt->adev = adev; | |
4a516539 VK |
249 | wdt->wdd.info = &wdt_info; |
250 | wdt->wdd.ops = &wdt_ops; | |
251 | ||
4a370278 | 252 | spin_lock_init(&wdt->lock); |
4a516539 VK |
253 | watchdog_set_nowayout(&wdt->wdd, nowayout); |
254 | watchdog_set_drvdata(&wdt->wdd, wdt); | |
255 | wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT); | |
4a370278 | 256 | |
4a516539 VK |
257 | ret = watchdog_register_device(&wdt->wdd); |
258 | if (ret) { | |
259 | dev_err(&adev->dev, "watchdog_register_device() failed: %d\n", | |
260 | ret); | |
261 | goto err_register; | |
4a370278 | 262 | } |
4a516539 | 263 | amba_set_drvdata(adev, wdt); |
4a370278 VK |
264 | |
265 | dev_info(&adev->dev, "registration successful\n"); | |
266 | return 0; | |
267 | ||
4a516539 | 268 | err_register: |
4a370278 | 269 | clk_put(wdt->clk); |
4a370278 VK |
270 | err: |
271 | dev_err(&adev->dev, "Probe Failed!!!\n"); | |
272 | return ret; | |
273 | } | |
274 | ||
275 | static int __devexit sp805_wdt_remove(struct amba_device *adev) | |
276 | { | |
4a516539 VK |
277 | struct sp805_wdt *wdt = amba_get_drvdata(adev); |
278 | ||
279 | watchdog_unregister_device(&wdt->wdd); | |
280 | amba_set_drvdata(adev, NULL); | |
281 | watchdog_set_drvdata(&wdt->wdd, NULL); | |
4a370278 | 282 | clk_put(wdt->clk); |
4a370278 VK |
283 | |
284 | return 0; | |
285 | } | |
286 | ||
16ac4abe VK |
287 | #ifdef CONFIG_PM |
288 | static int sp805_wdt_suspend(struct device *dev) | |
289 | { | |
4a516539 VK |
290 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
291 | ||
292 | if (watchdog_active(&wdt->wdd)) | |
293 | return wdt_disable(&wdt->wdd); | |
16ac4abe VK |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
298 | static int sp805_wdt_resume(struct device *dev) | |
299 | { | |
4a516539 | 300 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
16ac4abe | 301 | |
4a516539 VK |
302 | if (watchdog_active(&wdt->wdd)) |
303 | return wdt_enable(&wdt->wdd); | |
16ac4abe | 304 | |
4a516539 | 305 | return 0; |
16ac4abe VK |
306 | } |
307 | #endif /* CONFIG_PM */ | |
308 | ||
309 | static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend, | |
310 | sp805_wdt_resume); | |
311 | ||
bb558dac | 312 | static struct amba_id sp805_wdt_ids[] = { |
4a370278 VK |
313 | { |
314 | .id = 0x00141805, | |
315 | .mask = 0x00ffffff, | |
316 | }, | |
317 | { 0, 0 }, | |
318 | }; | |
319 | ||
17885b05 DM |
320 | MODULE_DEVICE_TABLE(amba, sp805_wdt_ids); |
321 | ||
4a370278 VK |
322 | static struct amba_driver sp805_wdt_driver = { |
323 | .drv = { | |
324 | .name = MODULE_NAME, | |
16ac4abe | 325 | .pm = &sp805_wdt_dev_pm_ops, |
4a370278 VK |
326 | }, |
327 | .id_table = sp805_wdt_ids, | |
328 | .probe = sp805_wdt_probe, | |
329 | .remove = __devexit_p(sp805_wdt_remove), | |
330 | }; | |
331 | ||
9e5ed094 | 332 | module_amba_driver(sp805_wdt_driver); |
4a370278 | 333 | |
10d8935f | 334 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |
4a370278 VK |
335 | MODULE_DESCRIPTION("ARM SP805 Watchdog Driver"); |
336 | MODULE_LICENSE("GPL"); |