[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / sunxi_wdt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *      sunxi Watchdog Driver
 *
 *      Copyright (c) 2013 Carlo Caione
 *                    2012 Henrik Nordstrom
 *
 *      Based on xen_wdt.c
 *      (c) Copyright 2010 Novell, Inc.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>

#define WDT_MAX_TIMEOUT         16
#define WDT_MIN_TIMEOUT         1
#define WDT_TIMEOUT_MASK        0x0F

#define WDT_CTRL_RELOAD         ((1 << 0) | (0x0a57 << 1))

#define WDT_MODE_EN             (1 << 0)

#define DRV_NAME		"sunxi-wdt"
#define DRV_VERSION		"1.0"

static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout;

/*
 * This structure stores the register offsets for different variants
 * of Allwinner's watchdog hardware.
 */
struct sunxi_wdt_reg {
	u8 wdt_ctrl;
	u8 wdt_cfg;
	u8 wdt_mode;
	u8 wdt_timeout_shift;
	u8 wdt_reset_mask;
	u8 wdt_reset_val;
};

struct sunxi_wdt_dev {
	struct watchdog_device wdt_dev;
	void __iomem *wdt_base;
	const struct sunxi_wdt_reg *wdt_regs;
};

/*
 * wdt_timeout_map maps the watchdog timer interval value in seconds to
 * the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
 *
 * [timeout seconds] = register value
 *
 */

static const int wdt_timeout_map[] = {
	[1] = 0x1,  /* 1s  */
	[2] = 0x2,  /* 2s  */
	[3] = 0x3,  /* 3s  */
	[4] = 0x4,  /* 4s  */
	[5] = 0x5,  /* 5s  */
	[6] = 0x6,  /* 6s  */
	[8] = 0x7,  /* 8s  */
	[10] = 0x8, /* 10s */
	[12] = 0x9, /* 12s */
	[14] = 0xA, /* 14s */
	[16] = 0xB, /* 16s */
};


static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
			     unsigned long action, void *data)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	u32 val;

	/* Set system reset function */
	val = readl(wdt_base + regs->wdt_cfg);
	val &= ~(regs->wdt_reset_mask);
	val |= regs->wdt_reset_val;
	writel(val, wdt_base + regs->wdt_cfg);

	/* Set lowest timeout and enable watchdog */
	val = readl(wdt_base + regs->wdt_mode);
	val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	val |= WDT_MODE_EN;
	writel(val, wdt_base + regs->wdt_mode);

	/*
	 * Restart the watchdog. The default (and lowest) interval
	 * value for the watchdog is 0.5s.
	 */
	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);

	while (1) {
		mdelay(5);
		val = readl(wdt_base + regs->wdt_mode);
		val |= WDT_MODE_EN;
		writel(val, wdt_base + regs->wdt_mode);
	}
	return 0;
}

static int sunxi_wdt_ping(struct watchdog_device *wdt_dev)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;

	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);

	return 0;
}

static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
		unsigned int timeout)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	u32 reg;

	if (wdt_timeout_map[timeout] == 0)
		timeout++;

	sunxi_wdt->wdt_dev.timeout = timeout;

	reg = readl(wdt_base + regs->wdt_mode);
	reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
	writel(reg, wdt_base + regs->wdt_mode);

	sunxi_wdt_ping(wdt_dev);

	return 0;
}

static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;

	writel(0, wdt_base + regs->wdt_mode);

	return 0;
}

static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
{
	u32 reg;
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	int ret;

	ret = sunxi_wdt_set_timeout(&sunxi_wdt->wdt_dev,
			sunxi_wdt->wdt_dev.timeout);
	if (ret < 0)
		return ret;

	/* Set system reset function */
	reg = readl(wdt_base + regs->wdt_cfg);
	reg &= ~(regs->wdt_reset_mask);
	reg |= regs->wdt_reset_val;
	writel(reg, wdt_base + regs->wdt_cfg);

	/* Enable watchdog */
	reg = readl(wdt_base + regs->wdt_mode);
	reg |= WDT_MODE_EN;
	writel(reg, wdt_base + regs->wdt_mode);

	return 0;
}

static const struct watchdog_info sunxi_wdt_info = {
	.identity	= DRV_NAME,
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops sunxi_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= sunxi_wdt_start,
	.stop		= sunxi_wdt_stop,
	.ping		= sunxi_wdt_ping,
	.set_timeout	= sunxi_wdt_set_timeout,
	.restart	= sunxi_wdt_restart,
};

static const struct sunxi_wdt_reg sun4i_wdt_reg = {
	.wdt_ctrl = 0x00,
	.wdt_cfg = 0x04,
	.wdt_mode = 0x04,
	.wdt_timeout_shift = 3,
	.wdt_reset_mask = 0x02,
	.wdt_reset_val = 0x02,
};

static const struct sunxi_wdt_reg sun6i_wdt_reg = {
	.wdt_ctrl = 0x10,
	.wdt_cfg = 0x14,
	.wdt_mode = 0x18,
	.wdt_timeout_shift = 4,
	.wdt_reset_mask = 0x03,
	.wdt_reset_val = 0x01,
};

static const struct of_device_id sunxi_wdt_dt_ids[] = {
	{ .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
	{ .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);

static int sunxi_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct sunxi_wdt_dev *sunxi_wdt;
	int err;

	sunxi_wdt = devm_kzalloc(dev, sizeof(*sunxi_wdt), GFP_KERNEL);
	if (!sunxi_wdt)
		return -ENOMEM;

	sunxi_wdt->wdt_regs = of_device_get_match_data(dev);
	if (!sunxi_wdt->wdt_regs)
		return -ENODEV;

	sunxi_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(sunxi_wdt->wdt_base))
		return PTR_ERR(sunxi_wdt->wdt_base);

	sunxi_wdt->wdt_dev.info = &sunxi_wdt_info;
	sunxi_wdt->wdt_dev.ops = &sunxi_wdt_ops;
	sunxi_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
	sunxi_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
	sunxi_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
	sunxi_wdt->wdt_dev.parent = dev;

	watchdog_init_timeout(&sunxi_wdt->wdt_dev, timeout, dev);
	watchdog_set_nowayout(&sunxi_wdt->wdt_dev, nowayout);
	watchdog_set_restart_priority(&sunxi_wdt->wdt_dev, 128);

	watchdog_set_drvdata(&sunxi_wdt->wdt_dev, sunxi_wdt);

	sunxi_wdt_stop(&sunxi_wdt->wdt_dev);

	watchdog_stop_on_reboot(&sunxi_wdt->wdt_dev);
	err = devm_watchdog_register_device(dev, &sunxi_wdt->wdt_dev);
	if (unlikely(err))
		return err;

	dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
		 sunxi_wdt->wdt_dev.timeout, nowayout);

	return 0;
}

static struct platform_driver sunxi_wdt_driver = {
	.probe		= sunxi_wdt_probe,
	.driver		= {
		.name		= DRV_NAME,
		.of_match_table	= sunxi_wdt_dt_ids,
	},
};

module_platform_driver(sunxi_wdt_driver);

module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
MODULE_AUTHOR("Henrik Nordstrom <henrik@henriknordstrom.net>");
MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
d00680ed CC	2	/*
	3	* sunxi Watchdog Driver
	4	*
	5	* Copyright (c) 2013 Carlo Caione
	6	* 2012 Henrik Nordstrom
	7	*
d00680ed CC	8	* Based on xen_wdt.c
	9	* (c) Copyright 2010 Novell, Inc.
	10	*/
	11
	12	#include <linux/clk.h>
440e96bc	13	#include <linux/delay.h>
d00680ed CC	14	#include <linux/err.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/moduleparam.h>
	20	#include <linux/of.h>
f2147de3	21	#include <linux/of_device.h>
d00680ed CC	22	#include <linux/platform_device.h>
	23	#include <linux/types.h>
	24	#include <linux/watchdog.h>
	25
	26	#define WDT_MAX_TIMEOUT 16
	27	#define WDT_MIN_TIMEOUT 1
f2147de3	28	#define WDT_TIMEOUT_MASK 0x0F
d00680ed	29
d00680ed CC	30	#define WDT_CTRL_RELOAD ((1 << 0) \| (0x0a57 << 1))
d00680ed CC	31
d00680ed	32	#define WDT_MODE_EN (1 << 0)
d00680ed CC	33
	34	#define DRV_NAME "sunxi-wdt"
	35	#define DRV_VERSION "1.0"
	36
	37	static bool nowayout = WATCHDOG_NOWAYOUT;
1d1dedc2	38	static unsigned int timeout;
d00680ed	39
f2147de3 CYT	40	/*
	41	* This structure stores the register offsets for different variants
	42	* of Allwinner's watchdog hardware.
	43	*/
	44	struct sunxi_wdt_reg {
	45	u8 wdt_ctrl;
	46	u8 wdt_cfg;
	47	u8 wdt_mode;
	48	u8 wdt_timeout_shift;
	49	u8 wdt_reset_mask;
	50	u8 wdt_reset_val;
	51	};
	52
d00680ed CC	53	struct sunxi_wdt_dev {
	54	struct watchdog_device wdt_dev;
	55	void __iomem *wdt_base;
f2147de3	56	const struct sunxi_wdt_reg *wdt_regs;
d00680ed CC	57	};
	58
	59	/*
	60	* wdt_timeout_map maps the watchdog timer interval value in seconds to
f2147de3	61	* the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
d00680ed CC	62	*
	63	* [timeout seconds] = register value
	64	*
	65	*/
	66
	67	static const int wdt_timeout_map[] = {
51ee34ab EL	68	[1] = 0x1, /* 1s */
	69	[2] = 0x2, /* 2s */
	70	[3] = 0x3, /* 3s */
	71	[4] = 0x4, /* 4s */
	72	[5] = 0x5, /* 5s */
	73	[6] = 0x6, /* 6s */
	74	[8] = 0x7, /* 8s */
	75	[10] = 0x8, /* 10s */
	76	[12] = 0x9, /* 12s */
	77	[14] = 0xA, /* 14s */
	78	[16] = 0xB, /* 16s */
d00680ed CC	79	};
d00680ed CC	80
440e96bc	81
4d8b229d GR	82	static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
4d8b229d GR	83	unsigned long action, void *data)
440e96bc	84	{
0ebad1e5	85	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
d20a1d90	86	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3 CYT	87	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	88	u32 val;
	89
	90	/* Set system reset function */
	91	val = readl(wdt_base + regs->wdt_cfg);
	92	val &= ~(regs->wdt_reset_mask);
	93	val \|= regs->wdt_reset_val;
	94	writel(val, wdt_base + regs->wdt_cfg);
d20a1d90	95
f2147de3 CYT	96	/* Set lowest timeout and enable watchdog */
	97	val = readl(wdt_base + regs->wdt_mode);
	98	val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	99	val \|= WDT_MODE_EN;
	100	writel(val, wdt_base + regs->wdt_mode);
440e96bc MR	101
	102	/*
	103	* Restart the watchdog. The default (and lowest) interval
	104	* value for the watchdog is 0.5s.
	105	*/
f2147de3	106	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
440e96bc MR	107
	108	while (1) {
	109	mdelay(5);
f2147de3 CYT	110	val = readl(wdt_base + regs->wdt_mode);
	111	val \|= WDT_MODE_EN;
	112	writel(val, wdt_base + regs->wdt_mode);
440e96bc	113	}
0ebad1e5	114	return 0;
440e96bc MR	115	}
440e96bc MR	116
d00680ed CC	117	static int sunxi_wdt_ping(struct watchdog_device *wdt_dev)
	118	{
	119	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	120	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	121	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed	122
f2147de3	123	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
d00680ed CC	124
	125	return 0;
	126	}
	127
	128	static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
	129	unsigned int timeout)
	130	{
	131	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	132	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	133	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed CC	134	u32 reg;
	135
	136	if (wdt_timeout_map[timeout] == 0)
	137	timeout++;
	138
	139	sunxi_wdt->wdt_dev.timeout = timeout;
	140
f2147de3 CYT	141	reg = readl(wdt_base + regs->wdt_mode);
	142	reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	143	reg \|= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
	144	writel(reg, wdt_base + regs->wdt_mode);
d00680ed CC	145
	146	sunxi_wdt_ping(wdt_dev);
	147
	148	return 0;
	149	}
	150
	151	static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
	152	{
	153	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	154	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	155	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed	156
f2147de3	157	writel(0, wdt_base + regs->wdt_mode);
d00680ed CC	158
	159	return 0;
	160	}
	161
	162	static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
	163	{
	164	u32 reg;
	165	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	166	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	167	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed CC	168	int ret;
	169
	170	ret = sunxi_wdt_set_timeout(&sunxi_wdt->wdt_dev,
	171	sunxi_wdt->wdt_dev.timeout);
	172	if (ret < 0)
	173	return ret;
	174
f2147de3 CYT	175	/* Set system reset function */
	176	reg = readl(wdt_base + regs->wdt_cfg);
	177	reg &= ~(regs->wdt_reset_mask);
0919e444	178	reg \|= regs->wdt_reset_val;
f2147de3 CYT	179	writel(reg, wdt_base + regs->wdt_cfg);
	180
	181	/* Enable watchdog */
	182	reg = readl(wdt_base + regs->wdt_mode);
	183	reg \|= WDT_MODE_EN;
	184	writel(reg, wdt_base + regs->wdt_mode);
d00680ed CC	185
	186	return 0;
	187	}
	188
	189	static const struct watchdog_info sunxi_wdt_info = {
	190	.identity = DRV_NAME,
	191	.options = WDIOF_SETTIMEOUT \|
	192	WDIOF_KEEPALIVEPING \|
	193	WDIOF_MAGICCLOSE,
	194	};
	195
	196	static const struct watchdog_ops sunxi_wdt_ops = {
	197	.owner = THIS_MODULE,
	198	.start = sunxi_wdt_start,
	199	.stop = sunxi_wdt_stop,
	200	.ping = sunxi_wdt_ping,
	201	.set_timeout = sunxi_wdt_set_timeout,
0ebad1e5	202	.restart = sunxi_wdt_restart,
d00680ed CC	203	};
d00680ed CC	204
f2147de3 CYT	205	static const struct sunxi_wdt_reg sun4i_wdt_reg = {
	206	.wdt_ctrl = 0x00,
	207	.wdt_cfg = 0x04,
	208	.wdt_mode = 0x04,
	209	.wdt_timeout_shift = 3,
	210	.wdt_reset_mask = 0x02,
	211	.wdt_reset_val = 0x02,
	212	};
	213
c5ec618f CYT	214	static const struct sunxi_wdt_reg sun6i_wdt_reg = {
	215	.wdt_ctrl = 0x10,
	216	.wdt_cfg = 0x14,
	217	.wdt_mode = 0x18,
	218	.wdt_timeout_shift = 4,
	219	.wdt_reset_mask = 0x03,
	220	.wdt_reset_val = 0x01,
	221	};
	222
f2147de3 CYT	223	static const struct of_device_id sunxi_wdt_dt_ids[] = {
f2147de3 CYT	224	{ .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
c5ec618f	225	{ .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
f2147de3 CYT	226	{ /* sentinel */ }
	227	};
	228	MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
	229
1d5898b4	230	static int sunxi_wdt_probe(struct platform_device *pdev)
d00680ed	231	{
8ba41f6c	232	struct device *dev = &pdev->dev;
d00680ed	233	struct sunxi_wdt_dev *sunxi_wdt;
d00680ed CC	234	int err;
d00680ed CC	235
8ba41f6c	236	sunxi_wdt = devm_kzalloc(dev, sizeof(*sunxi_wdt), GFP_KERNEL);
d00680ed	237	if (!sunxi_wdt)
ff01cb1c	238	return -ENOMEM;
d00680ed	239
8ba41f6c	240	sunxi_wdt->wdt_regs = of_device_get_match_data(dev);
e5310371	241	if (!sunxi_wdt->wdt_regs)
f2147de3 CYT	242	return -ENODEV;
f2147de3 CYT	243
0f0a6a28	244	sunxi_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
d00680ed CC	245	if (IS_ERR(sunxi_wdt->wdt_base))
	246	return PTR_ERR(sunxi_wdt->wdt_base);
	247
	248	sunxi_wdt->wdt_dev.info = &sunxi_wdt_info;
	249	sunxi_wdt->wdt_dev.ops = &sunxi_wdt_ops;
	250	sunxi_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
	251	sunxi_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
	252	sunxi_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
8ba41f6c	253	sunxi_wdt->wdt_dev.parent = dev;
d00680ed	254
8ba41f6c	255	watchdog_init_timeout(&sunxi_wdt->wdt_dev, timeout, dev);
d00680ed	256	watchdog_set_nowayout(&sunxi_wdt->wdt_dev, nowayout);
0ebad1e5	257	watchdog_set_restart_priority(&sunxi_wdt->wdt_dev, 128);
d00680ed CC	258
	259	watchdog_set_drvdata(&sunxi_wdt->wdt_dev, sunxi_wdt);
	260
	261	sunxi_wdt_stop(&sunxi_wdt->wdt_dev);
	262
42f82693	263	watchdog_stop_on_reboot(&sunxi_wdt->wdt_dev);
8ba41f6c	264	err = devm_watchdog_register_device(dev, &sunxi_wdt->wdt_dev);
d00680ed CC	265	if (unlikely(err))
	266	return err;
	267
8ba41f6c GR	268	dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
8ba41f6c GR	269	sunxi_wdt->wdt_dev.timeout, nowayout);
d00680ed CC	270
	271	return 0;
	272	}
	273
d00680ed CC	274	static struct platform_driver sunxi_wdt_driver = {
d00680ed CC	275	.probe = sunxi_wdt_probe,
d00680ed	276	.driver = {
d00680ed	277	.name = DRV_NAME,
85eee819	278	.of_match_table = sunxi_wdt_dt_ids,
d00680ed CC	279	},
	280	};
	281
	282	module_platform_driver(sunxi_wdt_driver);
	283
	284	module_param(timeout, uint, 0);
	285	MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
	286
	287	module_param(nowayout, bool, 0);
	288	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	289	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	290
	291	MODULE_LICENSE("GPL");
	292	MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
	293	MODULE_AUTHOR("Henrik Nordstrom <henrik@henriknordstrom.net>");
	294	MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
	295	MODULE_VERSION(DRV_VERSION);