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Commit | Line | Data |
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1da177e4 | 1 | /* |
0e94f2ee VD |
2 | * w83627hf/thf WDT driver |
3 | * | |
30a83695 GR |
4 | * (c) Copyright 2013 Guenter Roeck |
5 | * converted to watchdog infrastructure | |
6 | * | |
0e94f2ee VD |
7 | * (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com> |
8 | * added support for W83627THF. | |
1da177e4 | 9 | * |
d36b6910 | 10 | * (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com> |
1da177e4 LT |
11 | * |
12 | * Based on advantechwdt.c which is based on wdt.c. | |
13 | * Original copyright messages: | |
14 | * | |
15 | * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl> | |
16 | * | |
29fa0586 AC |
17 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>, |
18 | * All Rights Reserved. | |
1da177e4 LT |
19 | * |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License | |
22 | * as published by the Free Software Foundation; either version | |
23 | * 2 of the License, or (at your option) any later version. | |
24 | * | |
25 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
26 | * warranty for any of this software. This material is provided | |
27 | * "AS-IS" and at no charge. | |
28 | * | |
29fa0586 | 29 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
30 | */ |
31 | ||
27c766aa JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/types.h> | |
1da177e4 | 37 | #include <linux/watchdog.h> |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/notifier.h> | |
40 | #include <linux/reboot.h> | |
41 | #include <linux/init.h> | |
46a3949d | 42 | #include <linux/io.h> |
1da177e4 | 43 | |
9c67bea4 | 44 | #define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT" |
1da177e4 LT |
45 | #define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */ |
46 | ||
962c04f5 | 47 | static int wdt_io; |
7b6d0b6a GR |
48 | static int cr_wdt_timeout; /* WDT timeout register */ |
49 | static int cr_wdt_control; /* WDT control register */ | |
962c04f5 | 50 | |
7b6d0b6a GR |
51 | enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf, |
52 | w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p, | |
53 | w83667hg_b, nct6775, nct6776, nct6779 }; | |
1da177e4 | 54 | |
30a83695 | 55 | static int timeout; /* in seconds */ |
1da177e4 | 56 | module_param(timeout, int, 0); |
46a3949d AC |
57 | MODULE_PARM_DESC(timeout, |
58 | "Watchdog timeout in seconds. 1 <= timeout <= 255, default=" | |
59 | __MODULE_STRING(WATCHDOG_TIMEOUT) "."); | |
1da177e4 | 60 | |
86a1e189 WVS |
61 | static bool nowayout = WATCHDOG_NOWAYOUT; |
62 | module_param(nowayout, bool, 0); | |
46a3949d AC |
63 | MODULE_PARM_DESC(nowayout, |
64 | "Watchdog cannot be stopped once started (default=" | |
65 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
1da177e4 LT |
66 | |
67 | /* | |
68 | * Kernel methods. | |
69 | */ | |
70 | ||
71 | #define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */ | |
46a3949d AC |
72 | #define WDT_EFIR (wdt_io+0) /* Extended Function Index Register |
73 | (same as EFER) */ | |
1da177e4 LT |
74 | #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */ |
75 | ||
ef0c1a6b GR |
76 | #define W83627HF_LD_WDT 0x08 |
77 | ||
962c04f5 GR |
78 | #define W83627HF_ID 0x52 |
79 | #define W83627S_ID 0x59 | |
7b6d0b6a GR |
80 | #define W83697HF_ID 0x60 |
81 | #define W83697UG_ID 0x68 | |
962c04f5 GR |
82 | #define W83637HF_ID 0x70 |
83 | #define W83627THF_ID 0x82 | |
84 | #define W83687THF_ID 0x85 | |
85 | #define W83627EHF_ID 0x88 | |
86 | #define W83627DHG_ID 0xa0 | |
87 | #define W83627UHG_ID 0xa2 | |
88 | #define W83667HG_ID 0xa5 | |
89 | #define W83627DHG_P_ID 0xb0 | |
90 | #define W83667HG_B_ID 0xb3 | |
91 | #define NCT6775_ID 0xb4 | |
92 | #define NCT6776_ID 0xc3 | |
93 | #define NCT6779_ID 0xc5 | |
94 | ||
7b6d0b6a GR |
95 | #define W83627HF_WDT_TIMEOUT 0xf6 |
96 | #define W83697HF_WDT_TIMEOUT 0xf4 | |
97 | ||
98 | #define W83627HF_WDT_CONTROL 0xf5 | |
99 | #define W83697HF_WDT_CONTROL 0xf3 | |
100 | ||
ef0c1a6b GR |
101 | static void superio_outb(int reg, int val) |
102 | { | |
103 | outb(reg, WDT_EFER); | |
104 | outb(val, WDT_EFDR); | |
105 | } | |
106 | ||
107 | static inline int superio_inb(int reg) | |
108 | { | |
109 | outb(reg, WDT_EFER); | |
110 | return inb(WDT_EFDR); | |
111 | } | |
112 | ||
113 | static int superio_enter(void) | |
1da177e4 | 114 | { |
ef0c1a6b GR |
115 | if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME)) |
116 | return -EBUSY; | |
117 | ||
1da177e4 LT |
118 | outb_p(0x87, WDT_EFER); /* Enter extended function mode */ |
119 | outb_p(0x87, WDT_EFER); /* Again according to manual */ | |
ef0c1a6b GR |
120 | |
121 | return 0; | |
1da177e4 LT |
122 | } |
123 | ||
ef0c1a6b GR |
124 | static void superio_select(int ld) |
125 | { | |
126 | superio_outb(0x07, ld); | |
127 | } | |
128 | ||
129 | static void superio_exit(void) | |
1da177e4 LT |
130 | { |
131 | outb_p(0xAA, WDT_EFER); /* Leave extended function mode */ | |
ef0c1a6b | 132 | release_region(wdt_io, 2); |
1da177e4 LT |
133 | } |
134 | ||
962c04f5 | 135 | static int w83627hf_init(struct watchdog_device *wdog, enum chips chip) |
1da177e4 | 136 | { |
ef0c1a6b | 137 | int ret; |
1da177e4 LT |
138 | unsigned char t; |
139 | ||
ef0c1a6b GR |
140 | ret = superio_enter(); |
141 | if (ret) | |
142 | return ret; | |
1da177e4 | 143 | |
ef0c1a6b | 144 | superio_select(W83627HF_LD_WDT); |
8f526389 | 145 | |
ef0c1a6b GR |
146 | /* set CR30 bit 0 to activate GPIO2 */ |
147 | t = superio_inb(0x30); | |
ac461103 | 148 | if (!(t & 0x01)) |
ef0c1a6b | 149 | superio_outb(0x30, t | 0x01); |
8f526389 | 150 | |
962c04f5 GR |
151 | switch (chip) { |
152 | case w83627hf: | |
153 | case w83627s: | |
154 | t = superio_inb(0x2B) & ~0x10; | |
155 | superio_outb(0x2B, t); /* set GPIO24 to WDT0 */ | |
156 | break; | |
7b6d0b6a GR |
157 | case w83697hf: |
158 | /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ | |
159 | t = superio_inb(0x29) & ~0x60; | |
160 | t |= 0x20; | |
161 | superio_outb(0x29, t); | |
162 | break; | |
163 | case w83697ug: | |
164 | /* Set pin 118 to WDTO# mode */ | |
165 | t = superio_inb(0x2b) & ~0x04; | |
166 | superio_outb(0x2b, t); | |
167 | break; | |
962c04f5 GR |
168 | case w83627thf: |
169 | t = (superio_inb(0x2B) & ~0x08) | 0x04; | |
170 | superio_outb(0x2B, t); /* set GPIO3 to WDT0 */ | |
171 | break; | |
172 | case w83627dhg: | |
173 | case w83627dhg_p: | |
174 | t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */ | |
175 | superio_outb(0x2D, t); /* set GPIO5 to WDT0 */ | |
7b6d0b6a | 176 | t = superio_inb(cr_wdt_control); |
962c04f5 GR |
177 | t |= 0x02; /* enable the WDTO# output low pulse |
178 | * to the KBRST# pin */ | |
7b6d0b6a | 179 | superio_outb(cr_wdt_control, t); |
962c04f5 GR |
180 | break; |
181 | case w83637hf: | |
182 | break; | |
183 | case w83687thf: | |
184 | t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */ | |
185 | superio_outb(0x2C, t); | |
186 | break; | |
187 | case w83627ehf: | |
188 | case w83627uhg: | |
189 | case w83667hg: | |
190 | case w83667hg_b: | |
191 | case nct6775: | |
192 | case nct6776: | |
193 | case nct6779: | |
194 | /* | |
195 | * These chips have a fixed WDTO# output pin (W83627UHG), | |
196 | * or support more than one WDTO# output pin. | |
197 | * Don't touch its configuration, and hope the BIOS | |
198 | * does the right thing. | |
199 | */ | |
7b6d0b6a | 200 | t = superio_inb(cr_wdt_control); |
962c04f5 GR |
201 | t |= 0x02; /* enable the WDTO# output low pulse |
202 | * to the KBRST# pin */ | |
7b6d0b6a | 203 | superio_outb(cr_wdt_control, t); |
962c04f5 GR |
204 | break; |
205 | default: | |
206 | break; | |
207 | } | |
208 | ||
7b6d0b6a | 209 | t = superio_inb(cr_wdt_timeout); |
93642ecd | 210 | if (t != 0) { |
27c766aa | 211 | pr_info("Watchdog already running. Resetting timeout to %d sec\n", |
30a83695 | 212 | wdog->timeout); |
7b6d0b6a | 213 | superio_outb(cr_wdt_timeout, wdog->timeout); |
93642ecd | 214 | } |