]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/xen/events/events_base.c
Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi...
[mirror_ubuntu-artful-kernel.git] / drivers / xen / events / events_base.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
JF
26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
JF
38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
9846ff10 42#include <asm/xen/page.h>
42a1de56 43#include <asm/xen/pci.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
SY
49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
e46cdb66
JF
52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
SY
55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
6efa20e4 59#include <xen/interface/vcpu.h>
0ec53ecf 60#include <asm/hw_irq.h>
e46cdb66 61
9a489f45
DV
62#include "events_internal.h"
63
ab9a1cca
DV
64const struct evtchn_ops *evtchn_ops;
65
e46cdb66
JF
66/*
67 * This lock protects updates to the following mapping and reference-count
68 * arrays. The lock does not need to be acquired to read the mapping tables.
69 */
77365948 70static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 71
6cb6537d
IC
72static LIST_HEAD(xen_irq_list_head);
73
e46cdb66 74/* IRQ <-> VIRQ mapping. */
204fba4a 75static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 76
f87e4cac 77/* IRQ <-> IPI mapping */
204fba4a 78static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 79
d0b075ff 80int **evtchn_to_irq;
bf86ad80 81#ifdef CONFIG_X86
9846ff10 82static unsigned long *pirq_eoi_map;
bf86ad80 83#endif
9846ff10 84static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 85
d0b075ff
DV
86#define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq)))
87#define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq)))
88#define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq))
89
e46cdb66
JF
90/* Xen will never allocate port zero for any purpose. */
91#define VALID_EVTCHN(chn) ((chn) != 0)
92
e46cdb66 93static struct irq_chip xen_dynamic_chip;
aaca4964 94static struct irq_chip xen_percpu_chip;
d46a78b0 95static struct irq_chip xen_pirq_chip;
7e186bdd
SS
96static void enable_dynirq(struct irq_data *data);
97static void disable_dynirq(struct irq_data *data);
e46cdb66 98
d0b075ff
DV
99static void clear_evtchn_to_irq_row(unsigned row)
100{
101 unsigned col;
102
103 for (col = 0; col < EVTCHN_PER_ROW; col++)
104 evtchn_to_irq[row][col] = -1;
105}
106
107static void clear_evtchn_to_irq_all(void)
108{
109 unsigned row;
110
111 for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) {
112 if (evtchn_to_irq[row] == NULL)
113 continue;
114 clear_evtchn_to_irq_row(row);
115 }
116}
117
118static int set_evtchn_to_irq(unsigned evtchn, unsigned irq)
119{
120 unsigned row;
121 unsigned col;
122
123 if (evtchn >= xen_evtchn_max_channels())
124 return -EINVAL;
125
126 row = EVTCHN_ROW(evtchn);
127 col = EVTCHN_COL(evtchn);
128
129 if (evtchn_to_irq[row] == NULL) {
130 /* Unallocated irq entries return -1 anyway */
131 if (irq == -1)
132 return 0;
133
134 evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL);
135 if (evtchn_to_irq[row] == NULL)
136 return -ENOMEM;
137
138 clear_evtchn_to_irq_row(row);
139 }
140
141 evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)] = irq;
142 return 0;
143}
144
145int get_evtchn_to_irq(unsigned evtchn)
146{
147 if (evtchn >= xen_evtchn_max_channels())
148 return -1;
149 if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL)
150 return -1;
151 return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)];
152}
153
9158c358 154/* Get info for IRQ */
9a489f45 155struct irq_info *info_for_irq(unsigned irq)
ced40d0f 156{
c442b806 157 return irq_get_handler_data(irq);
ced40d0f
JF
158}
159
9158c358 160/* Constructors for packed IRQ information. */
96d4c588 161static int xen_irq_info_common_setup(struct irq_info *info,
3d4cfa37 162 unsigned irq,
9158c358 163 enum xen_irq_type type,
d0b075ff 164 unsigned evtchn,
9158c358 165 unsigned short cpu)
ced40d0f 166{
d0b075ff 167 int ret;
9158c358
IC
168
169 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
170
171 info->type = type;
6cb6537d 172 info->irq = irq;
9158c358
IC
173 info->evtchn = evtchn;
174 info->cpu = cpu;
3d4cfa37 175
d0b075ff
DV
176 ret = set_evtchn_to_irq(evtchn, irq);
177 if (ret < 0)
178 return ret;
934f585e
JG
179
180 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
96d4c588 181
08385875 182 return xen_evtchn_port_setup(info);
ced40d0f
JF
183}
184
96d4c588 185static int xen_irq_info_evtchn_setup(unsigned irq,
d0b075ff 186 unsigned evtchn)
ced40d0f 187{
9158c358
IC
188 struct irq_info *info = info_for_irq(irq);
189
96d4c588 190 return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
191}
192
96d4c588 193static int xen_irq_info_ipi_setup(unsigned cpu,
3d4cfa37 194 unsigned irq,
d0b075ff 195 unsigned evtchn,
9158c358 196 enum ipi_vector ipi)
e46cdb66 197{
9158c358
IC
198 struct irq_info *info = info_for_irq(irq);
199
9158c358 200 info->u.ipi = ipi;
3d4cfa37
IC
201
202 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
96d4c588
DV
203
204 return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0);
ced40d0f
JF
205}
206
96d4c588 207static int xen_irq_info_virq_setup(unsigned cpu,
3d4cfa37 208 unsigned irq,
d0b075ff
DV
209 unsigned evtchn,
210 unsigned virq)
ced40d0f 211{
9158c358
IC
212 struct irq_info *info = info_for_irq(irq);
213
9158c358 214 info->u.virq = virq;
3d4cfa37
IC
215
216 per_cpu(virq_to_irq, cpu)[virq] = irq;
96d4c588
DV
217
218 return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0);
ced40d0f
JF
219}
220
96d4c588 221static int xen_irq_info_pirq_setup(unsigned irq,
d0b075ff
DV
222 unsigned evtchn,
223 unsigned pirq,
224 unsigned gsi,
beafbdc1 225 uint16_t domid,
9158c358 226 unsigned char flags)
ced40d0f 227{
9158c358
IC
228 struct irq_info *info = info_for_irq(irq);
229
9158c358
IC
230 info->u.pirq.pirq = pirq;
231 info->u.pirq.gsi = gsi;
beafbdc1 232 info->u.pirq.domid = domid;
9158c358 233 info->u.pirq.flags = flags;
96d4c588
DV
234
235 return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0);
e46cdb66
JF
236}
237
d0b075ff
DV
238static void xen_irq_info_cleanup(struct irq_info *info)
239{
240 set_evtchn_to_irq(info->evtchn, -1);
241 info->evtchn = 0;
242}
243
e46cdb66
JF
244/*
245 * Accessors for packed IRQ information.
246 */
9a489f45 247unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 248{
110e7c7e
JJ
249 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
250 return 0;
251
ced40d0f 252 return info_for_irq(irq)->evtchn;
e46cdb66
JF
253}
254
d4c04536
IC
255unsigned irq_from_evtchn(unsigned int evtchn)
256{
d0b075ff 257 return get_evtchn_to_irq(evtchn);
d4c04536
IC
258}
259EXPORT_SYMBOL_GPL(irq_from_evtchn);
260
9a489f45
DV
261int irq_from_virq(unsigned int cpu, unsigned int virq)
262{
263 return per_cpu(virq_to_irq, cpu)[virq];
264}
265
ced40d0f 266static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 267{
ced40d0f
JF
268 struct irq_info *info = info_for_irq(irq);
269
270 BUG_ON(info == NULL);
271 BUG_ON(info->type != IRQT_IPI);
272
273 return info->u.ipi;
274}
275
276static unsigned virq_from_irq(unsigned irq)
277{
278 struct irq_info *info = info_for_irq(irq);
279
280 BUG_ON(info == NULL);
281 BUG_ON(info->type != IRQT_VIRQ);
282
283 return info->u.virq;
284}
285
7a043f11
SS
286static unsigned pirq_from_irq(unsigned irq)
287{
288 struct irq_info *info = info_for_irq(irq);
289
290 BUG_ON(info == NULL);
291 BUG_ON(info->type != IRQT_PIRQ);
292
293 return info->u.pirq.pirq;
294}
295
ced40d0f
JF
296static enum xen_irq_type type_from_irq(unsigned irq)
297{
298 return info_for_irq(irq)->type;
299}
300
9a489f45 301unsigned cpu_from_irq(unsigned irq)
ced40d0f
JF
302{
303 return info_for_irq(irq)->cpu;
304}
305
9a489f45 306unsigned int cpu_from_evtchn(unsigned int evtchn)
ced40d0f 307{
d0b075ff 308 int irq = get_evtchn_to_irq(evtchn);
ced40d0f
JF
309 unsigned ret = 0;
310
311 if (irq != -1)
312 ret = cpu_from_irq(irq);
313
314 return ret;
e46cdb66
JF
315}
316
bf86ad80 317#ifdef CONFIG_X86
9846ff10 318static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 319{
521394e4 320 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 321}
bf86ad80 322#endif
d46a78b0 323
9846ff10
SS
324static bool pirq_needs_eoi_flag(unsigned irq)
325{
326 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
327 BUG_ON(info->type != IRQT_PIRQ);
328
329 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
330}
331
e46cdb66
JF
332static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
333{
d0b075ff 334 int irq = get_evtchn_to_irq(chn);
9a489f45 335 struct irq_info *info = info_for_irq(irq);
e46cdb66
JF
336
337 BUG_ON(irq == -1);
338#ifdef CONFIG_SMP
589d03e9 339 cpumask_copy(irq_get_irq_data(irq)->affinity, cpumask_of(cpu));
e46cdb66 340#endif
9a489f45 341 xen_evtchn_port_bind_to_cpu(info, cpu);
168d2f46 342
9a489f45 343 info->cpu = cpu;
3f70fa82
WL
344}
345
fd21069d
DV
346static void xen_evtchn_mask_all(void)
347{
348 unsigned int evtchn;
349
350 for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++)
351 mask_evtchn(evtchn);
352}
353
e46cdb66
JF
354/**
355 * notify_remote_via_irq - send event to remote end of event channel via irq
356 * @irq: irq of event channel to send event to
357 *
358 * Unlike notify_remote_via_evtchn(), this is safe to use across
359 * save/restore. Notifications on a broken connection are silently
360 * dropped.
361 */
362void notify_remote_via_irq(int irq)
363{
364 int evtchn = evtchn_from_irq(irq);
365
366 if (VALID_EVTCHN(evtchn))
367 notify_remote_via_evtchn(evtchn);
368}
369EXPORT_SYMBOL_GPL(notify_remote_via_irq);
370
6cb6537d
IC
371static void xen_irq_init(unsigned irq)
372{
373 struct irq_info *info;
b5328cd1 374#ifdef CONFIG_SMP
6cb6537d 375 /* By default all event channels notify CPU#0. */
589d03e9 376 cpumask_copy(irq_get_irq_data(irq)->affinity, cpumask_of(0));
44626e4a 377#endif
6cb6537d 378
ca62ce8c
IC
379 info = kzalloc(sizeof(*info), GFP_KERNEL);
380 if (info == NULL)
381 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
382
383 info->type = IRQT_UNBOUND;
420eb554 384 info->refcnt = -1;
6cb6537d 385
c442b806 386 irq_set_handler_data(irq, info);
ca62ce8c 387
6cb6537d
IC
388 list_add_tail(&info->list, &xen_irq_list_head);
389}
390
4892c9b4 391static int __must_check xen_allocate_irqs_dynamic(int nvec)
0794bfc7 392{
89911501 393 int first = 0;
4892c9b4 394 int i, irq;
0794bfc7
KRW
395
396#ifdef CONFIG_X86_IO_APIC
89911501
IC
397 /*
398 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 399 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
400 * e.g. those corresponding to event channels or MSIs
401 * etc. from the range above those "real" GSIs to avoid
402 * collisions.
403 */
404 if (xen_initial_domain() || xen_hvm_domain())
405 first = get_nr_irqs_gsi();
0794bfc7
KRW
406#endif
407
4892c9b4 408 irq = irq_alloc_descs_from(first, nvec, -1);
3a69e916 409
4892c9b4
RPM
410 if (irq >= 0) {
411 for (i = 0; i < nvec; i++)
412 xen_irq_init(irq + i);
413 }
ced40d0f 414
e46cdb66 415 return irq;
d46a78b0
JF
416}
417
4892c9b4
RPM
418static inline int __must_check xen_allocate_irq_dynamic(void)
419{
420
421 return xen_allocate_irqs_dynamic(1);
422}
423
7bee9768 424static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
425{
426 int irq;
427
89911501
IC
428 /*
429 * A PV guest has no concept of a GSI (since it has no ACPI
430 * nor access to/knowledge of the physical APICs). Therefore
431 * all IRQs are dynamically allocated from the entire IRQ
432 * space.
433 */
434 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
435 return xen_allocate_irq_dynamic();
436
437 /* Legacy IRQ descriptors are already allocated by the arch. */
438 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
439 irq = gsi;
440 else
441 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 442
6cb6537d 443 xen_irq_init(irq);
c9df1ce5
IC
444
445 return irq;
446}
447
448static void xen_free_irq(unsigned irq)
449{
c442b806 450 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 451
94032c50
KRW
452 if (WARN_ON(!info))
453 return;
454
6cb6537d 455 list_del(&info->list);
9158c358 456
c442b806 457 irq_set_handler_data(irq, NULL);
ca62ce8c 458
420eb554
DDG
459 WARN_ON(info->refcnt > 0);
460
ca62ce8c
IC
461 kfree(info);
462
72146104
IC
463 /* Legacy IRQ descriptors are managed by the arch. */
464 if (irq < NR_IRQS_LEGACY)
465 return;
466
c9df1ce5
IC
467 irq_free_desc(irq);
468}
469
d0b075ff
DV
470static void xen_evtchn_close(unsigned int port)
471{
472 struct evtchn_close close;
473
474 close.port = port;
475 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
476 BUG();
d0b075ff
DV
477}
478
d46a78b0
JF
479static void pirq_query_unmask(int irq)
480{
481 struct physdev_irq_status_query irq_status;
482 struct irq_info *info = info_for_irq(irq);
483
484 BUG_ON(info->type != IRQT_PIRQ);
485
7a043f11 486 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
487 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
488 irq_status.flags = 0;
489
490 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
491 if (irq_status.flags & XENIRQSTAT_needs_eoi)
492 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
493}
494
7e186bdd
SS
495static void eoi_pirq(struct irq_data *data)
496{
497 int evtchn = evtchn_from_irq(data->irq);
498 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
499 int rc = 0;
500
501 irq_move_irq(data);
502
503 if (VALID_EVTCHN(evtchn))
504 clear_evtchn(evtchn);
505
506 if (pirq_needs_eoi(data->irq)) {
507 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
508 WARN_ON(rc);
509 }
510}
511
512static void mask_ack_pirq(struct irq_data *data)
513{
514 disable_dynirq(data);
515 eoi_pirq(data);
516}
517
c9e265e0 518static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
519{
520 struct evtchn_bind_pirq bind_pirq;
521 struct irq_info *info = info_for_irq(irq);
522 int evtchn = evtchn_from_irq(irq);
15ebbb82 523 int rc;
d46a78b0
JF
524
525 BUG_ON(info->type != IRQT_PIRQ);
526
527 if (VALID_EVTCHN(evtchn))
528 goto out;
529
7a043f11 530 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 531 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
532 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
533 BIND_PIRQ__WILL_SHARE : 0;
534 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
535 if (rc != 0) {
02893afd 536 pr_warn("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
537 return 0;
538 }
539 evtchn = bind_pirq.port;
540
541 pirq_query_unmask(irq);
542
d0b075ff
DV
543 rc = set_evtchn_to_irq(evtchn, irq);
544 if (rc != 0) {
545 pr_err("irq%d: Failed to set port to irq mapping (%d)\n",
546 irq, rc);
547 xen_evtchn_close(evtchn);
548 return 0;
549 }
d46a78b0
JF
550 bind_evtchn_to_cpu(evtchn, 0);
551 info->evtchn = evtchn;
552
553out:
554 unmask_evtchn(evtchn);
7e186bdd 555 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
556
557 return 0;
558}
559
c9e265e0
TG
560static unsigned int startup_pirq(struct irq_data *data)
561{
562 return __startup_pirq(data->irq);
563}
564
565static void shutdown_pirq(struct irq_data *data)
d46a78b0 566{
c9e265e0 567 unsigned int irq = data->irq;
d46a78b0 568 struct irq_info *info = info_for_irq(irq);
d0b075ff 569 unsigned evtchn = evtchn_from_irq(irq);
d46a78b0
JF
570
571 BUG_ON(info->type != IRQT_PIRQ);
572
573 if (!VALID_EVTCHN(evtchn))
574 return;
575
576 mask_evtchn(evtchn);
d0b075ff
DV
577 xen_evtchn_close(evtchn);
578 xen_irq_info_cleanup(info);
d46a78b0
JF
579}
580
c9e265e0 581static void enable_pirq(struct irq_data *data)
d46a78b0 582{
c9e265e0 583 startup_pirq(data);
d46a78b0
JF
584}
585
c9e265e0 586static void disable_pirq(struct irq_data *data)
d46a78b0 587{
7e186bdd 588 disable_dynirq(data);
d46a78b0
JF
589}
590
68c2c39a 591int xen_irq_from_gsi(unsigned gsi)
d46a78b0 592{
6cb6537d 593 struct irq_info *info;
d46a78b0 594
6cb6537d
IC
595 list_for_each_entry(info, &xen_irq_list_head, list) {
596 if (info->type != IRQT_PIRQ)
d46a78b0
JF
597 continue;
598
6cb6537d
IC
599 if (info->u.pirq.gsi == gsi)
600 return info->irq;
d46a78b0
JF
601 }
602
603 return -1;
604}
68c2c39a 605EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 606
96d4c588
DV
607static void __unbind_from_irq(unsigned int irq)
608{
96d4c588
DV
609 int evtchn = evtchn_from_irq(irq);
610 struct irq_info *info = irq_get_handler_data(irq);
611
612 if (info->refcnt > 0) {
613 info->refcnt--;
614 if (info->refcnt != 0)
615 return;
616 }
617
618 if (VALID_EVTCHN(evtchn)) {
d0b075ff
DV
619 unsigned int cpu = cpu_from_irq(irq);
620
621 xen_evtchn_close(evtchn);
96d4c588
DV
622
623 switch (type_from_irq(irq)) {
624 case IRQT_VIRQ:
d0b075ff 625 per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1;
96d4c588
DV
626 break;
627 case IRQT_IPI:
d0b075ff 628 per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1;
96d4c588
DV
629 break;
630 default:
631 break;
632 }
633
d0b075ff 634 xen_irq_info_cleanup(info);
96d4c588
DV
635 }
636
637 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
638
639 xen_free_irq(irq);
640}
641
653378ac
IC
642/*
643 * Do not make any assumptions regarding the relationship between the
644 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
645 *
646 * Note: We don't assign an event channel until the irq actually started
647 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
648 *
649 * Shareable implies level triggered, not shareable implies edge
650 * triggered here.
d46a78b0 651 */
f4d0635b
IC
652int xen_bind_pirq_gsi_to_irq(unsigned gsi,
653 unsigned pirq, int shareable, char *name)
d46a78b0 654{
a0e18116 655 int irq = -1;
d46a78b0 656 struct physdev_irq irq_op;
96d4c588 657 int ret;
d46a78b0 658
77365948 659 mutex_lock(&irq_mapping_update_lock);
d46a78b0 660
68c2c39a 661 irq = xen_irq_from_gsi(gsi);
d46a78b0 662 if (irq != -1) {
283c0972
JP
663 pr_info("%s: returning irq %d for gsi %u\n",
664 __func__, irq, gsi);
420eb554 665 goto out;
d46a78b0
JF
666 }
667
c9df1ce5 668 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
669 if (irq < 0)
670 goto out;
d46a78b0 671
d46a78b0 672 irq_op.irq = irq;
b5401a96
AN
673 irq_op.vector = 0;
674
675 /* Only the privileged domain can do this. For non-priv, the pcifront
676 * driver provides a PCI bus that does the call to do exactly
677 * this in the priv domain. */
678 if (xen_initial_domain() &&
679 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 680 xen_free_irq(irq);
d46a78b0
JF
681 irq = -ENOSPC;
682 goto out;
683 }
684
96d4c588 685 ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 686 shareable ? PIRQ_SHAREABLE : 0);
96d4c588
DV
687 if (ret < 0) {
688 __unbind_from_irq(irq);
689 irq = ret;
690 goto out;
691 }
d46a78b0 692
7e186bdd
SS
693 pirq_query_unmask(irq);
694 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
695 * type of interrupt: if the interrupt is an edge triggered
696 * interrupt we use handle_edge_irq.
7e186bdd 697 *
e5ac0bda
SS
698 * On the other hand if the interrupt is level triggered we use
699 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 700 * interrupts.
e5ac0bda 701 *
7e186bdd
SS
702 * Depending on the Xen version, pirq_needs_eoi might return true
703 * not only for level triggered interrupts but for edge triggered
704 * interrupts too. In any case Xen always honors the eoi mechanism,
705 * not injecting any more pirqs of the same kind if the first one
706 * hasn't received an eoi yet. Therefore using the fasteoi handler
707 * is the right choice either way.
708 */
e5ac0bda 709 if (shareable)
7e186bdd
SS
710 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
711 handle_fasteoi_irq, name);
712 else
713 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
714 handle_edge_irq, name);
715
d46a78b0 716out:
77365948 717 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
718
719 return irq;
720}
721
f731e3ef 722#ifdef CONFIG_PCI_MSI
bf480d95 723int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 724{
5cad61a6 725 int rc;
cbf6aa89 726 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 727
bf480d95 728 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 729 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 730
5cad61a6
IC
731 WARN_ONCE(rc == -ENOSYS,
732 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
733
734 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
735}
736
bf480d95 737int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
4892c9b4 738 int pirq, int nvec, const char *name, domid_t domid)
809f9267 739{
4892c9b4 740 int i, irq, ret;
4b41df7f 741
77365948 742 mutex_lock(&irq_mapping_update_lock);
809f9267 743
4892c9b4 744 irq = xen_allocate_irqs_dynamic(nvec);
e6599225 745 if (irq < 0)
bb5d079a 746 goto out;
809f9267 747
4892c9b4
RPM
748 for (i = 0; i < nvec; i++) {
749 irq_set_chip_and_handler_name(irq + i, &xen_pirq_chip, handle_edge_irq, name);
750
751 ret = xen_irq_info_pirq_setup(irq + i, 0, pirq + i, 0, domid,
752 i == 0 ? 0 : PIRQ_MSI_GROUP);
753 if (ret < 0)
754 goto error_irq;
755 }
809f9267 756
5f6fb454 757 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
758 if (ret < 0)
759 goto error_irq;
809f9267 760out:
77365948 761 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 762 return irq;
bf480d95 763error_irq:
4892c9b4
RPM
764 for (; i >= 0; i--)
765 __unbind_from_irq(irq + i);
77365948 766 mutex_unlock(&irq_mapping_update_lock);
e6599225 767 return ret;
809f9267 768}
f731e3ef
QH
769#endif
770
b5401a96
AN
771int xen_destroy_irq(int irq)
772{
38aa66fc
JF
773 struct physdev_unmap_pirq unmap_irq;
774 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
775 int rc = -ENOENT;
776
77365948 777 mutex_lock(&irq_mapping_update_lock);
b5401a96 778
4892c9b4
RPM
779 /*
780 * If trying to remove a vector in a MSI group different
781 * than the first one skip the PIRQ unmap unless this vector
782 * is the first one in the group.
783 */
784 if (xen_initial_domain() && !(info->u.pirq.flags & PIRQ_MSI_GROUP)) {
12334715 785 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 786 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 787 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
788 /* If another domain quits without making the pci_disable_msix
789 * call, the Xen hypervisor takes care of freeing the PIRQs
790 * (free_domain_pirqs).
791 */
792 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 793 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
794 info->u.pirq.domid, info->u.pirq.pirq);
795 else if (rc) {
283c0972 796 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
797 goto out;
798 }
799 }
b5401a96 800
c9df1ce5 801 xen_free_irq(irq);
b5401a96
AN
802
803out:
77365948 804 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
805 return rc;
806}
807
af42b8d1 808int xen_irq_from_pirq(unsigned pirq)
d46a78b0 809{
69c358ce 810 int irq;
d46a78b0 811
69c358ce 812 struct irq_info *info;
e46cdb66 813
77365948 814 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
815
816 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 817 if (info->type != IRQT_PIRQ)
69c358ce
IC
818 continue;
819 irq = info->irq;
820 if (info->u.pirq.pirq == pirq)
821 goto out;
822 }
823 irq = -1;
824out:
77365948 825 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
826
827 return irq;
af42b8d1
SS
828}
829
e6197acc
KRW
830
831int xen_pirq_from_irq(unsigned irq)
832{
833 return pirq_from_irq(irq);
834}
835EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
96d4c588 836
b536b4b9 837int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
838{
839 int irq;
96d4c588 840 int ret;
e46cdb66 841
d0b075ff
DV
842 if (evtchn >= xen_evtchn_max_channels())
843 return -ENOMEM;
844
77365948 845 mutex_lock(&irq_mapping_update_lock);
e46cdb66 846
d0b075ff 847 irq = get_evtchn_to_irq(evtchn);
e46cdb66
JF
848
849 if (irq == -1) {
c9df1ce5 850 irq = xen_allocate_irq_dynamic();
68ba45ff 851 if (irq < 0)
7bee9768 852 goto out;
e46cdb66 853
c442b806 854 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 855 handle_edge_irq, "event");
e46cdb66 856
96d4c588
DV
857 ret = xen_irq_info_evtchn_setup(irq, evtchn);
858 if (ret < 0) {
859 __unbind_from_irq(irq);
860 irq = ret;
861 goto out;
862 }
97253eee
DV
863 /* New interdomain events are bound to VCPU 0. */
864 bind_evtchn_to_cpu(evtchn, 0);
5e152e6c
KRW
865 } else {
866 struct irq_info *info = info_for_irq(irq);
867 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
868 }
869
7bee9768 870out:
77365948 871 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
872
873 return irq;
874}
b536b4b9 875EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 876
f87e4cac
JF
877static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
878{
879 struct evtchn_bind_ipi bind_ipi;
880 int evtchn, irq;
96d4c588 881 int ret;
f87e4cac 882
77365948 883 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
884
885 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 886
f87e4cac 887 if (irq == -1) {
c9df1ce5 888 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
889 if (irq < 0)
890 goto out;
891
c442b806 892 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 893 handle_percpu_irq, "ipi");
f87e4cac
JF
894
895 bind_ipi.vcpu = cpu;
896 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
897 &bind_ipi) != 0)
898 BUG();
899 evtchn = bind_ipi.port;
900
96d4c588
DV
901 ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
902 if (ret < 0) {
903 __unbind_from_irq(irq);
904 irq = ret;
905 goto out;
906 }
f87e4cac 907 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
908 } else {
909 struct irq_info *info = info_for_irq(irq);
910 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
911 }
912
f87e4cac 913 out:
77365948 914 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
915 return irq;
916}
917
2e820f58
IC
918static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
919 unsigned int remote_port)
920{
921 struct evtchn_bind_interdomain bind_interdomain;
922 int err;
923
924 bind_interdomain.remote_dom = remote_domain;
925 bind_interdomain.remote_port = remote_port;
926
927 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
928 &bind_interdomain);
929
930 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
931}
932
62cc5fc7
OH
933static int find_virq(unsigned int virq, unsigned int cpu)
934{
935 struct evtchn_status status;
936 int port, rc = -ENOENT;
937
938 memset(&status, 0, sizeof(status));
d0b075ff 939 for (port = 0; port < xen_evtchn_max_channels(); port++) {
62cc5fc7
OH
940 status.dom = DOMID_SELF;
941 status.port = port;
942 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
943 if (rc < 0)
944 continue;
945 if (status.status != EVTCHNSTAT_virq)
946 continue;
947 if (status.u.virq == virq && status.vcpu == cpu) {
948 rc = port;
949 break;
950 }
951 }
952 return rc;
953}
f87e4cac 954
0dc0064a
DV
955/**
956 * xen_evtchn_nr_channels - number of usable event channel ports
957 *
958 * This may be less than the maximum supported by the current
959 * hypervisor ABI. Use xen_evtchn_max_channels() for the maximum
960 * supported.
961 */
962unsigned xen_evtchn_nr_channels(void)
963{
964 return evtchn_ops->nr_channels();
965}
966EXPORT_SYMBOL_GPL(xen_evtchn_nr_channels);
967
4fe7d5a7 968int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
969{
970 struct evtchn_bind_virq bind_virq;
62cc5fc7 971 int evtchn, irq, ret;
e46cdb66 972
77365948 973 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
974
975 irq = per_cpu(virq_to_irq, cpu)[virq];
976
977 if (irq == -1) {
c9df1ce5 978 irq = xen_allocate_irq_dynamic();
68ba45ff 979 if (irq < 0)
7bee9768 980 goto out;
a52521f1 981
c442b806 982 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
983 handle_percpu_irq, "virq");
984
e46cdb66
JF
985 bind_virq.virq = virq;
986 bind_virq.vcpu = cpu;
62cc5fc7
OH
987 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
988 &bind_virq);
989 if (ret == 0)
990 evtchn = bind_virq.port;
991 else {
992 if (ret == -EEXIST)
993 ret = find_virq(virq, cpu);
994 BUG_ON(ret < 0);
995 evtchn = ret;
996 }
e46cdb66 997
96d4c588
DV
998 ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
999 if (ret < 0) {
1000 __unbind_from_irq(irq);
1001 irq = ret;
1002 goto out;
1003 }
e46cdb66
JF
1004
1005 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
1006 } else {
1007 struct irq_info *info = info_for_irq(irq);
1008 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
1009 }
1010
7bee9768 1011out:
77365948 1012 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1013
1014 return irq;
1015}
1016
1017static void unbind_from_irq(unsigned int irq)
1018{
77365948 1019 mutex_lock(&irq_mapping_update_lock);
96d4c588 1020 __unbind_from_irq(irq);
77365948 1021 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1022}
1023
1024int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1025 irq_handler_t handler,
e46cdb66
JF
1026 unsigned long irqflags,
1027 const char *devname, void *dev_id)
1028{
361ae8cb 1029 int irq, retval;
e46cdb66
JF
1030
1031 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1032 if (irq < 0)
1033 return irq;
e46cdb66
JF
1034 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1035 if (retval != 0) {
1036 unbind_from_irq(irq);
1037 return retval;
1038 }
1039
1040 return irq;
1041}
1042EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1043
2e820f58
IC
1044int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1045 unsigned int remote_port,
1046 irq_handler_t handler,
1047 unsigned long irqflags,
1048 const char *devname,
1049 void *dev_id)
1050{
1051 int irq, retval;
1052
1053 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1054 if (irq < 0)
1055 return irq;
1056
1057 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1058 if (retval != 0) {
1059 unbind_from_irq(irq);
1060 return retval;
1061 }
1062
1063 return irq;
1064}
1065EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1066
e46cdb66 1067int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1068 irq_handler_t handler,
e46cdb66
JF
1069 unsigned long irqflags, const char *devname, void *dev_id)
1070{
361ae8cb 1071 int irq, retval;
e46cdb66
JF
1072
1073 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1074 if (irq < 0)
1075 return irq;
e46cdb66
JF
1076 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1077 if (retval != 0) {
1078 unbind_from_irq(irq);
1079 return retval;
1080 }
1081
1082 return irq;
1083}
1084EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1085
f87e4cac
JF
1086int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1087 unsigned int cpu,
1088 irq_handler_t handler,
1089 unsigned long irqflags,
1090 const char *devname,
1091 void *dev_id)
1092{
1093 int irq, retval;
1094
1095 irq = bind_ipi_to_irq(ipi, cpu);
1096 if (irq < 0)
1097 return irq;
1098
9bab0b7f 1099 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1100 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1101 if (retval != 0) {
1102 unbind_from_irq(irq);
1103 return retval;
1104 }
1105
1106 return irq;
1107}
1108
e46cdb66
JF
1109void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1110{
94032c50
KRW
1111 struct irq_info *info = irq_get_handler_data(irq);
1112
1113 if (WARN_ON(!info))
1114 return;
e46cdb66
JF
1115 free_irq(irq, dev_id);
1116 unbind_from_irq(irq);
1117}
1118EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1119
6ccecb0f
DV
1120/**
1121 * xen_set_irq_priority() - set an event channel priority.
1122 * @irq:irq bound to an event channel.
1123 * @priority: priority between XEN_IRQ_PRIORITY_MAX and XEN_IRQ_PRIORITY_MIN.
1124 */
1125int xen_set_irq_priority(unsigned irq, unsigned priority)
1126{
1127 struct evtchn_set_priority set_priority;
1128
1129 set_priority.port = evtchn_from_irq(irq);
1130 set_priority.priority = priority;
1131
1132 return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority,
1133 &set_priority);
1134}
1135EXPORT_SYMBOL_GPL(xen_set_irq_priority);
1136
420eb554
DDG
1137int evtchn_make_refcounted(unsigned int evtchn)
1138{
d0b075ff 1139 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1140 struct irq_info *info;
1141
1142 if (irq == -1)
1143 return -ENOENT;
1144
1145 info = irq_get_handler_data(irq);
1146
1147 if (!info)
1148 return -ENOENT;
1149
1150 WARN_ON(info->refcnt != -1);
1151
1152 info->refcnt = 1;
1153
1154 return 0;
1155}
1156EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1157
1158int evtchn_get(unsigned int evtchn)
1159{
1160 int irq;
1161 struct irq_info *info;
1162 int err = -ENOENT;
1163
d0b075ff 1164 if (evtchn >= xen_evtchn_max_channels())
c3b3f16d
DDG
1165 return -EINVAL;
1166
420eb554
DDG
1167 mutex_lock(&irq_mapping_update_lock);
1168
d0b075ff 1169 irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1170 if (irq == -1)
1171 goto done;
1172
1173 info = irq_get_handler_data(irq);
1174
1175 if (!info)
1176 goto done;
1177
1178 err = -EINVAL;
1179 if (info->refcnt <= 0)
1180 goto done;
1181
1182 info->refcnt++;
1183 err = 0;
1184 done:
1185 mutex_unlock(&irq_mapping_update_lock);
1186
1187 return err;
1188}
1189EXPORT_SYMBOL_GPL(evtchn_get);
1190
1191void evtchn_put(unsigned int evtchn)
1192{
d0b075ff 1193 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1194 if (WARN_ON(irq == -1))
1195 return;
1196 unbind_from_irq(irq);
1197}
1198EXPORT_SYMBOL_GPL(evtchn_put);
1199
f87e4cac
JF
1200void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1201{
6efa20e4
KRW
1202 int irq;
1203
072b2064 1204#ifdef CONFIG_X86
6efa20e4
KRW
1205 if (unlikely(vector == XEN_NMI_VECTOR)) {
1206 int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
1207 if (rc < 0)
1208 printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
1209 return;
1210 }
072b2064 1211#endif
6efa20e4 1212 irq = per_cpu(ipi_to_irq, cpu)[vector];
f87e4cac
JF
1213 BUG_ON(irq < 0);
1214 notify_remote_via_irq(irq);
1215}
1216
245b2e70
TH
1217static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1218
38e20b07 1219static void __xen_evtchn_do_upcall(void)
e46cdb66 1220{
780f36d8 1221 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
9a489f45 1222 int cpu = get_cpu();
088c05a8 1223 unsigned count;
e46cdb66 1224
229664be 1225 do {
229664be 1226 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1227
b2e4ae69 1228 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1229 goto out;
e46cdb66 1230
9a489f45 1231 xen_evtchn_handle_events(cpu);
e46cdb66 1232
229664be
JF
1233 BUG_ON(!irqs_disabled());
1234
780f36d8
CL
1235 count = __this_cpu_read(xed_nesting_count);
1236 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1237 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1238
1239out:
38e20b07
SY
1240
1241 put_cpu();
1242}
1243
1244void xen_evtchn_do_upcall(struct pt_regs *regs)
1245{
1246 struct pt_regs *old_regs = set_irq_regs(regs);
1247
772aebce 1248 irq_enter();
0ec53ecf 1249#ifdef CONFIG_X86
38e20b07 1250 exit_idle();
99c8b79d 1251 inc_irq_stat(irq_hv_callback_count);
d06eb3ee 1252#endif
38e20b07
SY
1253
1254 __xen_evtchn_do_upcall();
1255
3445a8fd
JF
1256 irq_exit();
1257 set_irq_regs(old_regs);
38e20b07 1258}
3445a8fd 1259
38e20b07
SY
1260void xen_hvm_evtchn_do_upcall(void)
1261{
1262 __xen_evtchn_do_upcall();
e46cdb66 1263}
183d03cc 1264EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1265
eb1e305f
JF
1266/* Rebind a new event channel to an existing irq. */
1267void rebind_evtchn_irq(int evtchn, int irq)
1268{
d77bbd4d
JF
1269 struct irq_info *info = info_for_irq(irq);
1270
94032c50
KRW
1271 if (WARN_ON(!info))
1272 return;
1273
eb1e305f
JF
1274 /* Make sure the irq is masked, since the new event channel
1275 will also be masked. */
1276 disable_irq(irq);
1277
77365948 1278 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1279
1280 /* After resume the irq<->evtchn mappings are all cleared out */
d0b075ff 1281 BUG_ON(get_evtchn_to_irq(evtchn) != -1);
eb1e305f 1282 /* Expect irq to have been bound before,
d77bbd4d
JF
1283 so there should be a proper type */
1284 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1285
96d4c588 1286 (void)xen_irq_info_evtchn_setup(irq, evtchn);
eb1e305f 1287
77365948 1288 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1289
1290 /* new event channels are always bound to cpu 0 */
0de26520 1291 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1292
1293 /* Unmask the event channel. */
1294 enable_irq(irq);
1295}
1296
e46cdb66 1297/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1298static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1299{
1300 struct evtchn_bind_vcpu bind_vcpu;
1301 int evtchn = evtchn_from_irq(irq);
4704fe4f 1302 int masked;
e46cdb66 1303
be49472f
IC
1304 if (!VALID_EVTCHN(evtchn))
1305 return -1;
1306
1307 /*
1308 * Events delivered via platform PCI interrupts are always
1309 * routed to vcpu 0 and hence cannot be rebound.
1310 */
1311 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1312 return -1;
e46cdb66
JF
1313
1314 /* Send future instances of this interrupt to other vcpu. */
1315 bind_vcpu.port = evtchn;
1316 bind_vcpu.vcpu = tcpu;
1317
4704fe4f
DV
1318 /*
1319 * Mask the event while changing the VCPU binding to prevent
1320 * it being delivered on an unexpected VCPU.
1321 */
3f70fa82 1322 masked = test_and_set_mask(evtchn);
4704fe4f 1323
e46cdb66
JF
1324 /*
1325 * If this fails, it usually just indicates that we're dealing with a
1326 * virq or IPI channel, which don't actually need to be rebound. Ignore
1327 * it, but don't do the xenlinux-level rebind in that case.
1328 */
1329 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1330 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1331
4704fe4f
DV
1332 if (!masked)
1333 unmask_evtchn(evtchn);
1334
d5dedd45
YL
1335 return 0;
1336}
e46cdb66 1337
c9e265e0
TG
1338static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1339 bool force)
e46cdb66 1340{
753fbd23 1341 unsigned tcpu = cpumask_first_and(dest, cpu_online_mask);
d5dedd45 1342
c9e265e0 1343 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1344}
1345
c9e265e0 1346static void enable_dynirq(struct irq_data *data)
e46cdb66 1347{
c9e265e0 1348 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1349
1350 if (VALID_EVTCHN(evtchn))
1351 unmask_evtchn(evtchn);
1352}
1353
c9e265e0 1354static void disable_dynirq(struct irq_data *data)
e46cdb66 1355{
c9e265e0 1356 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1357
1358 if (VALID_EVTCHN(evtchn))
1359 mask_evtchn(evtchn);
1360}
1361
c9e265e0 1362static void ack_dynirq(struct irq_data *data)
e46cdb66 1363{
c9e265e0 1364 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1365
7e186bdd 1366 irq_move_irq(data);
e46cdb66
JF
1367
1368 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1369 clear_evtchn(evtchn);
1370}
1371
1372static void mask_ack_dynirq(struct irq_data *data)
1373{
1374 disable_dynirq(data);
1375 ack_dynirq(data);
e46cdb66
JF
1376}
1377
c9e265e0 1378static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1379{
4640ddf5
DV
1380 unsigned int evtchn = evtchn_from_irq(data->irq);
1381 int masked;
1382
1383 if (!VALID_EVTCHN(evtchn))
1384 return 0;
1385
1386 masked = test_and_set_mask(evtchn);
1387 set_evtchn(evtchn);
1388 if (!masked)
1389 unmask_evtchn(evtchn);
1390
1391 return 1;
e46cdb66
JF
1392}
1393
0a85226f 1394static void restore_pirqs(void)
9a069c33
SS
1395{
1396 int pirq, rc, irq, gsi;
1397 struct physdev_map_pirq map_irq;
69c358ce 1398 struct irq_info *info;
9a069c33 1399
69c358ce
IC
1400 list_for_each_entry(info, &xen_irq_list_head, list) {
1401 if (info->type != IRQT_PIRQ)
9a069c33
SS
1402 continue;
1403
69c358ce
IC
1404 pirq = info->u.pirq.pirq;
1405 gsi = info->u.pirq.gsi;
1406 irq = info->irq;
1407
9a069c33
SS
1408 /* save/restore of PT devices doesn't work, so at this point the
1409 * only devices present are GSI based emulated devices */
9a069c33
SS
1410 if (!gsi)
1411 continue;
1412
1413 map_irq.domid = DOMID_SELF;
1414 map_irq.type = MAP_PIRQ_TYPE_GSI;
1415 map_irq.index = gsi;
1416 map_irq.pirq = pirq;
1417
1418 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1419 if (rc) {
283c0972
JP
1420 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1421 gsi, irq, pirq, rc);
9158c358 1422 xen_free_irq(irq);
9a069c33
SS
1423 continue;
1424 }
1425
1426 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1427
c9e265e0 1428 __startup_pirq(irq);
9a069c33
SS
1429 }
1430}
1431
0e91398f
JF
1432static void restore_cpu_virqs(unsigned int cpu)
1433{
1434 struct evtchn_bind_virq bind_virq;
1435 int virq, irq, evtchn;
1436
1437 for (virq = 0; virq < NR_VIRQS; virq++) {
1438 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1439 continue;
1440
ced40d0f 1441 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1442
1443 /* Get a new binding from Xen. */
1444 bind_virq.virq = virq;
1445 bind_virq.vcpu = cpu;
1446 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1447 &bind_virq) != 0)
1448 BUG();
1449 evtchn = bind_virq.port;
1450
1451 /* Record the new mapping. */
96d4c588 1452 (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
0e91398f 1453 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1454 }
1455}
1456
1457static void restore_cpu_ipis(unsigned int cpu)
1458{
1459 struct evtchn_bind_ipi bind_ipi;
1460 int ipi, irq, evtchn;
1461
1462 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1463 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1464 continue;
1465
ced40d0f 1466 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1467
1468 /* Get a new binding from Xen. */
1469 bind_ipi.vcpu = cpu;
1470 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1471 &bind_ipi) != 0)
1472 BUG();
1473 evtchn = bind_ipi.port;
1474
1475 /* Record the new mapping. */
96d4c588 1476 (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
0e91398f 1477 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1478 }
1479}
1480
2d9e1e2f
JF
1481/* Clear an irq's pending state, in preparation for polling on it */
1482void xen_clear_irq_pending(int irq)
1483{
1484 int evtchn = evtchn_from_irq(irq);
1485
1486 if (VALID_EVTCHN(evtchn))
1487 clear_evtchn(evtchn);
1488}
d9a8814f 1489EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1490void xen_set_irq_pending(int irq)
1491{
1492 int evtchn = evtchn_from_irq(irq);
1493
1494 if (VALID_EVTCHN(evtchn))
1495 set_evtchn(evtchn);
1496}
1497
1498bool xen_test_irq_pending(int irq)
1499{
1500 int evtchn = evtchn_from_irq(irq);
1501 bool ret = false;
1502
1503 if (VALID_EVTCHN(evtchn))
1504 ret = test_evtchn(evtchn);
1505
1506 return ret;
1507}
1508
d9a8814f
KRW
1509/* Poll waiting for an irq to become pending with timeout. In the usual case,
1510 * the irq will be disabled so it won't deliver an interrupt. */
1511void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1512{
1513 evtchn_port_t evtchn = evtchn_from_irq(irq);
1514
1515 if (VALID_EVTCHN(evtchn)) {
1516 struct sched_poll poll;
1517
1518 poll.nr_ports = 1;
d9a8814f 1519 poll.timeout = timeout;
ff3c5362 1520 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1521
1522 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1523 BUG();
1524 }
1525}
d9a8814f
KRW
1526EXPORT_SYMBOL(xen_poll_irq_timeout);
1527/* Poll waiting for an irq to become pending. In the usual case, the
1528 * irq will be disabled so it won't deliver an interrupt. */
1529void xen_poll_irq(int irq)
1530{
1531 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1532}
2d9e1e2f 1533
c7c2c3a2
KRW
1534/* Check whether the IRQ line is shared with other guests. */
1535int xen_test_irq_shared(int irq)
1536{
1537 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1538 struct physdev_irq_status_query irq_status;
1539
1540 if (WARN_ON(!info))
1541 return -ENOENT;
1542
1543 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1544
1545 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1546 return 0;
1547 return !(irq_status.flags & XENIRQSTAT_shared);
1548}
1549EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1550
0e91398f
JF
1551void xen_irq_resume(void)
1552{
fd21069d 1553 unsigned int cpu;
6cb6537d 1554 struct irq_info *info;
0e91398f 1555
0e91398f 1556 /* New event-channel space is not 'live' yet. */
fd21069d 1557 xen_evtchn_mask_all();
1fe56551 1558 xen_evtchn_resume();
0e91398f
JF
1559
1560 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1561 list_for_each_entry(info, &xen_irq_list_head, list)
1562 info->evtchn = 0; /* zap event-channel binding */
0e91398f 1563
d0b075ff 1564 clear_evtchn_to_irq_all();
0e91398f
JF
1565
1566 for_each_possible_cpu(cpu) {
1567 restore_cpu_virqs(cpu);
1568 restore_cpu_ipis(cpu);
1569 }
6903591f 1570
0a85226f 1571 restore_pirqs();
0e91398f
JF
1572}
1573
e46cdb66 1574static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1575 .name = "xen-dyn",
54a353a0 1576
c9e265e0
TG
1577 .irq_disable = disable_dynirq,
1578 .irq_mask = disable_dynirq,
1579 .irq_unmask = enable_dynirq,
54a353a0 1580
7e186bdd
SS
1581 .irq_ack = ack_dynirq,
1582 .irq_mask_ack = mask_ack_dynirq,
1583
c9e265e0
TG
1584 .irq_set_affinity = set_affinity_irq,
1585 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1586};
1587
d46a78b0 1588static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1589 .name = "xen-pirq",
d46a78b0 1590
c9e265e0
TG
1591 .irq_startup = startup_pirq,
1592 .irq_shutdown = shutdown_pirq,
c9e265e0 1593 .irq_enable = enable_pirq,
c9e265e0 1594 .irq_disable = disable_pirq,
d46a78b0 1595
7e186bdd
SS
1596 .irq_mask = disable_dynirq,
1597 .irq_unmask = enable_dynirq,
1598
1599 .irq_ack = eoi_pirq,
1600 .irq_eoi = eoi_pirq,
1601 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1602
c9e265e0 1603 .irq_set_affinity = set_affinity_irq,
d46a78b0 1604
c9e265e0 1605 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1606};
1607
aaca4964 1608static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1609 .name = "xen-percpu",
aaca4964 1610
c9e265e0
TG
1611 .irq_disable = disable_dynirq,
1612 .irq_mask = disable_dynirq,
1613 .irq_unmask = enable_dynirq,
aaca4964 1614
c9e265e0 1615 .irq_ack = ack_dynirq,
aaca4964
JF
1616};
1617
38e20b07
SY
1618int xen_set_callback_via(uint64_t via)
1619{
1620 struct xen_hvm_param a;
1621 a.domid = DOMID_SELF;
1622 a.index = HVM_PARAM_CALLBACK_IRQ;
1623 a.value = via;
1624 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1625}
1626EXPORT_SYMBOL_GPL(xen_set_callback_via);
1627
ca65f9fc 1628#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1629/* Vector callbacks are better than PCI interrupts to receive event
1630 * channel notifications because we can receive vector callbacks on any
1631 * vcpu and we don't need PCI support or APIC interactions. */
1632void xen_callback_vector(void)
1633{
1634 int rc;
1635 uint64_t callback_via;
1636 if (xen_have_vector_callback) {
bc2b0331 1637 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1638 rc = xen_set_callback_via(callback_via);
1639 if (rc) {
283c0972 1640 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1641 xen_have_vector_callback = 0;
1642 return;
1643 }
283c0972 1644 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1645 /* in the restore case the vector has already been allocated */
bc2b0331
S
1646 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1647 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1648 xen_hvm_callback_vector);
38e20b07
SY
1649 }
1650}
ca65f9fc
SS
1651#else
1652void xen_callback_vector(void) {}
1653#endif
38e20b07 1654
1fe56551
DV
1655#undef MODULE_PARAM_PREFIX
1656#define MODULE_PARAM_PREFIX "xen."
1657
1658static bool fifo_events = true;
1659module_param(fifo_events, bool, 0);
1660
2e3d8860 1661void __init xen_init_IRQ(void)
e46cdb66 1662{
1fe56551
DV
1663 int ret = -EINVAL;
1664
1665 if (fifo_events)
1666 ret = xen_evtchn_fifo_init();
1667 if (ret < 0)
1668 xen_evtchn_2l_init();
ab9a1cca 1669
d0b075ff
DV
1670 evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()),
1671 sizeof(*evtchn_to_irq), GFP_KERNEL);
9d093e29 1672 BUG_ON(!evtchn_to_irq);
e46cdb66 1673
e46cdb66 1674 /* No event channels are 'live' right now. */
fd21069d 1675 xen_evtchn_mask_all();
e46cdb66 1676
9846ff10
SS
1677 pirq_needs_eoi = pirq_needs_eoi_flag;
1678
0ec53ecf 1679#ifdef CONFIG_X86
2771374d
MR
1680 if (xen_pv_domain()) {
1681 irq_ctx_init(smp_processor_id());
1682 if (xen_initial_domain())
1683 pci_xen_initial_domain();
1684 }
1685 if (xen_feature(XENFEAT_hvm_callback_vector))
38e20b07 1686 xen_callback_vector();
2771374d
MR
1687
1688 if (xen_hvm_domain()) {
38e20b07 1689 native_init_IRQ();
3942b740
SS
1690 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1691 * __acpi_register_gsi can point at the right function */
1692 pci_xen_hvm_init();
38e20b07 1693 } else {
0ec53ecf 1694 int rc;
9846ff10
SS
1695 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1696
9846ff10
SS
1697 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1698 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1699 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
2771374d 1700 /* TODO: No PVH support for PIRQ EOI */
9846ff10
SS
1701 if (rc != 0) {
1702 free_page((unsigned long) pirq_eoi_map);
1703 pirq_eoi_map = NULL;
1704 } else
1705 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1706 }
0ec53ecf 1707#endif
e46cdb66 1708}