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xen/events: add a evtchn_op for port setup
[mirror_ubuntu-artful-kernel.git] / drivers / xen / events / events_base.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
JF
26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
JF
38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
9846ff10 42#include <asm/xen/page.h>
42a1de56 43#include <asm/xen/pci.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
SY
49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
e46cdb66
JF
52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
SY
55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
6efa20e4 59#include <xen/interface/vcpu.h>
0ec53ecf 60#include <asm/hw_irq.h>
e46cdb66 61
9a489f45
DV
62#include "events_internal.h"
63
ab9a1cca
DV
64const struct evtchn_ops *evtchn_ops;
65
e46cdb66
JF
66/*
67 * This lock protects updates to the following mapping and reference-count
68 * arrays. The lock does not need to be acquired to read the mapping tables.
69 */
77365948 70static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 71
6cb6537d
IC
72static LIST_HEAD(xen_irq_list_head);
73
e46cdb66 74/* IRQ <-> VIRQ mapping. */
204fba4a 75static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 76
f87e4cac 77/* IRQ <-> IPI mapping */
204fba4a 78static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 79
9a489f45 80int *evtchn_to_irq;
bf86ad80 81#ifdef CONFIG_X86
9846ff10 82static unsigned long *pirq_eoi_map;
bf86ad80 83#endif
9846ff10 84static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 85
e46cdb66
JF
86/* Xen will never allocate port zero for any purpose. */
87#define VALID_EVTCHN(chn) ((chn) != 0)
88
e46cdb66 89static struct irq_chip xen_dynamic_chip;
aaca4964 90static struct irq_chip xen_percpu_chip;
d46a78b0 91static struct irq_chip xen_pirq_chip;
7e186bdd
SS
92static void enable_dynirq(struct irq_data *data);
93static void disable_dynirq(struct irq_data *data);
e46cdb66 94
9158c358 95/* Get info for IRQ */
9a489f45 96struct irq_info *info_for_irq(unsigned irq)
ced40d0f 97{
c442b806 98 return irq_get_handler_data(irq);
ced40d0f
JF
99}
100
9158c358 101/* Constructors for packed IRQ information. */
96d4c588 102static int xen_irq_info_common_setup(struct irq_info *info,
3d4cfa37 103 unsigned irq,
9158c358
IC
104 enum xen_irq_type type,
105 unsigned short evtchn,
106 unsigned short cpu)
ced40d0f 107{
9158c358
IC
108
109 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
110
111 info->type = type;
6cb6537d 112 info->irq = irq;
9158c358
IC
113 info->evtchn = evtchn;
114 info->cpu = cpu;
3d4cfa37
IC
115
116 evtchn_to_irq[evtchn] = irq;
934f585e
JG
117
118 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
96d4c588 119
08385875 120 return xen_evtchn_port_setup(info);
ced40d0f
JF
121}
122
96d4c588 123static int xen_irq_info_evtchn_setup(unsigned irq,
9158c358 124 unsigned short evtchn)
ced40d0f 125{
9158c358
IC
126 struct irq_info *info = info_for_irq(irq);
127
96d4c588 128 return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
129}
130
96d4c588 131static int xen_irq_info_ipi_setup(unsigned cpu,
3d4cfa37 132 unsigned irq,
9158c358
IC
133 unsigned short evtchn,
134 enum ipi_vector ipi)
e46cdb66 135{
9158c358
IC
136 struct irq_info *info = info_for_irq(irq);
137
9158c358 138 info->u.ipi = ipi;
3d4cfa37
IC
139
140 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
96d4c588
DV
141
142 return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0);
ced40d0f
JF
143}
144
96d4c588 145static int xen_irq_info_virq_setup(unsigned cpu,
3d4cfa37 146 unsigned irq,
9158c358
IC
147 unsigned short evtchn,
148 unsigned short virq)
ced40d0f 149{
9158c358
IC
150 struct irq_info *info = info_for_irq(irq);
151
9158c358 152 info->u.virq = virq;
3d4cfa37
IC
153
154 per_cpu(virq_to_irq, cpu)[virq] = irq;
96d4c588
DV
155
156 return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0);
ced40d0f
JF
157}
158
96d4c588 159static int xen_irq_info_pirq_setup(unsigned irq,
9158c358
IC
160 unsigned short evtchn,
161 unsigned short pirq,
162 unsigned short gsi,
beafbdc1 163 uint16_t domid,
9158c358 164 unsigned char flags)
ced40d0f 165{
9158c358
IC
166 struct irq_info *info = info_for_irq(irq);
167
9158c358
IC
168 info->u.pirq.pirq = pirq;
169 info->u.pirq.gsi = gsi;
beafbdc1 170 info->u.pirq.domid = domid;
9158c358 171 info->u.pirq.flags = flags;
96d4c588
DV
172
173 return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0);
e46cdb66
JF
174}
175
176/*
177 * Accessors for packed IRQ information.
178 */
9a489f45 179unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 180{
110e7c7e
JJ
181 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
182 return 0;
183
ced40d0f 184 return info_for_irq(irq)->evtchn;
e46cdb66
JF
185}
186
d4c04536
IC
187unsigned irq_from_evtchn(unsigned int evtchn)
188{
189 return evtchn_to_irq[evtchn];
190}
191EXPORT_SYMBOL_GPL(irq_from_evtchn);
192
9a489f45
DV
193int irq_from_virq(unsigned int cpu, unsigned int virq)
194{
195 return per_cpu(virq_to_irq, cpu)[virq];
196}
197
ced40d0f 198static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 199{
ced40d0f
JF
200 struct irq_info *info = info_for_irq(irq);
201
202 BUG_ON(info == NULL);
203 BUG_ON(info->type != IRQT_IPI);
204
205 return info->u.ipi;
206}
207
208static unsigned virq_from_irq(unsigned irq)
209{
210 struct irq_info *info = info_for_irq(irq);
211
212 BUG_ON(info == NULL);
213 BUG_ON(info->type != IRQT_VIRQ);
214
215 return info->u.virq;
216}
217
7a043f11
SS
218static unsigned pirq_from_irq(unsigned irq)
219{
220 struct irq_info *info = info_for_irq(irq);
221
222 BUG_ON(info == NULL);
223 BUG_ON(info->type != IRQT_PIRQ);
224
225 return info->u.pirq.pirq;
226}
227
ced40d0f
JF
228static enum xen_irq_type type_from_irq(unsigned irq)
229{
230 return info_for_irq(irq)->type;
231}
232
9a489f45 233unsigned cpu_from_irq(unsigned irq)
ced40d0f
JF
234{
235 return info_for_irq(irq)->cpu;
236}
237
9a489f45 238unsigned int cpu_from_evtchn(unsigned int evtchn)
ced40d0f
JF
239{
240 int irq = evtchn_to_irq[evtchn];
241 unsigned ret = 0;
242
243 if (irq != -1)
244 ret = cpu_from_irq(irq);
245
246 return ret;
e46cdb66
JF
247}
248
bf86ad80 249#ifdef CONFIG_X86
9846ff10 250static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 251{
521394e4 252 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 253}
bf86ad80 254#endif
d46a78b0 255
9846ff10
SS
256static bool pirq_needs_eoi_flag(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
259 BUG_ON(info->type != IRQT_PIRQ);
260
261 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
262}
263
e46cdb66
JF
264static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
265{
266 int irq = evtchn_to_irq[chn];
9a489f45 267 struct irq_info *info = info_for_irq(irq);
e46cdb66
JF
268
269 BUG_ON(irq == -1);
270#ifdef CONFIG_SMP
c9e265e0 271 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
272#endif
273
9a489f45 274 xen_evtchn_port_bind_to_cpu(info, cpu);
168d2f46 275
9a489f45 276 info->cpu = cpu;
3f70fa82
WL
277}
278
e46cdb66
JF
279/**
280 * notify_remote_via_irq - send event to remote end of event channel via irq
281 * @irq: irq of event channel to send event to
282 *
283 * Unlike notify_remote_via_evtchn(), this is safe to use across
284 * save/restore. Notifications on a broken connection are silently
285 * dropped.
286 */
287void notify_remote_via_irq(int irq)
288{
289 int evtchn = evtchn_from_irq(irq);
290
291 if (VALID_EVTCHN(evtchn))
292 notify_remote_via_evtchn(evtchn);
293}
294EXPORT_SYMBOL_GPL(notify_remote_via_irq);
295
6cb6537d
IC
296static void xen_irq_init(unsigned irq)
297{
298 struct irq_info *info;
b5328cd1 299#ifdef CONFIG_SMP
6cb6537d
IC
300 struct irq_desc *desc = irq_to_desc(irq);
301
302 /* By default all event channels notify CPU#0. */
303 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 304#endif
6cb6537d 305
ca62ce8c
IC
306 info = kzalloc(sizeof(*info), GFP_KERNEL);
307 if (info == NULL)
308 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
309
310 info->type = IRQT_UNBOUND;
420eb554 311 info->refcnt = -1;
6cb6537d 312
c442b806 313 irq_set_handler_data(irq, info);
ca62ce8c 314
6cb6537d
IC
315 list_add_tail(&info->list, &xen_irq_list_head);
316}
317
7bee9768 318static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 319{
89911501
IC
320 int first = 0;
321 int irq;
0794bfc7
KRW
322
323#ifdef CONFIG_X86_IO_APIC
89911501
IC
324 /*
325 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 326 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
327 * e.g. those corresponding to event channels or MSIs
328 * etc. from the range above those "real" GSIs to avoid
329 * collisions.
330 */
331 if (xen_initial_domain() || xen_hvm_domain())
332 first = get_nr_irqs_gsi();
0794bfc7
KRW
333#endif
334
89911501 335 irq = irq_alloc_desc_from(first, -1);
3a69e916 336
e6599225
KRW
337 if (irq >= 0)
338 xen_irq_init(irq);
ced40d0f 339
e46cdb66 340 return irq;
d46a78b0
JF
341}
342
7bee9768 343static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
344{
345 int irq;
346
89911501
IC
347 /*
348 * A PV guest has no concept of a GSI (since it has no ACPI
349 * nor access to/knowledge of the physical APICs). Therefore
350 * all IRQs are dynamically allocated from the entire IRQ
351 * space.
352 */
353 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
354 return xen_allocate_irq_dynamic();
355
356 /* Legacy IRQ descriptors are already allocated by the arch. */
357 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
358 irq = gsi;
359 else
360 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 361
6cb6537d 362 xen_irq_init(irq);
c9df1ce5
IC
363
364 return irq;
365}
366
367static void xen_free_irq(unsigned irq)
368{
c442b806 369 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 370
94032c50
KRW
371 if (WARN_ON(!info))
372 return;
373
6cb6537d 374 list_del(&info->list);
9158c358 375
c442b806 376 irq_set_handler_data(irq, NULL);
ca62ce8c 377
420eb554
DDG
378 WARN_ON(info->refcnt > 0);
379
ca62ce8c
IC
380 kfree(info);
381
72146104
IC
382 /* Legacy IRQ descriptors are managed by the arch. */
383 if (irq < NR_IRQS_LEGACY)
384 return;
385
c9df1ce5
IC
386 irq_free_desc(irq);
387}
388
d46a78b0
JF
389static void pirq_query_unmask(int irq)
390{
391 struct physdev_irq_status_query irq_status;
392 struct irq_info *info = info_for_irq(irq);
393
394 BUG_ON(info->type != IRQT_PIRQ);
395
7a043f11 396 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
397 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
398 irq_status.flags = 0;
399
400 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
401 if (irq_status.flags & XENIRQSTAT_needs_eoi)
402 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
403}
404
405static bool probing_irq(int irq)
406{
407 struct irq_desc *desc = irq_to_desc(irq);
408
409 return desc && desc->action == NULL;
410}
411
7e186bdd
SS
412static void eoi_pirq(struct irq_data *data)
413{
414 int evtchn = evtchn_from_irq(data->irq);
415 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
416 int rc = 0;
417
418 irq_move_irq(data);
419
420 if (VALID_EVTCHN(evtchn))
421 clear_evtchn(evtchn);
422
423 if (pirq_needs_eoi(data->irq)) {
424 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
425 WARN_ON(rc);
426 }
427}
428
429static void mask_ack_pirq(struct irq_data *data)
430{
431 disable_dynirq(data);
432 eoi_pirq(data);
433}
434
c9e265e0 435static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
436{
437 struct evtchn_bind_pirq bind_pirq;
438 struct irq_info *info = info_for_irq(irq);
439 int evtchn = evtchn_from_irq(irq);
15ebbb82 440 int rc;
d46a78b0
JF
441
442 BUG_ON(info->type != IRQT_PIRQ);
443
444 if (VALID_EVTCHN(evtchn))
445 goto out;
446
7a043f11 447 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 448 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
449 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
450 BIND_PIRQ__WILL_SHARE : 0;
451 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
452 if (rc != 0) {
d46a78b0 453 if (!probing_irq(irq))
283c0972 454 pr_info("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
455 return 0;
456 }
457 evtchn = bind_pirq.port;
458
459 pirq_query_unmask(irq);
460
461 evtchn_to_irq[evtchn] = irq;
462 bind_evtchn_to_cpu(evtchn, 0);
463 info->evtchn = evtchn;
464
465out:
466 unmask_evtchn(evtchn);
7e186bdd 467 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
468
469 return 0;
470}
471
c9e265e0
TG
472static unsigned int startup_pirq(struct irq_data *data)
473{
474 return __startup_pirq(data->irq);
475}
476
477static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
478{
479 struct evtchn_close close;
c9e265e0 480 unsigned int irq = data->irq;
d46a78b0
JF
481 struct irq_info *info = info_for_irq(irq);
482 int evtchn = evtchn_from_irq(irq);
483
484 BUG_ON(info->type != IRQT_PIRQ);
485
486 if (!VALID_EVTCHN(evtchn))
487 return;
488
489 mask_evtchn(evtchn);
490
491 close.port = evtchn;
492 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
493 BUG();
494
495 bind_evtchn_to_cpu(evtchn, 0);
496 evtchn_to_irq[evtchn] = -1;
497 info->evtchn = 0;
498}
499
c9e265e0 500static void enable_pirq(struct irq_data *data)
d46a78b0 501{
c9e265e0 502 startup_pirq(data);
d46a78b0
JF
503}
504
c9e265e0 505static void disable_pirq(struct irq_data *data)
d46a78b0 506{
7e186bdd 507 disable_dynirq(data);
d46a78b0
JF
508}
509
68c2c39a 510int xen_irq_from_gsi(unsigned gsi)
d46a78b0 511{
6cb6537d 512 struct irq_info *info;
d46a78b0 513
6cb6537d
IC
514 list_for_each_entry(info, &xen_irq_list_head, list) {
515 if (info->type != IRQT_PIRQ)
d46a78b0
JF
516 continue;
517
6cb6537d
IC
518 if (info->u.pirq.gsi == gsi)
519 return info->irq;
d46a78b0
JF
520 }
521
522 return -1;
523}
68c2c39a 524EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 525
96d4c588
DV
526static void __unbind_from_irq(unsigned int irq)
527{
528 struct evtchn_close close;
529 int evtchn = evtchn_from_irq(irq);
530 struct irq_info *info = irq_get_handler_data(irq);
531
532 if (info->refcnt > 0) {
533 info->refcnt--;
534 if (info->refcnt != 0)
535 return;
536 }
537
538 if (VALID_EVTCHN(evtchn)) {
539 close.port = evtchn;
540 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
541 BUG();
542
543 switch (type_from_irq(irq)) {
544 case IRQT_VIRQ:
545 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
546 [virq_from_irq(irq)] = -1;
547 break;
548 case IRQT_IPI:
549 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
550 [ipi_from_irq(irq)] = -1;
551 break;
552 default:
553 break;
554 }
555
556 /* Closed ports are implicitly re-bound to VCPU0. */
557 bind_evtchn_to_cpu(evtchn, 0);
558
559 evtchn_to_irq[evtchn] = -1;
560 }
561
562 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
563
564 xen_free_irq(irq);
565}
566
653378ac
IC
567/*
568 * Do not make any assumptions regarding the relationship between the
569 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
570 *
571 * Note: We don't assign an event channel until the irq actually started
572 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
573 *
574 * Shareable implies level triggered, not shareable implies edge
575 * triggered here.
d46a78b0 576 */
f4d0635b
IC
577int xen_bind_pirq_gsi_to_irq(unsigned gsi,
578 unsigned pirq, int shareable, char *name)
d46a78b0 579{
a0e18116 580 int irq = -1;
d46a78b0 581 struct physdev_irq irq_op;
96d4c588 582 int ret;
d46a78b0 583
77365948 584 mutex_lock(&irq_mapping_update_lock);
d46a78b0 585
68c2c39a 586 irq = xen_irq_from_gsi(gsi);
d46a78b0 587 if (irq != -1) {
283c0972
JP
588 pr_info("%s: returning irq %d for gsi %u\n",
589 __func__, irq, gsi);
420eb554 590 goto out;
d46a78b0
JF
591 }
592
c9df1ce5 593 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
594 if (irq < 0)
595 goto out;
d46a78b0 596
d46a78b0 597 irq_op.irq = irq;
b5401a96
AN
598 irq_op.vector = 0;
599
600 /* Only the privileged domain can do this. For non-priv, the pcifront
601 * driver provides a PCI bus that does the call to do exactly
602 * this in the priv domain. */
603 if (xen_initial_domain() &&
604 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 605 xen_free_irq(irq);
d46a78b0
JF
606 irq = -ENOSPC;
607 goto out;
608 }
609
96d4c588 610 ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 611 shareable ? PIRQ_SHAREABLE : 0);
96d4c588
DV
612 if (ret < 0) {
613 __unbind_from_irq(irq);
614 irq = ret;
615 goto out;
616 }
d46a78b0 617
7e186bdd
SS
618 pirq_query_unmask(irq);
619 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
620 * type of interrupt: if the interrupt is an edge triggered
621 * interrupt we use handle_edge_irq.
7e186bdd 622 *
e5ac0bda
SS
623 * On the other hand if the interrupt is level triggered we use
624 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 625 * interrupts.
e5ac0bda 626 *
7e186bdd
SS
627 * Depending on the Xen version, pirq_needs_eoi might return true
628 * not only for level triggered interrupts but for edge triggered
629 * interrupts too. In any case Xen always honors the eoi mechanism,
630 * not injecting any more pirqs of the same kind if the first one
631 * hasn't received an eoi yet. Therefore using the fasteoi handler
632 * is the right choice either way.
633 */
e5ac0bda 634 if (shareable)
7e186bdd
SS
635 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
636 handle_fasteoi_irq, name);
637 else
638 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
639 handle_edge_irq, name);
640
d46a78b0 641out:
77365948 642 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
643
644 return irq;
645}
646
f731e3ef 647#ifdef CONFIG_PCI_MSI
bf480d95 648int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 649{
5cad61a6 650 int rc;
cbf6aa89 651 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 652
bf480d95 653 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 654 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 655
5cad61a6
IC
656 WARN_ONCE(rc == -ENOSYS,
657 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
658
659 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
660}
661
bf480d95 662int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 663 int pirq, const char *name, domid_t domid)
809f9267 664{
bf480d95 665 int irq, ret;
4b41df7f 666
77365948 667 mutex_lock(&irq_mapping_update_lock);
809f9267 668
4b41df7f 669 irq = xen_allocate_irq_dynamic();
e6599225 670 if (irq < 0)
bb5d079a 671 goto out;
809f9267 672
7e186bdd
SS
673 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
674 name);
809f9267 675
96d4c588
DV
676 ret = xen_irq_info_pirq_setup(irq, 0, pirq, 0, domid, 0);
677 if (ret < 0)
678 goto error_irq;
5f6fb454 679 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
680 if (ret < 0)
681 goto error_irq;
809f9267 682out:
77365948 683 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 684 return irq;
bf480d95 685error_irq:
96d4c588 686 __unbind_from_irq(irq);
77365948 687 mutex_unlock(&irq_mapping_update_lock);
e6599225 688 return ret;
809f9267 689}
f731e3ef
QH
690#endif
691
b5401a96
AN
692int xen_destroy_irq(int irq)
693{
694 struct irq_desc *desc;
38aa66fc
JF
695 struct physdev_unmap_pirq unmap_irq;
696 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
697 int rc = -ENOENT;
698
77365948 699 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
700
701 desc = irq_to_desc(irq);
702 if (!desc)
703 goto out;
704
38aa66fc 705 if (xen_initial_domain()) {
12334715 706 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 707 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 708 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
709 /* If another domain quits without making the pci_disable_msix
710 * call, the Xen hypervisor takes care of freeing the PIRQs
711 * (free_domain_pirqs).
712 */
713 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 714 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
715 info->u.pirq.domid, info->u.pirq.pirq);
716 else if (rc) {
283c0972 717 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
718 goto out;
719 }
720 }
b5401a96 721
c9df1ce5 722 xen_free_irq(irq);
b5401a96
AN
723
724out:
77365948 725 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
726 return rc;
727}
728
af42b8d1 729int xen_irq_from_pirq(unsigned pirq)
d46a78b0 730{
69c358ce 731 int irq;
d46a78b0 732
69c358ce 733 struct irq_info *info;
e46cdb66 734
77365948 735 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
736
737 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 738 if (info->type != IRQT_PIRQ)
69c358ce
IC
739 continue;
740 irq = info->irq;
741 if (info->u.pirq.pirq == pirq)
742 goto out;
743 }
744 irq = -1;
745out:
77365948 746 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
747
748 return irq;
af42b8d1
SS
749}
750
e6197acc
KRW
751
752int xen_pirq_from_irq(unsigned irq)
753{
754 return pirq_from_irq(irq);
755}
756EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
96d4c588 757
b536b4b9 758int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
759{
760 int irq;
96d4c588 761 int ret;
e46cdb66 762
77365948 763 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
764
765 irq = evtchn_to_irq[evtchn];
766
767 if (irq == -1) {
c9df1ce5 768 irq = xen_allocate_irq_dynamic();
68ba45ff 769 if (irq < 0)
7bee9768 770 goto out;
e46cdb66 771
c442b806 772 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 773 handle_edge_irq, "event");
e46cdb66 774
96d4c588
DV
775 ret = xen_irq_info_evtchn_setup(irq, evtchn);
776 if (ret < 0) {
777 __unbind_from_irq(irq);
778 irq = ret;
779 goto out;
780 }
5e152e6c
KRW
781 } else {
782 struct irq_info *info = info_for_irq(irq);
783 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
784 }
785
7bee9768 786out:
77365948 787 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
788
789 return irq;
790}
b536b4b9 791EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 792
f87e4cac
JF
793static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
794{
795 struct evtchn_bind_ipi bind_ipi;
796 int evtchn, irq;
96d4c588 797 int ret;
f87e4cac 798
77365948 799 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
800
801 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 802
f87e4cac 803 if (irq == -1) {
c9df1ce5 804 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
805 if (irq < 0)
806 goto out;
807
c442b806 808 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 809 handle_percpu_irq, "ipi");
f87e4cac
JF
810
811 bind_ipi.vcpu = cpu;
812 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
813 &bind_ipi) != 0)
814 BUG();
815 evtchn = bind_ipi.port;
816
96d4c588
DV
817 ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
818 if (ret < 0) {
819 __unbind_from_irq(irq);
820 irq = ret;
821 goto out;
822 }
f87e4cac 823 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
824 } else {
825 struct irq_info *info = info_for_irq(irq);
826 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
827 }
828
f87e4cac 829 out:
77365948 830 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
831 return irq;
832}
833
2e820f58
IC
834static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
835 unsigned int remote_port)
836{
837 struct evtchn_bind_interdomain bind_interdomain;
838 int err;
839
840 bind_interdomain.remote_dom = remote_domain;
841 bind_interdomain.remote_port = remote_port;
842
843 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
844 &bind_interdomain);
845
846 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
847}
848
62cc5fc7
OH
849static int find_virq(unsigned int virq, unsigned int cpu)
850{
851 struct evtchn_status status;
852 int port, rc = -ENOENT;
853
854 memset(&status, 0, sizeof(status));
855 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
856 status.dom = DOMID_SELF;
857 status.port = port;
858 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
859 if (rc < 0)
860 continue;
861 if (status.status != EVTCHNSTAT_virq)
862 continue;
863 if (status.u.virq == virq && status.vcpu == cpu) {
864 rc = port;
865 break;
866 }
867 }
868 return rc;
869}
f87e4cac 870
4fe7d5a7 871int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
872{
873 struct evtchn_bind_virq bind_virq;
62cc5fc7 874 int evtchn, irq, ret;
e46cdb66 875
77365948 876 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
877
878 irq = per_cpu(virq_to_irq, cpu)[virq];
879
880 if (irq == -1) {
c9df1ce5 881 irq = xen_allocate_irq_dynamic();
68ba45ff 882 if (irq < 0)
7bee9768 883 goto out;
a52521f1 884
c442b806 885 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
886 handle_percpu_irq, "virq");
887
e46cdb66
JF
888 bind_virq.virq = virq;
889 bind_virq.vcpu = cpu;
62cc5fc7
OH
890 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
891 &bind_virq);
892 if (ret == 0)
893 evtchn = bind_virq.port;
894 else {
895 if (ret == -EEXIST)
896 ret = find_virq(virq, cpu);
897 BUG_ON(ret < 0);
898 evtchn = ret;
899 }
e46cdb66 900
96d4c588
DV
901 ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
902 if (ret < 0) {
903 __unbind_from_irq(irq);
904 irq = ret;
905 goto out;
906 }
e46cdb66
JF
907
908 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
909 } else {
910 struct irq_info *info = info_for_irq(irq);
911 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
912 }
913
7bee9768 914out:
77365948 915 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
916
917 return irq;
918}
919
920static void unbind_from_irq(unsigned int irq)
921{
77365948 922 mutex_lock(&irq_mapping_update_lock);
96d4c588 923 __unbind_from_irq(irq);
77365948 924 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
925}
926
927int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 928 irq_handler_t handler,
e46cdb66
JF
929 unsigned long irqflags,
930 const char *devname, void *dev_id)
931{
361ae8cb 932 int irq, retval;
e46cdb66
JF
933
934 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
935 if (irq < 0)
936 return irq;
e46cdb66
JF
937 retval = request_irq(irq, handler, irqflags, devname, dev_id);
938 if (retval != 0) {
939 unbind_from_irq(irq);
940 return retval;
941 }
942
943 return irq;
944}
945EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
946
2e820f58
IC
947int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
948 unsigned int remote_port,
949 irq_handler_t handler,
950 unsigned long irqflags,
951 const char *devname,
952 void *dev_id)
953{
954 int irq, retval;
955
956 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
957 if (irq < 0)
958 return irq;
959
960 retval = request_irq(irq, handler, irqflags, devname, dev_id);
961 if (retval != 0) {
962 unbind_from_irq(irq);
963 return retval;
964 }
965
966 return irq;
967}
968EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
969
e46cdb66 970int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 971 irq_handler_t handler,
e46cdb66
JF
972 unsigned long irqflags, const char *devname, void *dev_id)
973{
361ae8cb 974 int irq, retval;
e46cdb66
JF
975
976 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
977 if (irq < 0)
978 return irq;
e46cdb66
JF
979 retval = request_irq(irq, handler, irqflags, devname, dev_id);
980 if (retval != 0) {
981 unbind_from_irq(irq);
982 return retval;
983 }
984
985 return irq;
986}
987EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
988
f87e4cac
JF
989int bind_ipi_to_irqhandler(enum ipi_vector ipi,
990 unsigned int cpu,
991 irq_handler_t handler,
992 unsigned long irqflags,
993 const char *devname,
994 void *dev_id)
995{
996 int irq, retval;
997
998 irq = bind_ipi_to_irq(ipi, cpu);
999 if (irq < 0)
1000 return irq;
1001
9bab0b7f 1002 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1003 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1004 if (retval != 0) {
1005 unbind_from_irq(irq);
1006 return retval;
1007 }
1008
1009 return irq;
1010}
1011
e46cdb66
JF
1012void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1013{
94032c50
KRW
1014 struct irq_info *info = irq_get_handler_data(irq);
1015
1016 if (WARN_ON(!info))
1017 return;
e46cdb66
JF
1018 free_irq(irq, dev_id);
1019 unbind_from_irq(irq);
1020}
1021EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1022
420eb554
DDG
1023int evtchn_make_refcounted(unsigned int evtchn)
1024{
1025 int irq = evtchn_to_irq[evtchn];
1026 struct irq_info *info;
1027
1028 if (irq == -1)
1029 return -ENOENT;
1030
1031 info = irq_get_handler_data(irq);
1032
1033 if (!info)
1034 return -ENOENT;
1035
1036 WARN_ON(info->refcnt != -1);
1037
1038 info->refcnt = 1;
1039
1040 return 0;
1041}
1042EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1043
1044int evtchn_get(unsigned int evtchn)
1045{
1046 int irq;
1047 struct irq_info *info;
1048 int err = -ENOENT;
1049
c3b3f16d
DDG
1050 if (evtchn >= NR_EVENT_CHANNELS)
1051 return -EINVAL;
1052
420eb554
DDG
1053 mutex_lock(&irq_mapping_update_lock);
1054
1055 irq = evtchn_to_irq[evtchn];
1056 if (irq == -1)
1057 goto done;
1058
1059 info = irq_get_handler_data(irq);
1060
1061 if (!info)
1062 goto done;
1063
1064 err = -EINVAL;
1065 if (info->refcnt <= 0)
1066 goto done;
1067
1068 info->refcnt++;
1069 err = 0;
1070 done:
1071 mutex_unlock(&irq_mapping_update_lock);
1072
1073 return err;
1074}
1075EXPORT_SYMBOL_GPL(evtchn_get);
1076
1077void evtchn_put(unsigned int evtchn)
1078{
1079 int irq = evtchn_to_irq[evtchn];
1080 if (WARN_ON(irq == -1))
1081 return;
1082 unbind_from_irq(irq);
1083}
1084EXPORT_SYMBOL_GPL(evtchn_put);
1085
f87e4cac
JF
1086void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1087{
6efa20e4
KRW
1088 int irq;
1089
072b2064 1090#ifdef CONFIG_X86
6efa20e4
KRW
1091 if (unlikely(vector == XEN_NMI_VECTOR)) {
1092 int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
1093 if (rc < 0)
1094 printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
1095 return;
1096 }
072b2064 1097#endif
6efa20e4 1098 irq = per_cpu(ipi_to_irq, cpu)[vector];
f87e4cac
JF
1099 BUG_ON(irq < 0);
1100 notify_remote_via_irq(irq);
1101}
1102
245b2e70
TH
1103static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1104
38e20b07 1105static void __xen_evtchn_do_upcall(void)
e46cdb66 1106{
780f36d8 1107 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
9a489f45 1108 int cpu = get_cpu();
088c05a8 1109 unsigned count;
e46cdb66 1110
229664be 1111 do {
229664be 1112 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1113
b2e4ae69 1114 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1115 goto out;
e46cdb66 1116
9a489f45 1117 xen_evtchn_handle_events(cpu);
e46cdb66 1118
229664be
JF
1119 BUG_ON(!irqs_disabled());
1120
780f36d8
CL
1121 count = __this_cpu_read(xed_nesting_count);
1122 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1123 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1124
1125out:
38e20b07
SY
1126
1127 put_cpu();
1128}
1129
1130void xen_evtchn_do_upcall(struct pt_regs *regs)
1131{
1132 struct pt_regs *old_regs = set_irq_regs(regs);
1133
772aebce 1134 irq_enter();
0ec53ecf 1135#ifdef CONFIG_X86
38e20b07 1136 exit_idle();
0ec53ecf 1137#endif
38e20b07
SY
1138
1139 __xen_evtchn_do_upcall();
1140
3445a8fd
JF
1141 irq_exit();
1142 set_irq_regs(old_regs);
38e20b07 1143}
3445a8fd 1144
38e20b07
SY
1145void xen_hvm_evtchn_do_upcall(void)
1146{
1147 __xen_evtchn_do_upcall();
e46cdb66 1148}
183d03cc 1149EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1150
eb1e305f
JF
1151/* Rebind a new event channel to an existing irq. */
1152void rebind_evtchn_irq(int evtchn, int irq)
1153{
d77bbd4d
JF
1154 struct irq_info *info = info_for_irq(irq);
1155
94032c50
KRW
1156 if (WARN_ON(!info))
1157 return;
1158
eb1e305f
JF
1159 /* Make sure the irq is masked, since the new event channel
1160 will also be masked. */
1161 disable_irq(irq);
1162
77365948 1163 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1164
1165 /* After resume the irq<->evtchn mappings are all cleared out */
1166 BUG_ON(evtchn_to_irq[evtchn] != -1);
1167 /* Expect irq to have been bound before,
d77bbd4d
JF
1168 so there should be a proper type */
1169 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1170
96d4c588 1171 (void)xen_irq_info_evtchn_setup(irq, evtchn);
eb1e305f 1172
77365948 1173 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1174
1175 /* new event channels are always bound to cpu 0 */
0de26520 1176 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1177
1178 /* Unmask the event channel. */
1179 enable_irq(irq);
1180}
1181
e46cdb66 1182/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1183static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1184{
1185 struct evtchn_bind_vcpu bind_vcpu;
1186 int evtchn = evtchn_from_irq(irq);
4704fe4f 1187 int masked;
e46cdb66 1188
be49472f
IC
1189 if (!VALID_EVTCHN(evtchn))
1190 return -1;
1191
1192 /*
1193 * Events delivered via platform PCI interrupts are always
1194 * routed to vcpu 0 and hence cannot be rebound.
1195 */
1196 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1197 return -1;
e46cdb66
JF
1198
1199 /* Send future instances of this interrupt to other vcpu. */
1200 bind_vcpu.port = evtchn;
1201 bind_vcpu.vcpu = tcpu;
1202
4704fe4f
DV
1203 /*
1204 * Mask the event while changing the VCPU binding to prevent
1205 * it being delivered on an unexpected VCPU.
1206 */
3f70fa82 1207 masked = test_and_set_mask(evtchn);
4704fe4f 1208
e46cdb66
JF
1209 /*
1210 * If this fails, it usually just indicates that we're dealing with a
1211 * virq or IPI channel, which don't actually need to be rebound. Ignore
1212 * it, but don't do the xenlinux-level rebind in that case.
1213 */
1214 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1215 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1216
4704fe4f
DV
1217 if (!masked)
1218 unmask_evtchn(evtchn);
1219
d5dedd45
YL
1220 return 0;
1221}
e46cdb66 1222
c9e265e0
TG
1223static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1224 bool force)
e46cdb66 1225{
0de26520 1226 unsigned tcpu = cpumask_first(dest);
d5dedd45 1227
c9e265e0 1228 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1229}
1230
87295185 1231static int retrigger_evtchn(int evtchn)
642e0c88 1232{
87295185 1233 int masked;
642e0c88
IY
1234
1235 if (!VALID_EVTCHN(evtchn))
87295185 1236 return 0;
642e0c88 1237
3f70fa82 1238 masked = test_and_set_mask(evtchn);
76ec8d64 1239 set_evtchn(evtchn);
642e0c88
IY
1240 if (!masked)
1241 unmask_evtchn(evtchn);
1242
1243 return 1;
1244}
1245
87295185
DV
1246int resend_irq_on_evtchn(unsigned int irq)
1247{
1248 return retrigger_evtchn(evtchn_from_irq(irq));
1249}
1250
c9e265e0 1251static void enable_dynirq(struct irq_data *data)
e46cdb66 1252{
c9e265e0 1253 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1254
1255 if (VALID_EVTCHN(evtchn))
1256 unmask_evtchn(evtchn);
1257}
1258
c9e265e0 1259static void disable_dynirq(struct irq_data *data)
e46cdb66 1260{
c9e265e0 1261 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1262
1263 if (VALID_EVTCHN(evtchn))
1264 mask_evtchn(evtchn);
1265}
1266
c9e265e0 1267static void ack_dynirq(struct irq_data *data)
e46cdb66 1268{
c9e265e0 1269 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1270
7e186bdd 1271 irq_move_irq(data);
e46cdb66
JF
1272
1273 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1274 clear_evtchn(evtchn);
1275}
1276
1277static void mask_ack_dynirq(struct irq_data *data)
1278{
1279 disable_dynirq(data);
1280 ack_dynirq(data);
e46cdb66
JF
1281}
1282
c9e265e0 1283static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1284{
87295185 1285 return retrigger_evtchn(evtchn_from_irq(data->irq));
e46cdb66
JF
1286}
1287
0a85226f 1288static void restore_pirqs(void)
9a069c33
SS
1289{
1290 int pirq, rc, irq, gsi;
1291 struct physdev_map_pirq map_irq;
69c358ce 1292 struct irq_info *info;
9a069c33 1293
69c358ce
IC
1294 list_for_each_entry(info, &xen_irq_list_head, list) {
1295 if (info->type != IRQT_PIRQ)
9a069c33
SS
1296 continue;
1297
69c358ce
IC
1298 pirq = info->u.pirq.pirq;
1299 gsi = info->u.pirq.gsi;
1300 irq = info->irq;
1301
9a069c33
SS
1302 /* save/restore of PT devices doesn't work, so at this point the
1303 * only devices present are GSI based emulated devices */
9a069c33
SS
1304 if (!gsi)
1305 continue;
1306
1307 map_irq.domid = DOMID_SELF;
1308 map_irq.type = MAP_PIRQ_TYPE_GSI;
1309 map_irq.index = gsi;
1310 map_irq.pirq = pirq;
1311
1312 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1313 if (rc) {
283c0972
JP
1314 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1315 gsi, irq, pirq, rc);
9158c358 1316 xen_free_irq(irq);
9a069c33
SS
1317 continue;
1318 }
1319
1320 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1321
c9e265e0 1322 __startup_pirq(irq);
9a069c33
SS
1323 }
1324}
1325
0e91398f
JF
1326static void restore_cpu_virqs(unsigned int cpu)
1327{
1328 struct evtchn_bind_virq bind_virq;
1329 int virq, irq, evtchn;
1330
1331 for (virq = 0; virq < NR_VIRQS; virq++) {
1332 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1333 continue;
1334
ced40d0f 1335 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1336
1337 /* Get a new binding from Xen. */
1338 bind_virq.virq = virq;
1339 bind_virq.vcpu = cpu;
1340 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1341 &bind_virq) != 0)
1342 BUG();
1343 evtchn = bind_virq.port;
1344
1345 /* Record the new mapping. */
96d4c588 1346 (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
0e91398f 1347 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1348 }
1349}
1350
1351static void restore_cpu_ipis(unsigned int cpu)
1352{
1353 struct evtchn_bind_ipi bind_ipi;
1354 int ipi, irq, evtchn;
1355
1356 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1357 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1358 continue;
1359
ced40d0f 1360 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1361
1362 /* Get a new binding from Xen. */
1363 bind_ipi.vcpu = cpu;
1364 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1365 &bind_ipi) != 0)
1366 BUG();
1367 evtchn = bind_ipi.port;
1368
1369 /* Record the new mapping. */
96d4c588 1370 (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
0e91398f 1371 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1372 }
1373}
1374
2d9e1e2f
JF
1375/* Clear an irq's pending state, in preparation for polling on it */
1376void xen_clear_irq_pending(int irq)
1377{
1378 int evtchn = evtchn_from_irq(irq);
1379
1380 if (VALID_EVTCHN(evtchn))
1381 clear_evtchn(evtchn);
1382}
d9a8814f 1383EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1384void xen_set_irq_pending(int irq)
1385{
1386 int evtchn = evtchn_from_irq(irq);
1387
1388 if (VALID_EVTCHN(evtchn))
1389 set_evtchn(evtchn);
1390}
1391
1392bool xen_test_irq_pending(int irq)
1393{
1394 int evtchn = evtchn_from_irq(irq);
1395 bool ret = false;
1396
1397 if (VALID_EVTCHN(evtchn))
1398 ret = test_evtchn(evtchn);
1399
1400 return ret;
1401}
1402
d9a8814f
KRW
1403/* Poll waiting for an irq to become pending with timeout. In the usual case,
1404 * the irq will be disabled so it won't deliver an interrupt. */
1405void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1406{
1407 evtchn_port_t evtchn = evtchn_from_irq(irq);
1408
1409 if (VALID_EVTCHN(evtchn)) {
1410 struct sched_poll poll;
1411
1412 poll.nr_ports = 1;
d9a8814f 1413 poll.timeout = timeout;
ff3c5362 1414 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1415
1416 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1417 BUG();
1418 }
1419}
d9a8814f
KRW
1420EXPORT_SYMBOL(xen_poll_irq_timeout);
1421/* Poll waiting for an irq to become pending. In the usual case, the
1422 * irq will be disabled so it won't deliver an interrupt. */
1423void xen_poll_irq(int irq)
1424{
1425 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1426}
2d9e1e2f 1427
c7c2c3a2
KRW
1428/* Check whether the IRQ line is shared with other guests. */
1429int xen_test_irq_shared(int irq)
1430{
1431 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1432 struct physdev_irq_status_query irq_status;
1433
1434 if (WARN_ON(!info))
1435 return -ENOENT;
1436
1437 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1438
1439 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1440 return 0;
1441 return !(irq_status.flags & XENIRQSTAT_shared);
1442}
1443EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1444
0e91398f
JF
1445void xen_irq_resume(void)
1446{
6cb6537d
IC
1447 unsigned int cpu, evtchn;
1448 struct irq_info *info;
0e91398f 1449
0e91398f
JF
1450 /* New event-channel space is not 'live' yet. */
1451 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1452 mask_evtchn(evtchn);
1453
1454 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1455 list_for_each_entry(info, &xen_irq_list_head, list)
1456 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1457
1458 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1459 evtchn_to_irq[evtchn] = -1;
1460
1461 for_each_possible_cpu(cpu) {
1462 restore_cpu_virqs(cpu);
1463 restore_cpu_ipis(cpu);
1464 }
6903591f 1465
0a85226f 1466 restore_pirqs();
0e91398f
JF
1467}
1468
e46cdb66 1469static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1470 .name = "xen-dyn",
54a353a0 1471
c9e265e0
TG
1472 .irq_disable = disable_dynirq,
1473 .irq_mask = disable_dynirq,
1474 .irq_unmask = enable_dynirq,
54a353a0 1475
7e186bdd
SS
1476 .irq_ack = ack_dynirq,
1477 .irq_mask_ack = mask_ack_dynirq,
1478
c9e265e0
TG
1479 .irq_set_affinity = set_affinity_irq,
1480 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1481};
1482
d46a78b0 1483static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1484 .name = "xen-pirq",
d46a78b0 1485
c9e265e0
TG
1486 .irq_startup = startup_pirq,
1487 .irq_shutdown = shutdown_pirq,
c9e265e0 1488 .irq_enable = enable_pirq,
c9e265e0 1489 .irq_disable = disable_pirq,
d46a78b0 1490
7e186bdd
SS
1491 .irq_mask = disable_dynirq,
1492 .irq_unmask = enable_dynirq,
1493
1494 .irq_ack = eoi_pirq,
1495 .irq_eoi = eoi_pirq,
1496 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1497
c9e265e0 1498 .irq_set_affinity = set_affinity_irq,
d46a78b0 1499
c9e265e0 1500 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1501};
1502
aaca4964 1503static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1504 .name = "xen-percpu",
aaca4964 1505
c9e265e0
TG
1506 .irq_disable = disable_dynirq,
1507 .irq_mask = disable_dynirq,
1508 .irq_unmask = enable_dynirq,
aaca4964 1509
c9e265e0 1510 .irq_ack = ack_dynirq,
aaca4964
JF
1511};
1512
38e20b07
SY
1513int xen_set_callback_via(uint64_t via)
1514{
1515 struct xen_hvm_param a;
1516 a.domid = DOMID_SELF;
1517 a.index = HVM_PARAM_CALLBACK_IRQ;
1518 a.value = via;
1519 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1520}
1521EXPORT_SYMBOL_GPL(xen_set_callback_via);
1522
ca65f9fc 1523#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1524/* Vector callbacks are better than PCI interrupts to receive event
1525 * channel notifications because we can receive vector callbacks on any
1526 * vcpu and we don't need PCI support or APIC interactions. */
1527void xen_callback_vector(void)
1528{
1529 int rc;
1530 uint64_t callback_via;
1531 if (xen_have_vector_callback) {
bc2b0331 1532 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1533 rc = xen_set_callback_via(callback_via);
1534 if (rc) {
283c0972 1535 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1536 xen_have_vector_callback = 0;
1537 return;
1538 }
283c0972 1539 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1540 /* in the restore case the vector has already been allocated */
bc2b0331
S
1541 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1542 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1543 xen_hvm_callback_vector);
38e20b07
SY
1544 }
1545}
ca65f9fc
SS
1546#else
1547void xen_callback_vector(void) {}
1548#endif
38e20b07 1549
2e3d8860 1550void __init xen_init_IRQ(void)
e46cdb66 1551{
0ec53ecf 1552 int i;
c7a3589e 1553
ab9a1cca
DV
1554 xen_evtchn_2l_init();
1555
b21ddbf5
JF
1556 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1557 GFP_KERNEL);
9d093e29 1558 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1559 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1560 evtchn_to_irq[i] = -1;
e46cdb66 1561
e46cdb66
JF
1562 /* No event channels are 'live' right now. */
1563 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1564 mask_evtchn(i);
1565
9846ff10
SS
1566 pirq_needs_eoi = pirq_needs_eoi_flag;
1567
0ec53ecf 1568#ifdef CONFIG_X86
38e20b07
SY
1569 if (xen_hvm_domain()) {
1570 xen_callback_vector();
1571 native_init_IRQ();
3942b740
SS
1572 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1573 * __acpi_register_gsi can point at the right function */
1574 pci_xen_hvm_init();
38e20b07 1575 } else {
0ec53ecf 1576 int rc;
9846ff10
SS
1577 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1578
38e20b07 1579 irq_ctx_init(smp_processor_id());
38aa66fc 1580 if (xen_initial_domain())
a0ee0567 1581 pci_xen_initial_domain();
9846ff10
SS
1582
1583 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1584 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1585 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1586 if (rc != 0) {
1587 free_page((unsigned long) pirq_eoi_map);
1588 pirq_eoi_map = NULL;
1589 } else
1590 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1591 }
0ec53ecf 1592#endif
e46cdb66 1593}