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[mirror_ubuntu-artful-kernel.git] / drivers / xen / events / events_base.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
JF
26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
JF
38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
42a1de56 42#include <asm/xen/pci.h>
a9fd60e2 43#include <xen/page.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
SY
49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
e46cdb66
JF
52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
SY
55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
6efa20e4 59#include <xen/interface/vcpu.h>
0ec53ecf 60#include <asm/hw_irq.h>
e46cdb66 61
9a489f45
DV
62#include "events_internal.h"
63
ab9a1cca
DV
64const struct evtchn_ops *evtchn_ops;
65
e46cdb66
JF
66/*
67 * This lock protects updates to the following mapping and reference-count
68 * arrays. The lock does not need to be acquired to read the mapping tables.
69 */
77365948 70static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 71
6cb6537d
IC
72static LIST_HEAD(xen_irq_list_head);
73
e46cdb66 74/* IRQ <-> VIRQ mapping. */
204fba4a 75static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 76
f87e4cac 77/* IRQ <-> IPI mapping */
204fba4a 78static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 79
d0b075ff 80int **evtchn_to_irq;
bf86ad80 81#ifdef CONFIG_X86
9846ff10 82static unsigned long *pirq_eoi_map;
bf86ad80 83#endif
9846ff10 84static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 85
d0b075ff
DV
86#define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq)))
87#define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq)))
88#define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq))
89
e46cdb66
JF
90/* Xen will never allocate port zero for any purpose. */
91#define VALID_EVTCHN(chn) ((chn) != 0)
92
e46cdb66 93static struct irq_chip xen_dynamic_chip;
aaca4964 94static struct irq_chip xen_percpu_chip;
d46a78b0 95static struct irq_chip xen_pirq_chip;
7e186bdd
SS
96static void enable_dynirq(struct irq_data *data);
97static void disable_dynirq(struct irq_data *data);
e46cdb66 98
d0b075ff
DV
99static void clear_evtchn_to_irq_row(unsigned row)
100{
101 unsigned col;
102
103 for (col = 0; col < EVTCHN_PER_ROW; col++)
104 evtchn_to_irq[row][col] = -1;
105}
106
107static void clear_evtchn_to_irq_all(void)
108{
109 unsigned row;
110
111 for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) {
112 if (evtchn_to_irq[row] == NULL)
113 continue;
114 clear_evtchn_to_irq_row(row);
115 }
116}
117
118static int set_evtchn_to_irq(unsigned evtchn, unsigned irq)
119{
120 unsigned row;
121 unsigned col;
122
123 if (evtchn >= xen_evtchn_max_channels())
124 return -EINVAL;
125
126 row = EVTCHN_ROW(evtchn);
127 col = EVTCHN_COL(evtchn);
128
129 if (evtchn_to_irq[row] == NULL) {
130 /* Unallocated irq entries return -1 anyway */
131 if (irq == -1)
132 return 0;
133
134 evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL);
135 if (evtchn_to_irq[row] == NULL)
136 return -ENOMEM;
137
138 clear_evtchn_to_irq_row(row);
139 }
140
141 evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)] = irq;
142 return 0;
143}
144
145int get_evtchn_to_irq(unsigned evtchn)
146{
147 if (evtchn >= xen_evtchn_max_channels())
148 return -1;
149 if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL)
150 return -1;
151 return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)];
152}
153
9158c358 154/* Get info for IRQ */
9a489f45 155struct irq_info *info_for_irq(unsigned irq)
ced40d0f 156{
c442b806 157 return irq_get_handler_data(irq);
ced40d0f
JF
158}
159
9158c358 160/* Constructors for packed IRQ information. */
96d4c588 161static int xen_irq_info_common_setup(struct irq_info *info,
3d4cfa37 162 unsigned irq,
9158c358 163 enum xen_irq_type type,
d0b075ff 164 unsigned evtchn,
9158c358 165 unsigned short cpu)
ced40d0f 166{
d0b075ff 167 int ret;
9158c358
IC
168
169 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
170
171 info->type = type;
6cb6537d 172 info->irq = irq;
9158c358
IC
173 info->evtchn = evtchn;
174 info->cpu = cpu;
3d4cfa37 175
d0b075ff
DV
176 ret = set_evtchn_to_irq(evtchn, irq);
177 if (ret < 0)
178 return ret;
934f585e
JG
179
180 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
96d4c588 181
08385875 182 return xen_evtchn_port_setup(info);
ced40d0f
JF
183}
184
96d4c588 185static int xen_irq_info_evtchn_setup(unsigned irq,
d0b075ff 186 unsigned evtchn)
ced40d0f 187{
9158c358
IC
188 struct irq_info *info = info_for_irq(irq);
189
96d4c588 190 return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
191}
192
96d4c588 193static int xen_irq_info_ipi_setup(unsigned cpu,
3d4cfa37 194 unsigned irq,
d0b075ff 195 unsigned evtchn,
9158c358 196 enum ipi_vector ipi)
e46cdb66 197{
9158c358
IC
198 struct irq_info *info = info_for_irq(irq);
199
9158c358 200 info->u.ipi = ipi;
3d4cfa37
IC
201
202 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
96d4c588
DV
203
204 return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0);
ced40d0f
JF
205}
206
96d4c588 207static int xen_irq_info_virq_setup(unsigned cpu,
3d4cfa37 208 unsigned irq,
d0b075ff
DV
209 unsigned evtchn,
210 unsigned virq)
ced40d0f 211{
9158c358
IC
212 struct irq_info *info = info_for_irq(irq);
213
9158c358 214 info->u.virq = virq;
3d4cfa37
IC
215
216 per_cpu(virq_to_irq, cpu)[virq] = irq;
96d4c588
DV
217
218 return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0);
ced40d0f
JF
219}
220
96d4c588 221static int xen_irq_info_pirq_setup(unsigned irq,
d0b075ff
DV
222 unsigned evtchn,
223 unsigned pirq,
224 unsigned gsi,
beafbdc1 225 uint16_t domid,
9158c358 226 unsigned char flags)
ced40d0f 227{
9158c358
IC
228 struct irq_info *info = info_for_irq(irq);
229
9158c358
IC
230 info->u.pirq.pirq = pirq;
231 info->u.pirq.gsi = gsi;
beafbdc1 232 info->u.pirq.domid = domid;
9158c358 233 info->u.pirq.flags = flags;
96d4c588
DV
234
235 return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0);
e46cdb66
JF
236}
237
d0b075ff
DV
238static void xen_irq_info_cleanup(struct irq_info *info)
239{
240 set_evtchn_to_irq(info->evtchn, -1);
241 info->evtchn = 0;
242}
243
e46cdb66
JF
244/*
245 * Accessors for packed IRQ information.
246 */
9a489f45 247unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 248{
474b8fea 249 if (unlikely(WARN(irq >= nr_irqs, "Invalid irq %d!\n", irq)))
110e7c7e
JJ
250 return 0;
251
ced40d0f 252 return info_for_irq(irq)->evtchn;
e46cdb66
JF
253}
254
d4c04536
IC
255unsigned irq_from_evtchn(unsigned int evtchn)
256{
d0b075ff 257 return get_evtchn_to_irq(evtchn);
d4c04536
IC
258}
259EXPORT_SYMBOL_GPL(irq_from_evtchn);
260
9a489f45
DV
261int irq_from_virq(unsigned int cpu, unsigned int virq)
262{
263 return per_cpu(virq_to_irq, cpu)[virq];
264}
265
ced40d0f 266static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 267{
ced40d0f
JF
268 struct irq_info *info = info_for_irq(irq);
269
270 BUG_ON(info == NULL);
271 BUG_ON(info->type != IRQT_IPI);
272
273 return info->u.ipi;
274}
275
276static unsigned virq_from_irq(unsigned irq)
277{
278 struct irq_info *info = info_for_irq(irq);
279
280 BUG_ON(info == NULL);
281 BUG_ON(info->type != IRQT_VIRQ);
282
283 return info->u.virq;
284}
285
7a043f11
SS
286static unsigned pirq_from_irq(unsigned irq)
287{
288 struct irq_info *info = info_for_irq(irq);
289
290 BUG_ON(info == NULL);
291 BUG_ON(info->type != IRQT_PIRQ);
292
293 return info->u.pirq.pirq;
294}
295
ced40d0f
JF
296static enum xen_irq_type type_from_irq(unsigned irq)
297{
298 return info_for_irq(irq)->type;
299}
300
9a489f45 301unsigned cpu_from_irq(unsigned irq)
ced40d0f
JF
302{
303 return info_for_irq(irq)->cpu;
304}
305
9a489f45 306unsigned int cpu_from_evtchn(unsigned int evtchn)
ced40d0f 307{
d0b075ff 308 int irq = get_evtchn_to_irq(evtchn);
ced40d0f
JF
309 unsigned ret = 0;
310
311 if (irq != -1)
312 ret = cpu_from_irq(irq);
313
314 return ret;
e46cdb66
JF
315}
316
bf86ad80 317#ifdef CONFIG_X86
9846ff10 318static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 319{
521394e4 320 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 321}
bf86ad80 322#endif
d46a78b0 323
9846ff10
SS
324static bool pirq_needs_eoi_flag(unsigned irq)
325{
326 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
327 BUG_ON(info->type != IRQT_PIRQ);
328
329 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
330}
331
e46cdb66
JF
332static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
333{
d0b075ff 334 int irq = get_evtchn_to_irq(chn);
9a489f45 335 struct irq_info *info = info_for_irq(irq);
e46cdb66
JF
336
337 BUG_ON(irq == -1);
338#ifdef CONFIG_SMP
c149e4cd 339 cpumask_copy(irq_get_affinity_mask(irq), cpumask_of(cpu));
e46cdb66 340#endif
9a489f45 341 xen_evtchn_port_bind_to_cpu(info, cpu);
168d2f46 342
9a489f45 343 info->cpu = cpu;
3f70fa82
WL
344}
345
fd21069d
DV
346static void xen_evtchn_mask_all(void)
347{
348 unsigned int evtchn;
349
350 for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++)
351 mask_evtchn(evtchn);
352}
353
e46cdb66
JF
354/**
355 * notify_remote_via_irq - send event to remote end of event channel via irq
356 * @irq: irq of event channel to send event to
357 *
358 * Unlike notify_remote_via_evtchn(), this is safe to use across
359 * save/restore. Notifications on a broken connection are silently
360 * dropped.
361 */
362void notify_remote_via_irq(int irq)
363{
364 int evtchn = evtchn_from_irq(irq);
365
366 if (VALID_EVTCHN(evtchn))
367 notify_remote_via_evtchn(evtchn);
368}
369EXPORT_SYMBOL_GPL(notify_remote_via_irq);
370
6cb6537d
IC
371static void xen_irq_init(unsigned irq)
372{
373 struct irq_info *info;
b5328cd1 374#ifdef CONFIG_SMP
6cb6537d 375 /* By default all event channels notify CPU#0. */
c149e4cd 376 cpumask_copy(irq_get_affinity_mask(irq), cpumask_of(0));
44626e4a 377#endif
6cb6537d 378
ca62ce8c
IC
379 info = kzalloc(sizeof(*info), GFP_KERNEL);
380 if (info == NULL)
381 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
382
383 info->type = IRQT_UNBOUND;
420eb554 384 info->refcnt = -1;
6cb6537d 385
c442b806 386 irq_set_handler_data(irq, info);
ca62ce8c 387
6cb6537d
IC
388 list_add_tail(&info->list, &xen_irq_list_head);
389}
390
4892c9b4 391static int __must_check xen_allocate_irqs_dynamic(int nvec)
0794bfc7 392{
d07c9f18 393 int i, irq = irq_alloc_descs(-1, 0, nvec, -1);
3a69e916 394
4892c9b4
RPM
395 if (irq >= 0) {
396 for (i = 0; i < nvec; i++)
397 xen_irq_init(irq + i);
398 }
ced40d0f 399
e46cdb66 400 return irq;
d46a78b0
JF
401}
402
4892c9b4
RPM
403static inline int __must_check xen_allocate_irq_dynamic(void)
404{
405
406 return xen_allocate_irqs_dynamic(1);
407}
408
7bee9768 409static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
410{
411 int irq;
412
89911501
IC
413 /*
414 * A PV guest has no concept of a GSI (since it has no ACPI
415 * nor access to/knowledge of the physical APICs). Therefore
416 * all IRQs are dynamically allocated from the entire IRQ
417 * space.
418 */
419 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
420 return xen_allocate_irq_dynamic();
421
422 /* Legacy IRQ descriptors are already allocated by the arch. */
423 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
424 irq = gsi;
425 else
426 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 427
6cb6537d 428 xen_irq_init(irq);
c9df1ce5
IC
429
430 return irq;
431}
432
433static void xen_free_irq(unsigned irq)
434{
c442b806 435 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 436
94032c50
KRW
437 if (WARN_ON(!info))
438 return;
439
6cb6537d 440 list_del(&info->list);
9158c358 441
c442b806 442 irq_set_handler_data(irq, NULL);
ca62ce8c 443
420eb554
DDG
444 WARN_ON(info->refcnt > 0);
445
ca62ce8c
IC
446 kfree(info);
447
72146104
IC
448 /* Legacy IRQ descriptors are managed by the arch. */
449 if (irq < NR_IRQS_LEGACY)
450 return;
451
c9df1ce5
IC
452 irq_free_desc(irq);
453}
454
d0b075ff
DV
455static void xen_evtchn_close(unsigned int port)
456{
457 struct evtchn_close close;
458
459 close.port = port;
460 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
461 BUG();
d0b075ff
DV
462}
463
d46a78b0
JF
464static void pirq_query_unmask(int irq)
465{
466 struct physdev_irq_status_query irq_status;
467 struct irq_info *info = info_for_irq(irq);
468
469 BUG_ON(info->type != IRQT_PIRQ);
470
7a043f11 471 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
472 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
473 irq_status.flags = 0;
474
475 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
476 if (irq_status.flags & XENIRQSTAT_needs_eoi)
477 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
478}
479
7e186bdd
SS
480static void eoi_pirq(struct irq_data *data)
481{
482 int evtchn = evtchn_from_irq(data->irq);
483 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
484 int rc = 0;
485
486 irq_move_irq(data);
487
488 if (VALID_EVTCHN(evtchn))
489 clear_evtchn(evtchn);
490
491 if (pirq_needs_eoi(data->irq)) {
492 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
493 WARN_ON(rc);
494 }
495}
496
497static void mask_ack_pirq(struct irq_data *data)
498{
499 disable_dynirq(data);
500 eoi_pirq(data);
501}
502
c9e265e0 503static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
504{
505 struct evtchn_bind_pirq bind_pirq;
506 struct irq_info *info = info_for_irq(irq);
507 int evtchn = evtchn_from_irq(irq);
15ebbb82 508 int rc;
d46a78b0
JF
509
510 BUG_ON(info->type != IRQT_PIRQ);
511
512 if (VALID_EVTCHN(evtchn))
513 goto out;
514
7a043f11 515 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 516 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
517 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
518 BIND_PIRQ__WILL_SHARE : 0;
519 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
520 if (rc != 0) {
02893afd 521 pr_warn("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
522 return 0;
523 }
524 evtchn = bind_pirq.port;
525
526 pirq_query_unmask(irq);
527
d0b075ff 528 rc = set_evtchn_to_irq(evtchn, irq);
85e40b05
JG
529 if (rc)
530 goto err;
531
d46a78b0 532 info->evtchn = evtchn;
16e6bd59 533 bind_evtchn_to_cpu(evtchn, 0);
d46a78b0 534
85e40b05
JG
535 rc = xen_evtchn_port_setup(info);
536 if (rc)
537 goto err;
538
d46a78b0
JF
539out:
540 unmask_evtchn(evtchn);
7e186bdd 541 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
542
543 return 0;
85e40b05
JG
544
545err:
546 pr_err("irq%d: Failed to set port to irq mapping (%d)\n", irq, rc);
547 xen_evtchn_close(evtchn);
548 return 0;
d46a78b0
JF
549}
550
c9e265e0
TG
551static unsigned int startup_pirq(struct irq_data *data)
552{
553 return __startup_pirq(data->irq);
554}
555
556static void shutdown_pirq(struct irq_data *data)
d46a78b0 557{
c9e265e0 558 unsigned int irq = data->irq;
d46a78b0 559 struct irq_info *info = info_for_irq(irq);
d0b075ff 560 unsigned evtchn = evtchn_from_irq(irq);
d46a78b0
JF
561
562 BUG_ON(info->type != IRQT_PIRQ);
563
564 if (!VALID_EVTCHN(evtchn))
565 return;
566
567 mask_evtchn(evtchn);
d0b075ff
DV
568 xen_evtchn_close(evtchn);
569 xen_irq_info_cleanup(info);
d46a78b0
JF
570}
571
c9e265e0 572static void enable_pirq(struct irq_data *data)
d46a78b0 573{
c9e265e0 574 startup_pirq(data);
d46a78b0
JF
575}
576
c9e265e0 577static void disable_pirq(struct irq_data *data)
d46a78b0 578{
7e186bdd 579 disable_dynirq(data);
d46a78b0
JF
580}
581
68c2c39a 582int xen_irq_from_gsi(unsigned gsi)
d46a78b0 583{
6cb6537d 584 struct irq_info *info;
d46a78b0 585
6cb6537d
IC
586 list_for_each_entry(info, &xen_irq_list_head, list) {
587 if (info->type != IRQT_PIRQ)
d46a78b0
JF
588 continue;
589
6cb6537d
IC
590 if (info->u.pirq.gsi == gsi)
591 return info->irq;
d46a78b0
JF
592 }
593
594 return -1;
595}
68c2c39a 596EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 597
96d4c588
DV
598static void __unbind_from_irq(unsigned int irq)
599{
96d4c588
DV
600 int evtchn = evtchn_from_irq(irq);
601 struct irq_info *info = irq_get_handler_data(irq);
602
603 if (info->refcnt > 0) {
604 info->refcnt--;
605 if (info->refcnt != 0)
606 return;
607 }
608
609 if (VALID_EVTCHN(evtchn)) {
d0b075ff
DV
610 unsigned int cpu = cpu_from_irq(irq);
611
612 xen_evtchn_close(evtchn);
96d4c588
DV
613
614 switch (type_from_irq(irq)) {
615 case IRQT_VIRQ:
d0b075ff 616 per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1;
96d4c588
DV
617 break;
618 case IRQT_IPI:
d0b075ff 619 per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1;
96d4c588
DV
620 break;
621 default:
622 break;
623 }
624
d0b075ff 625 xen_irq_info_cleanup(info);
96d4c588
DV
626 }
627
628 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
629
630 xen_free_irq(irq);
631}
632
653378ac
IC
633/*
634 * Do not make any assumptions regarding the relationship between the
635 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
636 *
637 * Note: We don't assign an event channel until the irq actually started
638 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
639 *
640 * Shareable implies level triggered, not shareable implies edge
641 * triggered here.
d46a78b0 642 */
f4d0635b
IC
643int xen_bind_pirq_gsi_to_irq(unsigned gsi,
644 unsigned pirq, int shareable, char *name)
d46a78b0 645{
a0e18116 646 int irq = -1;
d46a78b0 647 struct physdev_irq irq_op;
96d4c588 648 int ret;
d46a78b0 649
77365948 650 mutex_lock(&irq_mapping_update_lock);
d46a78b0 651
68c2c39a 652 irq = xen_irq_from_gsi(gsi);
d46a78b0 653 if (irq != -1) {
283c0972
JP
654 pr_info("%s: returning irq %d for gsi %u\n",
655 __func__, irq, gsi);
420eb554 656 goto out;
d46a78b0
JF
657 }
658
c9df1ce5 659 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
660 if (irq < 0)
661 goto out;
d46a78b0 662
d46a78b0 663 irq_op.irq = irq;
b5401a96
AN
664 irq_op.vector = 0;
665
666 /* Only the privileged domain can do this. For non-priv, the pcifront
667 * driver provides a PCI bus that does the call to do exactly
668 * this in the priv domain. */
669 if (xen_initial_domain() &&
670 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 671 xen_free_irq(irq);
d46a78b0
JF
672 irq = -ENOSPC;
673 goto out;
674 }
675
96d4c588 676 ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 677 shareable ? PIRQ_SHAREABLE : 0);
96d4c588
DV
678 if (ret < 0) {
679 __unbind_from_irq(irq);
680 irq = ret;
681 goto out;
682 }
d46a78b0 683
7e186bdd
SS
684 pirq_query_unmask(irq);
685 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
686 * type of interrupt: if the interrupt is an edge triggered
687 * interrupt we use handle_edge_irq.
7e186bdd 688 *
e5ac0bda
SS
689 * On the other hand if the interrupt is level triggered we use
690 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 691 * interrupts.
e5ac0bda 692 *
7e186bdd
SS
693 * Depending on the Xen version, pirq_needs_eoi might return true
694 * not only for level triggered interrupts but for edge triggered
695 * interrupts too. In any case Xen always honors the eoi mechanism,
696 * not injecting any more pirqs of the same kind if the first one
697 * hasn't received an eoi yet. Therefore using the fasteoi handler
698 * is the right choice either way.
699 */
e5ac0bda 700 if (shareable)
7e186bdd
SS
701 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
702 handle_fasteoi_irq, name);
703 else
704 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
705 handle_edge_irq, name);
706
d46a78b0 707out:
77365948 708 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
709
710 return irq;
711}
712
f731e3ef 713#ifdef CONFIG_PCI_MSI
bf480d95 714int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 715{
5cad61a6 716 int rc;
cbf6aa89 717 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 718
bf480d95 719 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 720 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 721
5cad61a6
IC
722 WARN_ONCE(rc == -ENOSYS,
723 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
724
725 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
726}
727
bf480d95 728int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
4892c9b4 729 int pirq, int nvec, const char *name, domid_t domid)
809f9267 730{
4892c9b4 731 int i, irq, ret;
4b41df7f 732
77365948 733 mutex_lock(&irq_mapping_update_lock);
809f9267 734
4892c9b4 735 irq = xen_allocate_irqs_dynamic(nvec);
e6599225 736 if (irq < 0)
bb5d079a 737 goto out;
809f9267 738
4892c9b4
RPM
739 for (i = 0; i < nvec; i++) {
740 irq_set_chip_and_handler_name(irq + i, &xen_pirq_chip, handle_edge_irq, name);
741
742 ret = xen_irq_info_pirq_setup(irq + i, 0, pirq + i, 0, domid,
743 i == 0 ? 0 : PIRQ_MSI_GROUP);
744 if (ret < 0)
745 goto error_irq;
746 }
809f9267 747
5f6fb454 748 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
749 if (ret < 0)
750 goto error_irq;
809f9267 751out:
77365948 752 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 753 return irq;
bf480d95 754error_irq:
4892c9b4
RPM
755 for (; i >= 0; i--)
756 __unbind_from_irq(irq + i);
77365948 757 mutex_unlock(&irq_mapping_update_lock);
e6599225 758 return ret;
809f9267 759}
f731e3ef
QH
760#endif
761
b5401a96
AN
762int xen_destroy_irq(int irq)
763{
38aa66fc
JF
764 struct physdev_unmap_pirq unmap_irq;
765 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
766 int rc = -ENOENT;
767
77365948 768 mutex_lock(&irq_mapping_update_lock);
b5401a96 769
4892c9b4
RPM
770 /*
771 * If trying to remove a vector in a MSI group different
772 * than the first one skip the PIRQ unmap unless this vector
773 * is the first one in the group.
774 */
775 if (xen_initial_domain() && !(info->u.pirq.flags & PIRQ_MSI_GROUP)) {
12334715 776 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 777 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 778 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
779 /* If another domain quits without making the pci_disable_msix
780 * call, the Xen hypervisor takes care of freeing the PIRQs
781 * (free_domain_pirqs).
782 */
783 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 784 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
785 info->u.pirq.domid, info->u.pirq.pirq);
786 else if (rc) {
283c0972 787 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
788 goto out;
789 }
790 }
b5401a96 791
c9df1ce5 792 xen_free_irq(irq);
b5401a96
AN
793
794out:
77365948 795 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
796 return rc;
797}
798
af42b8d1 799int xen_irq_from_pirq(unsigned pirq)
d46a78b0 800{
69c358ce 801 int irq;
d46a78b0 802
69c358ce 803 struct irq_info *info;
e46cdb66 804
77365948 805 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
806
807 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 808 if (info->type != IRQT_PIRQ)
69c358ce
IC
809 continue;
810 irq = info->irq;
811 if (info->u.pirq.pirq == pirq)
812 goto out;
813 }
814 irq = -1;
815out:
77365948 816 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
817
818 return irq;
af42b8d1
SS
819}
820
e6197acc
KRW
821
822int xen_pirq_from_irq(unsigned irq)
823{
824 return pirq_from_irq(irq);
825}
826EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
96d4c588 827
b536b4b9 828int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
829{
830 int irq;
96d4c588 831 int ret;
e46cdb66 832
d0b075ff
DV
833 if (evtchn >= xen_evtchn_max_channels())
834 return -ENOMEM;
835
77365948 836 mutex_lock(&irq_mapping_update_lock);
e46cdb66 837
d0b075ff 838 irq = get_evtchn_to_irq(evtchn);
e46cdb66
JF
839
840 if (irq == -1) {
c9df1ce5 841 irq = xen_allocate_irq_dynamic();
68ba45ff 842 if (irq < 0)
7bee9768 843 goto out;
e46cdb66 844
c442b806 845 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 846 handle_edge_irq, "event");
e46cdb66 847
96d4c588
DV
848 ret = xen_irq_info_evtchn_setup(irq, evtchn);
849 if (ret < 0) {
850 __unbind_from_irq(irq);
851 irq = ret;
852 goto out;
853 }
97253eee
DV
854 /* New interdomain events are bound to VCPU 0. */
855 bind_evtchn_to_cpu(evtchn, 0);
5e152e6c
KRW
856 } else {
857 struct irq_info *info = info_for_irq(irq);
858 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
859 }
860
7bee9768 861out:
77365948 862 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
863
864 return irq;
865}
b536b4b9 866EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 867
f87e4cac
JF
868static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
869{
870 struct evtchn_bind_ipi bind_ipi;
871 int evtchn, irq;
96d4c588 872 int ret;
f87e4cac 873
77365948 874 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
875
876 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 877
f87e4cac 878 if (irq == -1) {
c9df1ce5 879 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
880 if (irq < 0)
881 goto out;
882
c442b806 883 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 884 handle_percpu_irq, "ipi");
f87e4cac
JF
885
886 bind_ipi.vcpu = cpu;
887 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
888 &bind_ipi) != 0)
889 BUG();
890 evtchn = bind_ipi.port;
891
96d4c588
DV
892 ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
893 if (ret < 0) {
894 __unbind_from_irq(irq);
895 irq = ret;
896 goto out;
897 }
f87e4cac 898 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
899 } else {
900 struct irq_info *info = info_for_irq(irq);
901 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
902 }
903
f87e4cac 904 out:
77365948 905 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
906 return irq;
907}
908
854072dd
JG
909int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
910 unsigned int remote_port)
2e820f58
IC
911{
912 struct evtchn_bind_interdomain bind_interdomain;
913 int err;
914
915 bind_interdomain.remote_dom = remote_domain;
916 bind_interdomain.remote_port = remote_port;
917
918 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
919 &bind_interdomain);
920
921 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
922}
854072dd 923EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irq);
2e820f58 924
62cc5fc7
OH
925static int find_virq(unsigned int virq, unsigned int cpu)
926{
927 struct evtchn_status status;
928 int port, rc = -ENOENT;
929
930 memset(&status, 0, sizeof(status));
d0b075ff 931 for (port = 0; port < xen_evtchn_max_channels(); port++) {
62cc5fc7
OH
932 status.dom = DOMID_SELF;
933 status.port = port;
934 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
935 if (rc < 0)
936 continue;
937 if (status.status != EVTCHNSTAT_virq)
938 continue;
939 if (status.u.virq == virq && status.vcpu == cpu) {
940 rc = port;
941 break;
942 }
943 }
944 return rc;
945}
f87e4cac 946
0dc0064a
DV
947/**
948 * xen_evtchn_nr_channels - number of usable event channel ports
949 *
950 * This may be less than the maximum supported by the current
951 * hypervisor ABI. Use xen_evtchn_max_channels() for the maximum
952 * supported.
953 */
954unsigned xen_evtchn_nr_channels(void)
955{
956 return evtchn_ops->nr_channels();
957}
958EXPORT_SYMBOL_GPL(xen_evtchn_nr_channels);
959
77bb3dfd 960int bind_virq_to_irq(unsigned int virq, unsigned int cpu, bool percpu)
e46cdb66
JF
961{
962 struct evtchn_bind_virq bind_virq;
62cc5fc7 963 int evtchn, irq, ret;
e46cdb66 964
77365948 965 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
966
967 irq = per_cpu(virq_to_irq, cpu)[virq];
968
969 if (irq == -1) {
c9df1ce5 970 irq = xen_allocate_irq_dynamic();
68ba45ff 971 if (irq < 0)
7bee9768 972 goto out;
a52521f1 973
77bb3dfd
DV
974 if (percpu)
975 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
976 handle_percpu_irq, "virq");
977 else
978 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
979 handle_edge_irq, "virq");
a52521f1 980
e46cdb66
JF
981 bind_virq.virq = virq;
982 bind_virq.vcpu = cpu;
62cc5fc7
OH
983 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
984 &bind_virq);
985 if (ret == 0)
986 evtchn = bind_virq.port;
987 else {
988 if (ret == -EEXIST)
989 ret = find_virq(virq, cpu);
990 BUG_ON(ret < 0);
991 evtchn = ret;
992 }
e46cdb66 993
96d4c588
DV
994 ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
995 if (ret < 0) {
996 __unbind_from_irq(irq);
997 irq = ret;
998 goto out;
999 }
e46cdb66
JF
1000
1001 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
1002 } else {
1003 struct irq_info *info = info_for_irq(irq);
1004 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
1005 }
1006
7bee9768 1007out:
77365948 1008 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1009
1010 return irq;
1011}
1012
1013static void unbind_from_irq(unsigned int irq)
1014{
77365948 1015 mutex_lock(&irq_mapping_update_lock);
96d4c588 1016 __unbind_from_irq(irq);
77365948 1017 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1018}
1019
1020int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1021 irq_handler_t handler,
e46cdb66
JF
1022 unsigned long irqflags,
1023 const char *devname, void *dev_id)
1024{
361ae8cb 1025 int irq, retval;
e46cdb66
JF
1026
1027 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1028 if (irq < 0)
1029 return irq;
e46cdb66
JF
1030 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1031 if (retval != 0) {
1032 unbind_from_irq(irq);
1033 return retval;
1034 }
1035
1036 return irq;
1037}
1038EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1039
2e820f58
IC
1040int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1041 unsigned int remote_port,
1042 irq_handler_t handler,
1043 unsigned long irqflags,
1044 const char *devname,
1045 void *dev_id)
1046{
1047 int irq, retval;
1048
1049 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1050 if (irq < 0)
1051 return irq;
1052
1053 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1054 if (retval != 0) {
1055 unbind_from_irq(irq);
1056 return retval;
1057 }
1058
1059 return irq;
1060}
1061EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1062
e46cdb66 1063int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1064 irq_handler_t handler,
e46cdb66
JF
1065 unsigned long irqflags, const char *devname, void *dev_id)
1066{
361ae8cb 1067 int irq, retval;
e46cdb66 1068
77bb3dfd 1069 irq = bind_virq_to_irq(virq, cpu, irqflags & IRQF_PERCPU);
7bee9768
IC
1070 if (irq < 0)
1071 return irq;
e46cdb66
JF
1072 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1073 if (retval != 0) {
1074 unbind_from_irq(irq);
1075 return retval;
1076 }
1077
1078 return irq;
1079}
1080EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1081
f87e4cac
JF
1082int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1083 unsigned int cpu,
1084 irq_handler_t handler,
1085 unsigned long irqflags,
1086 const char *devname,
1087 void *dev_id)
1088{
1089 int irq, retval;
1090
1091 irq = bind_ipi_to_irq(ipi, cpu);
1092 if (irq < 0)
1093 return irq;
1094
9bab0b7f 1095 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1096 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1097 if (retval != 0) {
1098 unbind_from_irq(irq);
1099 return retval;
1100 }
1101
1102 return irq;
1103}
1104
e46cdb66
JF
1105void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1106{
94032c50
KRW
1107 struct irq_info *info = irq_get_handler_data(irq);
1108
1109 if (WARN_ON(!info))
1110 return;
e46cdb66
JF
1111 free_irq(irq, dev_id);
1112 unbind_from_irq(irq);
1113}
1114EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1115
6ccecb0f
DV
1116/**
1117 * xen_set_irq_priority() - set an event channel priority.
1118 * @irq:irq bound to an event channel.
1119 * @priority: priority between XEN_IRQ_PRIORITY_MAX and XEN_IRQ_PRIORITY_MIN.
1120 */
1121int xen_set_irq_priority(unsigned irq, unsigned priority)
1122{
1123 struct evtchn_set_priority set_priority;
1124
1125 set_priority.port = evtchn_from_irq(irq);
1126 set_priority.priority = priority;
1127
1128 return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority,
1129 &set_priority);
1130}
1131EXPORT_SYMBOL_GPL(xen_set_irq_priority);
1132
420eb554
DDG
1133int evtchn_make_refcounted(unsigned int evtchn)
1134{
d0b075ff 1135 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1136 struct irq_info *info;
1137
1138 if (irq == -1)
1139 return -ENOENT;
1140
1141 info = irq_get_handler_data(irq);
1142
1143 if (!info)
1144 return -ENOENT;
1145
1146 WARN_ON(info->refcnt != -1);
1147
1148 info->refcnt = 1;
1149
1150 return 0;
1151}
1152EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1153
1154int evtchn_get(unsigned int evtchn)
1155{
1156 int irq;
1157 struct irq_info *info;
1158 int err = -ENOENT;
1159
d0b075ff 1160 if (evtchn >= xen_evtchn_max_channels())
c3b3f16d
DDG
1161 return -EINVAL;
1162
420eb554
DDG
1163 mutex_lock(&irq_mapping_update_lock);
1164
d0b075ff 1165 irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1166 if (irq == -1)
1167 goto done;
1168
1169 info = irq_get_handler_data(irq);
1170
1171 if (!info)
1172 goto done;
1173
1174 err = -EINVAL;
1175 if (info->refcnt <= 0)
1176 goto done;
1177
1178 info->refcnt++;
1179 err = 0;
1180 done:
1181 mutex_unlock(&irq_mapping_update_lock);
1182
1183 return err;
1184}
1185EXPORT_SYMBOL_GPL(evtchn_get);
1186
1187void evtchn_put(unsigned int evtchn)
1188{
d0b075ff 1189 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1190 if (WARN_ON(irq == -1))
1191 return;
1192 unbind_from_irq(irq);
1193}
1194EXPORT_SYMBOL_GPL(evtchn_put);
1195
f87e4cac
JF
1196void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1197{
6efa20e4
KRW
1198 int irq;
1199
072b2064 1200#ifdef CONFIG_X86
6efa20e4
KRW
1201 if (unlikely(vector == XEN_NMI_VECTOR)) {
1202 int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
1203 if (rc < 0)
1204 printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
1205 return;
1206 }
072b2064 1207#endif
6efa20e4 1208 irq = per_cpu(ipi_to_irq, cpu)[vector];
f87e4cac
JF
1209 BUG_ON(irq < 0);
1210 notify_remote_via_irq(irq);
1211}
1212
245b2e70
TH
1213static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1214
38e20b07 1215static void __xen_evtchn_do_upcall(void)
e46cdb66 1216{
780f36d8 1217 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
9a489f45 1218 int cpu = get_cpu();
088c05a8 1219 unsigned count;
e46cdb66 1220
229664be 1221 do {
229664be 1222 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1223
b2e4ae69 1224 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1225 goto out;
e46cdb66 1226
9a489f45 1227 xen_evtchn_handle_events(cpu);
e46cdb66 1228
229664be
JF
1229 BUG_ON(!irqs_disabled());
1230
780f36d8
CL
1231 count = __this_cpu_read(xed_nesting_count);
1232 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1233 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1234
1235out:
38e20b07
SY
1236
1237 put_cpu();
1238}
1239
1240void xen_evtchn_do_upcall(struct pt_regs *regs)
1241{
1242 struct pt_regs *old_regs = set_irq_regs(regs);
1243
772aebce 1244 irq_enter();
0ec53ecf 1245#ifdef CONFIG_X86
38e20b07 1246 exit_idle();
99c8b79d 1247 inc_irq_stat(irq_hv_callback_count);
d06eb3ee 1248#endif
38e20b07
SY
1249
1250 __xen_evtchn_do_upcall();
1251
3445a8fd
JF
1252 irq_exit();
1253 set_irq_regs(old_regs);
38e20b07 1254}
3445a8fd 1255
38e20b07
SY
1256void xen_hvm_evtchn_do_upcall(void)
1257{
1258 __xen_evtchn_do_upcall();
e46cdb66 1259}
183d03cc 1260EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1261
eb1e305f
JF
1262/* Rebind a new event channel to an existing irq. */
1263void rebind_evtchn_irq(int evtchn, int irq)
1264{
d77bbd4d
JF
1265 struct irq_info *info = info_for_irq(irq);
1266
94032c50
KRW
1267 if (WARN_ON(!info))
1268 return;
1269
eb1e305f
JF
1270 /* Make sure the irq is masked, since the new event channel
1271 will also be masked. */
1272 disable_irq(irq);
1273
77365948 1274 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1275
1276 /* After resume the irq<->evtchn mappings are all cleared out */
d0b075ff 1277 BUG_ON(get_evtchn_to_irq(evtchn) != -1);
eb1e305f 1278 /* Expect irq to have been bound before,
d77bbd4d
JF
1279 so there should be a proper type */
1280 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1281
96d4c588 1282 (void)xen_irq_info_evtchn_setup(irq, evtchn);
eb1e305f 1283
77365948 1284 mutex_unlock(&irq_mapping_update_lock);
eb1e305f 1285
5cec9883
BO
1286 bind_evtchn_to_cpu(evtchn, info->cpu);
1287 /* This will be deferred until interrupt is processed */
1288 irq_set_affinity(irq, cpumask_of(info->cpu));
eb1e305f
JF
1289
1290 /* Unmask the event channel. */
1291 enable_irq(irq);
1292}
1293
e46cdb66 1294/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1295static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1296{
1297 struct evtchn_bind_vcpu bind_vcpu;
1298 int evtchn = evtchn_from_irq(irq);
4704fe4f 1299 int masked;
e46cdb66 1300
be49472f
IC
1301 if (!VALID_EVTCHN(evtchn))
1302 return -1;
1303
4a5b6946 1304 if (!xen_support_evtchn_rebind())
d5dedd45 1305 return -1;
e46cdb66
JF
1306
1307 /* Send future instances of this interrupt to other vcpu. */
1308 bind_vcpu.port = evtchn;
1309 bind_vcpu.vcpu = tcpu;
1310
4704fe4f
DV
1311 /*
1312 * Mask the event while changing the VCPU binding to prevent
1313 * it being delivered on an unexpected VCPU.
1314 */
3f70fa82 1315 masked = test_and_set_mask(evtchn);
4704fe4f 1316
e46cdb66
JF
1317 /*
1318 * If this fails, it usually just indicates that we're dealing with a
1319 * virq or IPI channel, which don't actually need to be rebound. Ignore
1320 * it, but don't do the xenlinux-level rebind in that case.
1321 */
1322 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1323 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1324
4704fe4f
DV
1325 if (!masked)
1326 unmask_evtchn(evtchn);
1327
d5dedd45
YL
1328 return 0;
1329}
e46cdb66 1330
c9e265e0
TG
1331static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1332 bool force)
e46cdb66 1333{
753fbd23 1334 unsigned tcpu = cpumask_first_and(dest, cpu_online_mask);
d5dedd45 1335
c9e265e0 1336 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1337}
1338
c9e265e0 1339static void enable_dynirq(struct irq_data *data)
e46cdb66 1340{
c9e265e0 1341 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1342
1343 if (VALID_EVTCHN(evtchn))
1344 unmask_evtchn(evtchn);
1345}
1346
c9e265e0 1347static void disable_dynirq(struct irq_data *data)
e46cdb66 1348{
c9e265e0 1349 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1350
1351 if (VALID_EVTCHN(evtchn))
1352 mask_evtchn(evtchn);
1353}
1354
c9e265e0 1355static void ack_dynirq(struct irq_data *data)
e46cdb66 1356{
c9e265e0 1357 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1358
7e186bdd 1359 irq_move_irq(data);
e46cdb66
JF
1360
1361 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1362 clear_evtchn(evtchn);
1363}
1364
1365static void mask_ack_dynirq(struct irq_data *data)
1366{
1367 disable_dynirq(data);
1368 ack_dynirq(data);
e46cdb66
JF
1369}
1370
c9e265e0 1371static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1372{
4640ddf5
DV
1373 unsigned int evtchn = evtchn_from_irq(data->irq);
1374 int masked;
1375
1376 if (!VALID_EVTCHN(evtchn))
1377 return 0;
1378
1379 masked = test_and_set_mask(evtchn);
1380 set_evtchn(evtchn);
1381 if (!masked)
1382 unmask_evtchn(evtchn);
1383
1384 return 1;
e46cdb66
JF
1385}
1386
0a85226f 1387static void restore_pirqs(void)
9a069c33
SS
1388{
1389 int pirq, rc, irq, gsi;
1390 struct physdev_map_pirq map_irq;
69c358ce 1391 struct irq_info *info;
9a069c33 1392
69c358ce
IC
1393 list_for_each_entry(info, &xen_irq_list_head, list) {
1394 if (info->type != IRQT_PIRQ)
9a069c33
SS
1395 continue;
1396
69c358ce
IC
1397 pirq = info->u.pirq.pirq;
1398 gsi = info->u.pirq.gsi;
1399 irq = info->irq;
1400
9a069c33
SS
1401 /* save/restore of PT devices doesn't work, so at this point the
1402 * only devices present are GSI based emulated devices */
9a069c33
SS
1403 if (!gsi)
1404 continue;
1405
1406 map_irq.domid = DOMID_SELF;
1407 map_irq.type = MAP_PIRQ_TYPE_GSI;
1408 map_irq.index = gsi;
1409 map_irq.pirq = pirq;
1410
1411 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1412 if (rc) {
283c0972
JP
1413 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1414 gsi, irq, pirq, rc);
9158c358 1415 xen_free_irq(irq);
9a069c33
SS
1416 continue;
1417 }
1418
1419 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1420
c9e265e0 1421 __startup_pirq(irq);
9a069c33
SS
1422 }
1423}
1424
0e91398f
JF
1425static void restore_cpu_virqs(unsigned int cpu)
1426{
1427 struct evtchn_bind_virq bind_virq;
1428 int virq, irq, evtchn;
1429
1430 for (virq = 0; virq < NR_VIRQS; virq++) {
1431 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1432 continue;
1433
ced40d0f 1434 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1435
1436 /* Get a new binding from Xen. */
1437 bind_virq.virq = virq;
1438 bind_virq.vcpu = cpu;
1439 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1440 &bind_virq) != 0)
1441 BUG();
1442 evtchn = bind_virq.port;
1443
1444 /* Record the new mapping. */
96d4c588 1445 (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
0e91398f 1446 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1447 }
1448}
1449
1450static void restore_cpu_ipis(unsigned int cpu)
1451{
1452 struct evtchn_bind_ipi bind_ipi;
1453 int ipi, irq, evtchn;
1454
1455 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1456 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1457 continue;
1458
ced40d0f 1459 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1460
1461 /* Get a new binding from Xen. */
1462 bind_ipi.vcpu = cpu;
1463 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1464 &bind_ipi) != 0)
1465 BUG();
1466 evtchn = bind_ipi.port;
1467
1468 /* Record the new mapping. */
96d4c588 1469 (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
0e91398f 1470 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1471 }
1472}
1473
2d9e1e2f
JF
1474/* Clear an irq's pending state, in preparation for polling on it */
1475void xen_clear_irq_pending(int irq)
1476{
1477 int evtchn = evtchn_from_irq(irq);
1478
1479 if (VALID_EVTCHN(evtchn))
1480 clear_evtchn(evtchn);
1481}
d9a8814f 1482EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1483void xen_set_irq_pending(int irq)
1484{
1485 int evtchn = evtchn_from_irq(irq);
1486
1487 if (VALID_EVTCHN(evtchn))
1488 set_evtchn(evtchn);
1489}
1490
1491bool xen_test_irq_pending(int irq)
1492{
1493 int evtchn = evtchn_from_irq(irq);
1494 bool ret = false;
1495
1496 if (VALID_EVTCHN(evtchn))
1497 ret = test_evtchn(evtchn);
1498
1499 return ret;
1500}
1501
d9a8814f
KRW
1502/* Poll waiting for an irq to become pending with timeout. In the usual case,
1503 * the irq will be disabled so it won't deliver an interrupt. */
1504void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1505{
1506 evtchn_port_t evtchn = evtchn_from_irq(irq);
1507
1508 if (VALID_EVTCHN(evtchn)) {
1509 struct sched_poll poll;
1510
1511 poll.nr_ports = 1;
d9a8814f 1512 poll.timeout = timeout;
ff3c5362 1513 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1514
1515 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1516 BUG();
1517 }
1518}
d9a8814f
KRW
1519EXPORT_SYMBOL(xen_poll_irq_timeout);
1520/* Poll waiting for an irq to become pending. In the usual case, the
1521 * irq will be disabled so it won't deliver an interrupt. */
1522void xen_poll_irq(int irq)
1523{
1524 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1525}
2d9e1e2f 1526
c7c2c3a2
KRW
1527/* Check whether the IRQ line is shared with other guests. */
1528int xen_test_irq_shared(int irq)
1529{
1530 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1531 struct physdev_irq_status_query irq_status;
1532
1533 if (WARN_ON(!info))
1534 return -ENOENT;
1535
1536 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1537
1538 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1539 return 0;
1540 return !(irq_status.flags & XENIRQSTAT_shared);
1541}
1542EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1543
0e91398f
JF
1544void xen_irq_resume(void)
1545{
fd21069d 1546 unsigned int cpu;
6cb6537d 1547 struct irq_info *info;
0e91398f 1548
0e91398f 1549 /* New event-channel space is not 'live' yet. */
fd21069d 1550 xen_evtchn_mask_all();
1fe56551 1551 xen_evtchn_resume();
0e91398f
JF
1552
1553 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1554 list_for_each_entry(info, &xen_irq_list_head, list)
1555 info->evtchn = 0; /* zap event-channel binding */
0e91398f 1556
d0b075ff 1557 clear_evtchn_to_irq_all();
0e91398f
JF
1558
1559 for_each_possible_cpu(cpu) {
1560 restore_cpu_virqs(cpu);
1561 restore_cpu_ipis(cpu);
1562 }
6903591f 1563
0a85226f 1564 restore_pirqs();
0e91398f
JF
1565}
1566
e46cdb66 1567static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1568 .name = "xen-dyn",
54a353a0 1569
c9e265e0
TG
1570 .irq_disable = disable_dynirq,
1571 .irq_mask = disable_dynirq,
1572 .irq_unmask = enable_dynirq,
54a353a0 1573
7e186bdd
SS
1574 .irq_ack = ack_dynirq,
1575 .irq_mask_ack = mask_ack_dynirq,
1576
c9e265e0
TG
1577 .irq_set_affinity = set_affinity_irq,
1578 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1579};
1580
d46a78b0 1581static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1582 .name = "xen-pirq",
d46a78b0 1583
c9e265e0
TG
1584 .irq_startup = startup_pirq,
1585 .irq_shutdown = shutdown_pirq,
c9e265e0 1586 .irq_enable = enable_pirq,
c9e265e0 1587 .irq_disable = disable_pirq,
d46a78b0 1588
7e186bdd
SS
1589 .irq_mask = disable_dynirq,
1590 .irq_unmask = enable_dynirq,
1591
1592 .irq_ack = eoi_pirq,
1593 .irq_eoi = eoi_pirq,
1594 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1595
c9e265e0 1596 .irq_set_affinity = set_affinity_irq,
d46a78b0 1597
c9e265e0 1598 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1599};
1600
aaca4964 1601static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1602 .name = "xen-percpu",
aaca4964 1603
c9e265e0
TG
1604 .irq_disable = disable_dynirq,
1605 .irq_mask = disable_dynirq,
1606 .irq_unmask = enable_dynirq,
aaca4964 1607
c9e265e0 1608 .irq_ack = ack_dynirq,
aaca4964
JF
1609};
1610
38e20b07
SY
1611int xen_set_callback_via(uint64_t via)
1612{
1613 struct xen_hvm_param a;
1614 a.domid = DOMID_SELF;
1615 a.index = HVM_PARAM_CALLBACK_IRQ;
1616 a.value = via;
1617 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1618}
1619EXPORT_SYMBOL_GPL(xen_set_callback_via);
1620
ca65f9fc 1621#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1622/* Vector callbacks are better than PCI interrupts to receive event
1623 * channel notifications because we can receive vector callbacks on any
1624 * vcpu and we don't need PCI support or APIC interactions. */
1625void xen_callback_vector(void)
1626{
1627 int rc;
1628 uint64_t callback_via;
1629 if (xen_have_vector_callback) {
bc2b0331 1630 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1631 rc = xen_set_callback_via(callback_via);
1632 if (rc) {
283c0972 1633 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1634 xen_have_vector_callback = 0;
1635 return;
1636 }
283c0972 1637 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1638 /* in the restore case the vector has already been allocated */
bc2b0331
S
1639 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1640 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1641 xen_hvm_callback_vector);
38e20b07
SY
1642 }
1643}
ca65f9fc
SS
1644#else
1645void xen_callback_vector(void) {}
1646#endif
38e20b07 1647
1fe56551
DV
1648#undef MODULE_PARAM_PREFIX
1649#define MODULE_PARAM_PREFIX "xen."
1650
1651static bool fifo_events = true;
1652module_param(fifo_events, bool, 0);
1653
2e3d8860 1654void __init xen_init_IRQ(void)
e46cdb66 1655{
1fe56551
DV
1656 int ret = -EINVAL;
1657
1658 if (fifo_events)
1659 ret = xen_evtchn_fifo_init();
1660 if (ret < 0)
1661 xen_evtchn_2l_init();
ab9a1cca 1662
d0b075ff
DV
1663 evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()),
1664 sizeof(*evtchn_to_irq), GFP_KERNEL);
9d093e29 1665 BUG_ON(!evtchn_to_irq);
e46cdb66 1666
e46cdb66 1667 /* No event channels are 'live' right now. */
fd21069d 1668 xen_evtchn_mask_all();
e46cdb66 1669
9846ff10
SS
1670 pirq_needs_eoi = pirq_needs_eoi_flag;
1671
0ec53ecf 1672#ifdef CONFIG_X86
2771374d
MR
1673 if (xen_pv_domain()) {
1674 irq_ctx_init(smp_processor_id());
1675 if (xen_initial_domain())
1676 pci_xen_initial_domain();
1677 }
1678 if (xen_feature(XENFEAT_hvm_callback_vector))
38e20b07 1679 xen_callback_vector();
2771374d
MR
1680
1681 if (xen_hvm_domain()) {
38e20b07 1682 native_init_IRQ();
3942b740
SS
1683 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1684 * __acpi_register_gsi can point at the right function */
1685 pci_xen_hvm_init();
38e20b07 1686 } else {
0ec53ecf 1687 int rc;
9846ff10
SS
1688 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1689
9846ff10 1690 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
0df4f266 1691 eoi_gmfn.gmfn = virt_to_gfn(pirq_eoi_map);
9846ff10 1692 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
2771374d 1693 /* TODO: No PVH support for PIRQ EOI */
9846ff10
SS
1694 if (rc != 0) {
1695 free_page((unsigned long) pirq_eoi_map);
1696 pirq_eoi_map = NULL;
1697 } else
1698 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1699 }
0ec53ecf 1700#endif
e46cdb66 1701}