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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e46cdb66 JF |
2 | /* |
3 | * Xen event channels | |
4 | * | |
5 | * Xen models interrupts with abstract event channels. Because each | |
6 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
7 | * must dynamically map irqs<->event channels. The event channels | |
8 | * interface with the rest of the kernel by defining a xen interrupt | |
25985edc | 9 | * chip. When an event is received, it is mapped to an irq and sent |
e46cdb66 JF |
10 | * through the normal interrupt processing path. |
11 | * | |
12 | * There are four kinds of events which can be mapped to an event | |
13 | * channel: | |
14 | * | |
15 | * 1. Inter-domain notifications. This includes all the virtual | |
16 | * device events, since they're driven by front-ends in another domain | |
17 | * (typically dom0). | |
18 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
19 | * 3. IPIs. | |
d46a78b0 | 20 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
21 | * |
22 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
23 | */ | |
24 | ||
283c0972 JP |
25 | #define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt |
26 | ||
e46cdb66 JF |
27 | #include <linux/linkage.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/irq.h> | |
59aa56bf | 30 | #include <linux/moduleparam.h> |
e46cdb66 | 31 | #include <linux/string.h> |
57c8a661 | 32 | #include <linux/memblock.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
b21ddbf5 | 34 | #include <linux/irqnr.h> |
f731e3ef | 35 | #include <linux/pci.h> |
e46cdb66 | 36 | |
0ec53ecf | 37 | #ifdef CONFIG_X86 |
38e20b07 | 38 | #include <asm/desc.h> |
e46cdb66 JF |
39 | #include <asm/ptrace.h> |
40 | #include <asm/irq.h> | |
0794bfc7 | 41 | #include <asm/io_apic.h> |
b4ff8389 | 42 | #include <asm/i8259.h> |
42a1de56 | 43 | #include <asm/xen/pci.h> |
0ec53ecf SS |
44 | #endif |
45 | #include <asm/sync_bitops.h> | |
e46cdb66 | 46 | #include <asm/xen/hypercall.h> |
8d1b8753 | 47 | #include <asm/xen/hypervisor.h> |
a001c9d9 | 48 | #include <xen/page.h> |
e46cdb66 | 49 | |
38e20b07 SY |
50 | #include <xen/xen.h> |
51 | #include <xen/hvm.h> | |
e04d0d07 | 52 | #include <xen/xen-ops.h> |
e46cdb66 JF |
53 | #include <xen/events.h> |
54 | #include <xen/interface/xen.h> | |
55 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
56 | #include <xen/interface/hvm/hvm_op.h> |
57 | #include <xen/interface/hvm/params.h> | |
0ec53ecf SS |
58 | #include <xen/interface/physdev.h> |
59 | #include <xen/interface/sched.h> | |
6efa20e4 | 60 | #include <xen/interface/vcpu.h> |
0ec53ecf | 61 | #include <asm/hw_irq.h> |
e46cdb66 | 62 | |
9a489f45 DV |
63 | #include "events_internal.h" |
64 | ||
ab9a1cca DV |
65 | const struct evtchn_ops *evtchn_ops; |
66 | ||
e46cdb66 JF |
67 | /* |
68 | * This lock protects updates to the following mapping and reference-count | |
69 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
70 | */ | |
77365948 | 71 | static DEFINE_MUTEX(irq_mapping_update_lock); |
e46cdb66 | 72 | |
6cb6537d IC |
73 | static LIST_HEAD(xen_irq_list_head); |
74 | ||
e46cdb66 | 75 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 76 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 77 | |
f87e4cac | 78 | /* IRQ <-> IPI mapping */ |
204fba4a | 79 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 80 | |
d0b075ff | 81 | int **evtchn_to_irq; |
bf86ad80 | 82 | #ifdef CONFIG_X86 |
9846ff10 | 83 | static unsigned long *pirq_eoi_map; |
bf86ad80 | 84 | #endif |
9846ff10 | 85 | static bool (*pirq_needs_eoi)(unsigned irq); |
3b32f574 | 86 | |
d0b075ff DV |
87 | #define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq))) |
88 | #define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq))) | |
89 | #define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq)) | |
90 | ||
e46cdb66 JF |
91 | /* Xen will never allocate port zero for any purpose. */ |
92 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
93 | ||
4d858574 JG |
94 | static struct irq_info *legacy_info_ptrs[NR_IRQS_LEGACY]; |
95 | ||
e46cdb66 | 96 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 97 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 98 | static struct irq_chip xen_pirq_chip; |
7e186bdd SS |
99 | static void enable_dynirq(struct irq_data *data); |
100 | static void disable_dynirq(struct irq_data *data); | |
e46cdb66 | 101 | |
d0b075ff DV |
102 | static void clear_evtchn_to_irq_row(unsigned row) |
103 | { | |
104 | unsigned col; | |
105 | ||
106 | for (col = 0; col < EVTCHN_PER_ROW; col++) | |
107 | evtchn_to_irq[row][col] = -1; | |
108 | } | |
109 | ||
110 | static void clear_evtchn_to_irq_all(void) | |
111 | { | |
112 | unsigned row; | |
113 | ||
114 | for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) { | |
115 | if (evtchn_to_irq[row] == NULL) | |
116 | continue; | |
117 | clear_evtchn_to_irq_row(row); | |
118 | } | |
119 | } | |
120 | ||
121 | static int set_evtchn_to_irq(unsigned evtchn, unsigned irq) | |
122 | { | |
123 | unsigned row; | |
124 | unsigned col; | |
125 | ||
126 | if (evtchn >= xen_evtchn_max_channels()) | |
127 | return -EINVAL; | |
128 | ||
129 | row = EVTCHN_ROW(evtchn); | |
130 | col = EVTCHN_COL(evtchn); | |
131 | ||
132 | if (evtchn_to_irq[row] == NULL) { | |
133 | /* Unallocated irq entries return -1 anyway */ | |
134 | if (irq == -1) | |
135 | return 0; | |
136 | ||
137 | evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL); | |
138 | if (evtchn_to_irq[row] == NULL) | |
139 | return -ENOMEM; | |
140 | ||
141 | clear_evtchn_to_irq_row(row); | |
142 | } | |
143 | ||
4dca864b | 144 | evtchn_to_irq[row][col] = irq; |
d0b075ff DV |
145 | return 0; |
146 | } | |
147 | ||
148 | int get_evtchn_to_irq(unsigned evtchn) | |
149 | { | |
150 | if (evtchn >= xen_evtchn_max_channels()) | |
151 | return -1; | |
152 | if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL) | |
153 | return -1; | |
154 | return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)]; | |
155 | } | |
156 | ||
9158c358 | 157 | /* Get info for IRQ */ |
9a489f45 | 158 | struct irq_info *info_for_irq(unsigned irq) |
ced40d0f | 159 | { |
4d858574 JG |
160 | if (irq < nr_legacy_irqs()) |
161 | return legacy_info_ptrs[irq]; | |
162 | else | |
163 | return irq_get_chip_data(irq); | |
164 | } | |
165 | ||
166 | static void set_info_for_irq(unsigned int irq, struct irq_info *info) | |
167 | { | |
168 | if (irq < nr_legacy_irqs()) | |
169 | legacy_info_ptrs[irq] = info; | |
170 | else | |
171 | irq_set_chip_data(irq, info); | |
ced40d0f JF |
172 | } |
173 | ||
9158c358 | 174 | /* Constructors for packed IRQ information. */ |
96d4c588 | 175 | static int xen_irq_info_common_setup(struct irq_info *info, |
3d4cfa37 | 176 | unsigned irq, |
9158c358 | 177 | enum xen_irq_type type, |
d0b075ff | 178 | unsigned evtchn, |
9158c358 | 179 | unsigned short cpu) |
ced40d0f | 180 | { |
d0b075ff | 181 | int ret; |
9158c358 IC |
182 | |
183 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
184 | ||
185 | info->type = type; | |
6cb6537d | 186 | info->irq = irq; |
9158c358 IC |
187 | info->evtchn = evtchn; |
188 | info->cpu = cpu; | |
3d4cfa37 | 189 | |
d0b075ff DV |
190 | ret = set_evtchn_to_irq(evtchn, irq); |
191 | if (ret < 0) | |
192 | return ret; | |
934f585e JG |
193 | |
194 | irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN); | |
96d4c588 | 195 | |
08385875 | 196 | return xen_evtchn_port_setup(info); |
ced40d0f JF |
197 | } |
198 | ||
96d4c588 | 199 | static int xen_irq_info_evtchn_setup(unsigned irq, |
d0b075ff | 200 | unsigned evtchn) |
ced40d0f | 201 | { |
9158c358 IC |
202 | struct irq_info *info = info_for_irq(irq); |
203 | ||
96d4c588 | 204 | return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
205 | } |
206 | ||
96d4c588 | 207 | static int xen_irq_info_ipi_setup(unsigned cpu, |
3d4cfa37 | 208 | unsigned irq, |
d0b075ff | 209 | unsigned evtchn, |
9158c358 | 210 | enum ipi_vector ipi) |
e46cdb66 | 211 | { |
9158c358 IC |
212 | struct irq_info *info = info_for_irq(irq); |
213 | ||
9158c358 | 214 | info->u.ipi = ipi; |
3d4cfa37 IC |
215 | |
216 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
96d4c588 DV |
217 | |
218 | return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0); | |
ced40d0f JF |
219 | } |
220 | ||
96d4c588 | 221 | static int xen_irq_info_virq_setup(unsigned cpu, |
3d4cfa37 | 222 | unsigned irq, |
d0b075ff DV |
223 | unsigned evtchn, |
224 | unsigned virq) | |
ced40d0f | 225 | { |
9158c358 IC |
226 | struct irq_info *info = info_for_irq(irq); |
227 | ||
9158c358 | 228 | info->u.virq = virq; |
3d4cfa37 IC |
229 | |
230 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
96d4c588 DV |
231 | |
232 | return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0); | |
ced40d0f JF |
233 | } |
234 | ||
96d4c588 | 235 | static int xen_irq_info_pirq_setup(unsigned irq, |
d0b075ff DV |
236 | unsigned evtchn, |
237 | unsigned pirq, | |
238 | unsigned gsi, | |
beafbdc1 | 239 | uint16_t domid, |
9158c358 | 240 | unsigned char flags) |
ced40d0f | 241 | { |
9158c358 IC |
242 | struct irq_info *info = info_for_irq(irq); |
243 | ||
9158c358 IC |
244 | info->u.pirq.pirq = pirq; |
245 | info->u.pirq.gsi = gsi; | |
beafbdc1 | 246 | info->u.pirq.domid = domid; |
9158c358 | 247 | info->u.pirq.flags = flags; |
96d4c588 DV |
248 | |
249 | return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0); | |
e46cdb66 JF |
250 | } |
251 | ||
d0b075ff DV |
252 | static void xen_irq_info_cleanup(struct irq_info *info) |
253 | { | |
254 | set_evtchn_to_irq(info->evtchn, -1); | |
255 | info->evtchn = 0; | |
256 | } | |
257 | ||
e46cdb66 JF |
258 | /* |
259 | * Accessors for packed IRQ information. | |
260 | */ | |
9a489f45 | 261 | unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 262 | { |
89f40354 | 263 | if (WARN(irq >= nr_irqs, "Invalid irq %d!\n", irq)) |
110e7c7e JJ |
264 | return 0; |
265 | ||
ced40d0f | 266 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
267 | } |
268 | ||
d4c04536 IC |
269 | unsigned irq_from_evtchn(unsigned int evtchn) |
270 | { | |
d0b075ff | 271 | return get_evtchn_to_irq(evtchn); |
d4c04536 IC |
272 | } |
273 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
274 | ||
9a489f45 DV |
275 | int irq_from_virq(unsigned int cpu, unsigned int virq) |
276 | { | |
277 | return per_cpu(virq_to_irq, cpu)[virq]; | |
278 | } | |
279 | ||
ced40d0f | 280 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 281 | { |
ced40d0f JF |
282 | struct irq_info *info = info_for_irq(irq); |
283 | ||
284 | BUG_ON(info == NULL); | |
285 | BUG_ON(info->type != IRQT_IPI); | |
286 | ||
287 | return info->u.ipi; | |
288 | } | |
289 | ||
290 | static unsigned virq_from_irq(unsigned irq) | |
291 | { | |
292 | struct irq_info *info = info_for_irq(irq); | |
293 | ||
294 | BUG_ON(info == NULL); | |
295 | BUG_ON(info->type != IRQT_VIRQ); | |
296 | ||
297 | return info->u.virq; | |
298 | } | |
299 | ||
7a043f11 SS |
300 | static unsigned pirq_from_irq(unsigned irq) |
301 | { | |
302 | struct irq_info *info = info_for_irq(irq); | |
303 | ||
304 | BUG_ON(info == NULL); | |
305 | BUG_ON(info->type != IRQT_PIRQ); | |
306 | ||
307 | return info->u.pirq.pirq; | |
308 | } | |
309 | ||
ced40d0f JF |
310 | static enum xen_irq_type type_from_irq(unsigned irq) |
311 | { | |
312 | return info_for_irq(irq)->type; | |
313 | } | |
314 | ||
9a489f45 | 315 | unsigned cpu_from_irq(unsigned irq) |
ced40d0f JF |
316 | { |
317 | return info_for_irq(irq)->cpu; | |
318 | } | |
319 | ||
9a489f45 | 320 | unsigned int cpu_from_evtchn(unsigned int evtchn) |
ced40d0f | 321 | { |
d0b075ff | 322 | int irq = get_evtchn_to_irq(evtchn); |
ced40d0f JF |
323 | unsigned ret = 0; |
324 | ||
325 | if (irq != -1) | |
326 | ret = cpu_from_irq(irq); | |
327 | ||
328 | return ret; | |
e46cdb66 JF |
329 | } |
330 | ||
bf86ad80 | 331 | #ifdef CONFIG_X86 |
9846ff10 | 332 | static bool pirq_check_eoi_map(unsigned irq) |
d46a78b0 | 333 | { |
521394e4 | 334 | return test_bit(pirq_from_irq(irq), pirq_eoi_map); |
9846ff10 | 335 | } |
bf86ad80 | 336 | #endif |
d46a78b0 | 337 | |
9846ff10 SS |
338 | static bool pirq_needs_eoi_flag(unsigned irq) |
339 | { | |
340 | struct irq_info *info = info_for_irq(irq); | |
d46a78b0 JF |
341 | BUG_ON(info->type != IRQT_PIRQ); |
342 | ||
343 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
344 | } | |
345 | ||
e46cdb66 JF |
346 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) |
347 | { | |
d0b075ff | 348 | int irq = get_evtchn_to_irq(chn); |
9a489f45 | 349 | struct irq_info *info = info_for_irq(irq); |
e46cdb66 JF |
350 | |
351 | BUG_ON(irq == -1); | |
352 | #ifdef CONFIG_SMP | |
c149e4cd | 353 | cpumask_copy(irq_get_affinity_mask(irq), cpumask_of(cpu)); |
e46cdb66 | 354 | #endif |
9a489f45 | 355 | xen_evtchn_port_bind_to_cpu(info, cpu); |
168d2f46 | 356 | |
9a489f45 | 357 | info->cpu = cpu; |
3f70fa82 WL |
358 | } |
359 | ||
e46cdb66 JF |
360 | /** |
361 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
362 | * @irq: irq of event channel to send event to | |
363 | * | |
364 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
365 | * save/restore. Notifications on a broken connection are silently | |
366 | * dropped. | |
367 | */ | |
368 | void notify_remote_via_irq(int irq) | |
369 | { | |
370 | int evtchn = evtchn_from_irq(irq); | |
371 | ||
372 | if (VALID_EVTCHN(evtchn)) | |
373 | notify_remote_via_evtchn(evtchn); | |
374 | } | |
375 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
376 | ||
6cb6537d IC |
377 | static void xen_irq_init(unsigned irq) |
378 | { | |
379 | struct irq_info *info; | |
b5328cd1 | 380 | #ifdef CONFIG_SMP |
6cb6537d | 381 | /* By default all event channels notify CPU#0. */ |
c149e4cd | 382 | cpumask_copy(irq_get_affinity_mask(irq), cpumask_of(0)); |
44626e4a | 383 | #endif |
6cb6537d | 384 | |
ca62ce8c IC |
385 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
386 | if (info == NULL) | |
387 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
388 | |
389 | info->type = IRQT_UNBOUND; | |
420eb554 | 390 | info->refcnt = -1; |
6cb6537d | 391 | |
4d858574 | 392 | set_info_for_irq(irq, info); |
ca62ce8c | 393 | |
6cb6537d IC |
394 | list_add_tail(&info->list, &xen_irq_list_head); |
395 | } | |
396 | ||
4892c9b4 | 397 | static int __must_check xen_allocate_irqs_dynamic(int nvec) |
0794bfc7 | 398 | { |
d07c9f18 | 399 | int i, irq = irq_alloc_descs(-1, 0, nvec, -1); |
3a69e916 | 400 | |
4892c9b4 RPM |
401 | if (irq >= 0) { |
402 | for (i = 0; i < nvec; i++) | |
403 | xen_irq_init(irq + i); | |
404 | } | |
ced40d0f | 405 | |
e46cdb66 | 406 | return irq; |
d46a78b0 JF |
407 | } |
408 | ||
4892c9b4 RPM |
409 | static inline int __must_check xen_allocate_irq_dynamic(void) |
410 | { | |
411 | ||
412 | return xen_allocate_irqs_dynamic(1); | |
413 | } | |
414 | ||
7bee9768 | 415 | static int __must_check xen_allocate_irq_gsi(unsigned gsi) |
c9df1ce5 IC |
416 | { |
417 | int irq; | |
418 | ||
89911501 IC |
419 | /* |
420 | * A PV guest has no concept of a GSI (since it has no ACPI | |
421 | * nor access to/knowledge of the physical APICs). Therefore | |
422 | * all IRQs are dynamically allocated from the entire IRQ | |
423 | * space. | |
424 | */ | |
425 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
426 | return xen_allocate_irq_dynamic(); |
427 | ||
428 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
b4ff8389 | 429 | if (gsi < nr_legacy_irqs()) |
6cb6537d IC |
430 | irq = gsi; |
431 | else | |
432 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 433 | |
6cb6537d | 434 | xen_irq_init(irq); |
c9df1ce5 IC |
435 | |
436 | return irq; | |
437 | } | |
438 | ||
439 | static void xen_free_irq(unsigned irq) | |
440 | { | |
4d858574 | 441 | struct irq_info *info = info_for_irq(irq); |
6cb6537d | 442 | |
94032c50 KRW |
443 | if (WARN_ON(!info)) |
444 | return; | |
445 | ||
6cb6537d | 446 | list_del(&info->list); |
9158c358 | 447 | |
4d858574 | 448 | set_info_for_irq(irq, NULL); |
ca62ce8c | 449 | |
420eb554 DDG |
450 | WARN_ON(info->refcnt > 0); |
451 | ||
ca62ce8c IC |
452 | kfree(info); |
453 | ||
72146104 | 454 | /* Legacy IRQ descriptors are managed by the arch. */ |
b4ff8389 | 455 | if (irq < nr_legacy_irqs()) |
72146104 IC |
456 | return; |
457 | ||
c9df1ce5 IC |
458 | irq_free_desc(irq); |
459 | } | |
460 | ||
d0b075ff DV |
461 | static void xen_evtchn_close(unsigned int port) |
462 | { | |
463 | struct evtchn_close close; | |
464 | ||
465 | close.port = port; | |
466 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
467 | BUG(); | |
d0b075ff DV |
468 | } |
469 | ||
d46a78b0 JF |
470 | static void pirq_query_unmask(int irq) |
471 | { | |
472 | struct physdev_irq_status_query irq_status; | |
473 | struct irq_info *info = info_for_irq(irq); | |
474 | ||
475 | BUG_ON(info->type != IRQT_PIRQ); | |
476 | ||
7a043f11 | 477 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
478 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
479 | irq_status.flags = 0; | |
480 | ||
481 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
482 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
483 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
484 | } | |
485 | ||
7e186bdd SS |
486 | static void eoi_pirq(struct irq_data *data) |
487 | { | |
488 | int evtchn = evtchn_from_irq(data->irq); | |
489 | struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) }; | |
490 | int rc = 0; | |
491 | ||
ff1e22e7 BO |
492 | if (!VALID_EVTCHN(evtchn)) |
493 | return; | |
7e186bdd | 494 | |
f0f39387 RL |
495 | if (unlikely(irqd_is_setaffinity_pending(data)) && |
496 | likely(!irqd_irq_disabled(data))) { | |
ff1e22e7 BO |
497 | int masked = test_and_set_mask(evtchn); |
498 | ||
499 | clear_evtchn(evtchn); | |
500 | ||
501 | irq_move_masked_irq(data); | |
502 | ||
503 | if (!masked) | |
504 | unmask_evtchn(evtchn); | |
505 | } else | |
7e186bdd SS |
506 | clear_evtchn(evtchn); |
507 | ||
508 | if (pirq_needs_eoi(data->irq)) { | |
509 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
510 | WARN_ON(rc); | |
511 | } | |
512 | } | |
513 | ||
514 | static void mask_ack_pirq(struct irq_data *data) | |
515 | { | |
516 | disable_dynirq(data); | |
517 | eoi_pirq(data); | |
518 | } | |
519 | ||
c9e265e0 | 520 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
521 | { |
522 | struct evtchn_bind_pirq bind_pirq; | |
523 | struct irq_info *info = info_for_irq(irq); | |
524 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 525 | int rc; |
d46a78b0 JF |
526 | |
527 | BUG_ON(info->type != IRQT_PIRQ); | |
528 | ||
529 | if (VALID_EVTCHN(evtchn)) | |
530 | goto out; | |
531 | ||
7a043f11 | 532 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 533 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
534 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
535 | BIND_PIRQ__WILL_SHARE : 0; | |
536 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
537 | if (rc != 0) { | |
02893afd | 538 | pr_warn("Failed to obtain physical IRQ %d\n", irq); |
d46a78b0 JF |
539 | return 0; |
540 | } | |
541 | evtchn = bind_pirq.port; | |
542 | ||
543 | pirq_query_unmask(irq); | |
544 | ||
d0b075ff | 545 | rc = set_evtchn_to_irq(evtchn, irq); |
85e40b05 JG |
546 | if (rc) |
547 | goto err; | |
548 | ||
d46a78b0 | 549 | info->evtchn = evtchn; |
16e6bd59 | 550 | bind_evtchn_to_cpu(evtchn, 0); |
d46a78b0 | 551 | |
85e40b05 JG |
552 | rc = xen_evtchn_port_setup(info); |
553 | if (rc) | |
554 | goto err; | |
555 | ||
d46a78b0 JF |
556 | out: |
557 | unmask_evtchn(evtchn); | |
7e186bdd | 558 | eoi_pirq(irq_get_irq_data(irq)); |
d46a78b0 JF |
559 | |
560 | return 0; | |
85e40b05 JG |
561 | |
562 | err: | |
563 | pr_err("irq%d: Failed to set port to irq mapping (%d)\n", irq, rc); | |
564 | xen_evtchn_close(evtchn); | |
565 | return 0; | |
d46a78b0 JF |
566 | } |
567 | ||
c9e265e0 TG |
568 | static unsigned int startup_pirq(struct irq_data *data) |
569 | { | |
570 | return __startup_pirq(data->irq); | |
571 | } | |
572 | ||
573 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 | 574 | { |
c9e265e0 | 575 | unsigned int irq = data->irq; |
d46a78b0 | 576 | struct irq_info *info = info_for_irq(irq); |
d0b075ff | 577 | unsigned evtchn = evtchn_from_irq(irq); |
d46a78b0 JF |
578 | |
579 | BUG_ON(info->type != IRQT_PIRQ); | |
580 | ||
581 | if (!VALID_EVTCHN(evtchn)) | |
582 | return; | |
583 | ||
584 | mask_evtchn(evtchn); | |
d0b075ff DV |
585 | xen_evtchn_close(evtchn); |
586 | xen_irq_info_cleanup(info); | |
d46a78b0 JF |
587 | } |
588 | ||
c9e265e0 | 589 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 590 | { |
020db9d3 | 591 | enable_dynirq(data); |
d46a78b0 JF |
592 | } |
593 | ||
c9e265e0 | 594 | static void disable_pirq(struct irq_data *data) |
d46a78b0 | 595 | { |
7e186bdd | 596 | disable_dynirq(data); |
d46a78b0 JF |
597 | } |
598 | ||
68c2c39a | 599 | int xen_irq_from_gsi(unsigned gsi) |
d46a78b0 | 600 | { |
6cb6537d | 601 | struct irq_info *info; |
d46a78b0 | 602 | |
6cb6537d IC |
603 | list_for_each_entry(info, &xen_irq_list_head, list) { |
604 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
605 | continue; |
606 | ||
6cb6537d IC |
607 | if (info->u.pirq.gsi == gsi) |
608 | return info->irq; | |
d46a78b0 JF |
609 | } |
610 | ||
611 | return -1; | |
612 | } | |
68c2c39a | 613 | EXPORT_SYMBOL_GPL(xen_irq_from_gsi); |
d46a78b0 | 614 | |
96d4c588 DV |
615 | static void __unbind_from_irq(unsigned int irq) |
616 | { | |
96d4c588 | 617 | int evtchn = evtchn_from_irq(irq); |
4d858574 | 618 | struct irq_info *info = info_for_irq(irq); |
96d4c588 DV |
619 | |
620 | if (info->refcnt > 0) { | |
621 | info->refcnt--; | |
622 | if (info->refcnt != 0) | |
623 | return; | |
624 | } | |
625 | ||
626 | if (VALID_EVTCHN(evtchn)) { | |
d0b075ff DV |
627 | unsigned int cpu = cpu_from_irq(irq); |
628 | ||
629 | xen_evtchn_close(evtchn); | |
96d4c588 DV |
630 | |
631 | switch (type_from_irq(irq)) { | |
632 | case IRQT_VIRQ: | |
d0b075ff | 633 | per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1; |
96d4c588 DV |
634 | break; |
635 | case IRQT_IPI: | |
d0b075ff | 636 | per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1; |
96d4c588 DV |
637 | break; |
638 | default: | |
639 | break; | |
640 | } | |
641 | ||
d0b075ff | 642 | xen_irq_info_cleanup(info); |
96d4c588 DV |
643 | } |
644 | ||
96d4c588 DV |
645 | xen_free_irq(irq); |
646 | } | |
647 | ||
653378ac IC |
648 | /* |
649 | * Do not make any assumptions regarding the relationship between the | |
650 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
651 | * |
652 | * Note: We don't assign an event channel until the irq actually started | |
653 | * up. Return an existing irq if we've already got one for the gsi. | |
e5ac0bda SS |
654 | * |
655 | * Shareable implies level triggered, not shareable implies edge | |
656 | * triggered here. | |
d46a78b0 | 657 | */ |
f4d0635b IC |
658 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
659 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 660 | { |
a0e18116 | 661 | int irq = -1; |
d46a78b0 | 662 | struct physdev_irq irq_op; |
96d4c588 | 663 | int ret; |
d46a78b0 | 664 | |
77365948 | 665 | mutex_lock(&irq_mapping_update_lock); |
d46a78b0 | 666 | |
68c2c39a | 667 | irq = xen_irq_from_gsi(gsi); |
d46a78b0 | 668 | if (irq != -1) { |
283c0972 JP |
669 | pr_info("%s: returning irq %d for gsi %u\n", |
670 | __func__, irq, gsi); | |
420eb554 | 671 | goto out; |
d46a78b0 JF |
672 | } |
673 | ||
c9df1ce5 | 674 | irq = xen_allocate_irq_gsi(gsi); |
7bee9768 IC |
675 | if (irq < 0) |
676 | goto out; | |
d46a78b0 | 677 | |
d46a78b0 | 678 | irq_op.irq = irq; |
b5401a96 AN |
679 | irq_op.vector = 0; |
680 | ||
681 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
682 | * driver provides a PCI bus that does the call to do exactly | |
683 | * this in the priv domain. */ | |
684 | if (xen_initial_domain() && | |
685 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 686 | xen_free_irq(irq); |
d46a78b0 JF |
687 | irq = -ENOSPC; |
688 | goto out; | |
689 | } | |
690 | ||
96d4c588 | 691 | ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF, |
9158c358 | 692 | shareable ? PIRQ_SHAREABLE : 0); |
96d4c588 DV |
693 | if (ret < 0) { |
694 | __unbind_from_irq(irq); | |
695 | irq = ret; | |
696 | goto out; | |
697 | } | |
d46a78b0 | 698 | |
7e186bdd SS |
699 | pirq_query_unmask(irq); |
700 | /* We try to use the handler with the appropriate semantic for the | |
e5ac0bda SS |
701 | * type of interrupt: if the interrupt is an edge triggered |
702 | * interrupt we use handle_edge_irq. | |
7e186bdd | 703 | * |
e5ac0bda SS |
704 | * On the other hand if the interrupt is level triggered we use |
705 | * handle_fasteoi_irq like the native code does for this kind of | |
7e186bdd | 706 | * interrupts. |
e5ac0bda | 707 | * |
7e186bdd SS |
708 | * Depending on the Xen version, pirq_needs_eoi might return true |
709 | * not only for level triggered interrupts but for edge triggered | |
710 | * interrupts too. In any case Xen always honors the eoi mechanism, | |
711 | * not injecting any more pirqs of the same kind if the first one | |
712 | * hasn't received an eoi yet. Therefore using the fasteoi handler | |
713 | * is the right choice either way. | |
714 | */ | |
e5ac0bda | 715 | if (shareable) |
7e186bdd SS |
716 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, |
717 | handle_fasteoi_irq, name); | |
718 | else | |
719 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, | |
720 | handle_edge_irq, name); | |
721 | ||
d46a78b0 | 722 | out: |
77365948 | 723 | mutex_unlock(&irq_mapping_update_lock); |
d46a78b0 JF |
724 | |
725 | return irq; | |
726 | } | |
727 | ||
f731e3ef | 728 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 729 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 730 | { |
5cad61a6 | 731 | int rc; |
cbf6aa89 | 732 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 733 | |
bf480d95 | 734 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 735 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 736 | |
5cad61a6 IC |
737 | WARN_ONCE(rc == -ENOSYS, |
738 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
739 | ||
740 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
741 | } |
742 | ||
bf480d95 | 743 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
4892c9b4 | 744 | int pirq, int nvec, const char *name, domid_t domid) |
809f9267 | 745 | { |
4892c9b4 | 746 | int i, irq, ret; |
4b41df7f | 747 | |
77365948 | 748 | mutex_lock(&irq_mapping_update_lock); |
809f9267 | 749 | |
4892c9b4 | 750 | irq = xen_allocate_irqs_dynamic(nvec); |
e6599225 | 751 | if (irq < 0) |
bb5d079a | 752 | goto out; |
809f9267 | 753 | |
4892c9b4 RPM |
754 | for (i = 0; i < nvec; i++) { |
755 | irq_set_chip_and_handler_name(irq + i, &xen_pirq_chip, handle_edge_irq, name); | |
756 | ||
757 | ret = xen_irq_info_pirq_setup(irq + i, 0, pirq + i, 0, domid, | |
758 | i == 0 ? 0 : PIRQ_MSI_GROUP); | |
759 | if (ret < 0) | |
760 | goto error_irq; | |
761 | } | |
809f9267 | 762 | |
5f6fb454 | 763 | ret = irq_set_msi_desc(irq, msidesc); |
bf480d95 IC |
764 | if (ret < 0) |
765 | goto error_irq; | |
809f9267 | 766 | out: |
77365948 | 767 | mutex_unlock(&irq_mapping_update_lock); |
4b41df7f | 768 | return irq; |
bf480d95 | 769 | error_irq: |
910f8bef RPM |
770 | while (nvec--) |
771 | __unbind_from_irq(irq + nvec); | |
77365948 | 772 | mutex_unlock(&irq_mapping_update_lock); |
e6599225 | 773 | return ret; |
809f9267 | 774 | } |
f731e3ef QH |
775 | #endif |
776 | ||
b5401a96 AN |
777 | int xen_destroy_irq(int irq) |
778 | { | |
38aa66fc JF |
779 | struct physdev_unmap_pirq unmap_irq; |
780 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
781 | int rc = -ENOENT; |
782 | ||
77365948 | 783 | mutex_lock(&irq_mapping_update_lock); |
b5401a96 | 784 | |
4892c9b4 RPM |
785 | /* |
786 | * If trying to remove a vector in a MSI group different | |
787 | * than the first one skip the PIRQ unmap unless this vector | |
788 | * is the first one in the group. | |
789 | */ | |
790 | if (xen_initial_domain() && !(info->u.pirq.flags & PIRQ_MSI_GROUP)) { | |
12334715 | 791 | unmap_irq.pirq = info->u.pirq.pirq; |
beafbdc1 | 792 | unmap_irq.domid = info->u.pirq.domid; |
38aa66fc | 793 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); |
1eff1ad0 KRW |
794 | /* If another domain quits without making the pci_disable_msix |
795 | * call, the Xen hypervisor takes care of freeing the PIRQs | |
796 | * (free_domain_pirqs). | |
797 | */ | |
798 | if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF)) | |
283c0972 | 799 | pr_info("domain %d does not have %d anymore\n", |
1eff1ad0 KRW |
800 | info->u.pirq.domid, info->u.pirq.pirq); |
801 | else if (rc) { | |
283c0972 | 802 | pr_warn("unmap irq failed %d\n", rc); |
38aa66fc JF |
803 | goto out; |
804 | } | |
805 | } | |
b5401a96 | 806 | |
c9df1ce5 | 807 | xen_free_irq(irq); |
b5401a96 AN |
808 | |
809 | out: | |
77365948 | 810 | mutex_unlock(&irq_mapping_update_lock); |
b5401a96 AN |
811 | return rc; |
812 | } | |
813 | ||
af42b8d1 | 814 | int xen_irq_from_pirq(unsigned pirq) |
d46a78b0 | 815 | { |
69c358ce | 816 | int irq; |
d46a78b0 | 817 | |
69c358ce | 818 | struct irq_info *info; |
e46cdb66 | 819 | |
77365948 | 820 | mutex_lock(&irq_mapping_update_lock); |
69c358ce IC |
821 | |
822 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
9bb9efe4 | 823 | if (info->type != IRQT_PIRQ) |
69c358ce IC |
824 | continue; |
825 | irq = info->irq; | |
826 | if (info->u.pirq.pirq == pirq) | |
827 | goto out; | |
828 | } | |
829 | irq = -1; | |
830 | out: | |
77365948 | 831 | mutex_unlock(&irq_mapping_update_lock); |
69c358ce IC |
832 | |
833 | return irq; | |
af42b8d1 SS |
834 | } |
835 | ||
e6197acc KRW |
836 | |
837 | int xen_pirq_from_irq(unsigned irq) | |
838 | { | |
839 | return pirq_from_irq(irq); | |
840 | } | |
841 | EXPORT_SYMBOL_GPL(xen_pirq_from_irq); | |
96d4c588 | 842 | |
b536b4b9 | 843 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
844 | { |
845 | int irq; | |
96d4c588 | 846 | int ret; |
e46cdb66 | 847 | |
d0b075ff DV |
848 | if (evtchn >= xen_evtchn_max_channels()) |
849 | return -ENOMEM; | |
850 | ||
77365948 | 851 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 | 852 | |
d0b075ff | 853 | irq = get_evtchn_to_irq(evtchn); |
e46cdb66 JF |
854 | |
855 | if (irq == -1) { | |
c9df1ce5 | 856 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 857 | if (irq < 0) |
7bee9768 | 858 | goto out; |
e46cdb66 | 859 | |
c442b806 | 860 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, |
7e186bdd | 861 | handle_edge_irq, "event"); |
e46cdb66 | 862 | |
96d4c588 DV |
863 | ret = xen_irq_info_evtchn_setup(irq, evtchn); |
864 | if (ret < 0) { | |
865 | __unbind_from_irq(irq); | |
866 | irq = ret; | |
867 | goto out; | |
868 | } | |
97253eee DV |
869 | /* New interdomain events are bound to VCPU 0. */ |
870 | bind_evtchn_to_cpu(evtchn, 0); | |
5e152e6c KRW |
871 | } else { |
872 | struct irq_info *info = info_for_irq(irq); | |
873 | WARN_ON(info == NULL || info->type != IRQT_EVTCHN); | |
e46cdb66 JF |
874 | } |
875 | ||
7bee9768 | 876 | out: |
77365948 | 877 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
878 | |
879 | return irq; | |
880 | } | |
b536b4b9 | 881 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 882 | |
f87e4cac JF |
883 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
884 | { | |
885 | struct evtchn_bind_ipi bind_ipi; | |
886 | int evtchn, irq; | |
96d4c588 | 887 | int ret; |
f87e4cac | 888 | |
77365948 | 889 | mutex_lock(&irq_mapping_update_lock); |
f87e4cac JF |
890 | |
891 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 892 | |
f87e4cac | 893 | if (irq == -1) { |
c9df1ce5 | 894 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
895 | if (irq < 0) |
896 | goto out; | |
897 | ||
c442b806 | 898 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
aaca4964 | 899 | handle_percpu_irq, "ipi"); |
f87e4cac | 900 | |
8058c0b8 | 901 | bind_ipi.vcpu = xen_vcpu_nr(cpu); |
f87e4cac JF |
902 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, |
903 | &bind_ipi) != 0) | |
904 | BUG(); | |
905 | evtchn = bind_ipi.port; | |
906 | ||
96d4c588 DV |
907 | ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
908 | if (ret < 0) { | |
909 | __unbind_from_irq(irq); | |
910 | irq = ret; | |
911 | goto out; | |
912 | } | |
f87e4cac | 913 | bind_evtchn_to_cpu(evtchn, cpu); |
5e152e6c KRW |
914 | } else { |
915 | struct irq_info *info = info_for_irq(irq); | |
916 | WARN_ON(info == NULL || info->type != IRQT_IPI); | |
f87e4cac JF |
917 | } |
918 | ||
f87e4cac | 919 | out: |
77365948 | 920 | mutex_unlock(&irq_mapping_update_lock); |
f87e4cac JF |
921 | return irq; |
922 | } | |
923 | ||
854072dd JG |
924 | int bind_interdomain_evtchn_to_irq(unsigned int remote_domain, |
925 | unsigned int remote_port) | |
2e820f58 IC |
926 | { |
927 | struct evtchn_bind_interdomain bind_interdomain; | |
928 | int err; | |
929 | ||
930 | bind_interdomain.remote_dom = remote_domain; | |
931 | bind_interdomain.remote_port = remote_port; | |
932 | ||
933 | err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, | |
934 | &bind_interdomain); | |
935 | ||
936 | return err ? : bind_evtchn_to_irq(bind_interdomain.local_port); | |
937 | } | |
854072dd | 938 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irq); |
2e820f58 | 939 | |
62cc5fc7 OH |
940 | static int find_virq(unsigned int virq, unsigned int cpu) |
941 | { | |
942 | struct evtchn_status status; | |
943 | int port, rc = -ENOENT; | |
944 | ||
945 | memset(&status, 0, sizeof(status)); | |
d0b075ff | 946 | for (port = 0; port < xen_evtchn_max_channels(); port++) { |
62cc5fc7 OH |
947 | status.dom = DOMID_SELF; |
948 | status.port = port; | |
949 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status); | |
950 | if (rc < 0) | |
951 | continue; | |
952 | if (status.status != EVTCHNSTAT_virq) | |
953 | continue; | |
b36585a0 | 954 | if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) { |
62cc5fc7 OH |
955 | rc = port; |
956 | break; | |
957 | } | |
958 | } | |
959 | return rc; | |
960 | } | |
f87e4cac | 961 | |
0dc0064a DV |
962 | /** |
963 | * xen_evtchn_nr_channels - number of usable event channel ports | |
964 | * | |
965 | * This may be less than the maximum supported by the current | |
966 | * hypervisor ABI. Use xen_evtchn_max_channels() for the maximum | |
967 | * supported. | |
968 | */ | |
969 | unsigned xen_evtchn_nr_channels(void) | |
970 | { | |
971 | return evtchn_ops->nr_channels(); | |
972 | } | |
973 | EXPORT_SYMBOL_GPL(xen_evtchn_nr_channels); | |
974 | ||
77bb3dfd | 975 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu, bool percpu) |
e46cdb66 JF |
976 | { |
977 | struct evtchn_bind_virq bind_virq; | |
62cc5fc7 | 978 | int evtchn, irq, ret; |
e46cdb66 | 979 | |
77365948 | 980 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
981 | |
982 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
983 | ||
984 | if (irq == -1) { | |
c9df1ce5 | 985 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 986 | if (irq < 0) |
7bee9768 | 987 | goto out; |
a52521f1 | 988 | |
77bb3dfd DV |
989 | if (percpu) |
990 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, | |
991 | handle_percpu_irq, "virq"); | |
992 | else | |
993 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, | |
994 | handle_edge_irq, "virq"); | |
a52521f1 | 995 | |
e46cdb66 | 996 | bind_virq.virq = virq; |
8058c0b8 | 997 | bind_virq.vcpu = xen_vcpu_nr(cpu); |
62cc5fc7 OH |
998 | ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
999 | &bind_virq); | |
1000 | if (ret == 0) | |
1001 | evtchn = bind_virq.port; | |
1002 | else { | |
1003 | if (ret == -EEXIST) | |
1004 | ret = find_virq(virq, cpu); | |
1005 | BUG_ON(ret < 0); | |
1006 | evtchn = ret; | |
1007 | } | |
e46cdb66 | 1008 | |
96d4c588 DV |
1009 | ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
1010 | if (ret < 0) { | |
1011 | __unbind_from_irq(irq); | |
1012 | irq = ret; | |
1013 | goto out; | |
1014 | } | |
e46cdb66 JF |
1015 | |
1016 | bind_evtchn_to_cpu(evtchn, cpu); | |
5e152e6c KRW |
1017 | } else { |
1018 | struct irq_info *info = info_for_irq(irq); | |
1019 | WARN_ON(info == NULL || info->type != IRQT_VIRQ); | |
e46cdb66 JF |
1020 | } |
1021 | ||
7bee9768 | 1022 | out: |
77365948 | 1023 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1024 | |
1025 | return irq; | |
1026 | } | |
1027 | ||
1028 | static void unbind_from_irq(unsigned int irq) | |
1029 | { | |
77365948 | 1030 | mutex_lock(&irq_mapping_update_lock); |
96d4c588 | 1031 | __unbind_from_irq(irq); |
77365948 | 1032 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1033 | } |
1034 | ||
1035 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 1036 | irq_handler_t handler, |
e46cdb66 JF |
1037 | unsigned long irqflags, |
1038 | const char *devname, void *dev_id) | |
1039 | { | |
361ae8cb | 1040 | int irq, retval; |
e46cdb66 JF |
1041 | |
1042 | irq = bind_evtchn_to_irq(evtchn); | |
7bee9768 IC |
1043 | if (irq < 0) |
1044 | return irq; | |
e46cdb66 JF |
1045 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1046 | if (retval != 0) { | |
1047 | unbind_from_irq(irq); | |
1048 | return retval; | |
1049 | } | |
1050 | ||
1051 | return irq; | |
1052 | } | |
1053 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
1054 | ||
2e820f58 IC |
1055 | int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain, |
1056 | unsigned int remote_port, | |
1057 | irq_handler_t handler, | |
1058 | unsigned long irqflags, | |
1059 | const char *devname, | |
1060 | void *dev_id) | |
1061 | { | |
1062 | int irq, retval; | |
1063 | ||
1064 | irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port); | |
1065 | if (irq < 0) | |
1066 | return irq; | |
1067 | ||
1068 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
1069 | if (retval != 0) { | |
1070 | unbind_from_irq(irq); | |
1071 | return retval; | |
1072 | } | |
1073 | ||
1074 | return irq; | |
1075 | } | |
1076 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler); | |
1077 | ||
e46cdb66 | 1078 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, |
7c239975 | 1079 | irq_handler_t handler, |
e46cdb66 JF |
1080 | unsigned long irqflags, const char *devname, void *dev_id) |
1081 | { | |
361ae8cb | 1082 | int irq, retval; |
e46cdb66 | 1083 | |
77bb3dfd | 1084 | irq = bind_virq_to_irq(virq, cpu, irqflags & IRQF_PERCPU); |
7bee9768 IC |
1085 | if (irq < 0) |
1086 | return irq; | |
e46cdb66 JF |
1087 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1088 | if (retval != 0) { | |
1089 | unbind_from_irq(irq); | |
1090 | return retval; | |
1091 | } | |
1092 | ||
1093 | return irq; | |
1094 | } | |
1095 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
1096 | ||
f87e4cac JF |
1097 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
1098 | unsigned int cpu, | |
1099 | irq_handler_t handler, | |
1100 | unsigned long irqflags, | |
1101 | const char *devname, | |
1102 | void *dev_id) | |
1103 | { | |
1104 | int irq, retval; | |
1105 | ||
1106 | irq = bind_ipi_to_irq(ipi, cpu); | |
1107 | if (irq < 0) | |
1108 | return irq; | |
1109 | ||
9bab0b7f | 1110 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME; |
f87e4cac JF |
1111 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1112 | if (retval != 0) { | |
1113 | unbind_from_irq(irq); | |
1114 | return retval; | |
1115 | } | |
1116 | ||
1117 | return irq; | |
1118 | } | |
1119 | ||
e46cdb66 JF |
1120 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
1121 | { | |
4d858574 | 1122 | struct irq_info *info = info_for_irq(irq); |
94032c50 KRW |
1123 | |
1124 | if (WARN_ON(!info)) | |
1125 | return; | |
e46cdb66 JF |
1126 | free_irq(irq, dev_id); |
1127 | unbind_from_irq(irq); | |
1128 | } | |
1129 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1130 | ||
6ccecb0f DV |
1131 | /** |
1132 | * xen_set_irq_priority() - set an event channel priority. | |
1133 | * @irq:irq bound to an event channel. | |
1134 | * @priority: priority between XEN_IRQ_PRIORITY_MAX and XEN_IRQ_PRIORITY_MIN. | |
1135 | */ | |
1136 | int xen_set_irq_priority(unsigned irq, unsigned priority) | |
1137 | { | |
1138 | struct evtchn_set_priority set_priority; | |
1139 | ||
1140 | set_priority.port = evtchn_from_irq(irq); | |
1141 | set_priority.priority = priority; | |
1142 | ||
1143 | return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority, | |
1144 | &set_priority); | |
1145 | } | |
1146 | EXPORT_SYMBOL_GPL(xen_set_irq_priority); | |
1147 | ||
420eb554 DDG |
1148 | int evtchn_make_refcounted(unsigned int evtchn) |
1149 | { | |
d0b075ff | 1150 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1151 | struct irq_info *info; |
1152 | ||
1153 | if (irq == -1) | |
1154 | return -ENOENT; | |
1155 | ||
4d858574 | 1156 | info = info_for_irq(irq); |
420eb554 DDG |
1157 | |
1158 | if (!info) | |
1159 | return -ENOENT; | |
1160 | ||
1161 | WARN_ON(info->refcnt != -1); | |
1162 | ||
1163 | info->refcnt = 1; | |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | EXPORT_SYMBOL_GPL(evtchn_make_refcounted); | |
1168 | ||
1169 | int evtchn_get(unsigned int evtchn) | |
1170 | { | |
1171 | int irq; | |
1172 | struct irq_info *info; | |
1173 | int err = -ENOENT; | |
1174 | ||
d0b075ff | 1175 | if (evtchn >= xen_evtchn_max_channels()) |
c3b3f16d DDG |
1176 | return -EINVAL; |
1177 | ||
420eb554 DDG |
1178 | mutex_lock(&irq_mapping_update_lock); |
1179 | ||
d0b075ff | 1180 | irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1181 | if (irq == -1) |
1182 | goto done; | |
1183 | ||
4d858574 | 1184 | info = info_for_irq(irq); |
420eb554 DDG |
1185 | |
1186 | if (!info) | |
1187 | goto done; | |
1188 | ||
1189 | err = -EINVAL; | |
1190 | if (info->refcnt <= 0) | |
1191 | goto done; | |
1192 | ||
1193 | info->refcnt++; | |
1194 | err = 0; | |
1195 | done: | |
1196 | mutex_unlock(&irq_mapping_update_lock); | |
1197 | ||
1198 | return err; | |
1199 | } | |
1200 | EXPORT_SYMBOL_GPL(evtchn_get); | |
1201 | ||
1202 | void evtchn_put(unsigned int evtchn) | |
1203 | { | |
d0b075ff | 1204 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1205 | if (WARN_ON(irq == -1)) |
1206 | return; | |
1207 | unbind_from_irq(irq); | |
1208 | } | |
1209 | EXPORT_SYMBOL_GPL(evtchn_put); | |
1210 | ||
f87e4cac JF |
1211 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1212 | { | |
6efa20e4 KRW |
1213 | int irq; |
1214 | ||
072b2064 | 1215 | #ifdef CONFIG_X86 |
6efa20e4 | 1216 | if (unlikely(vector == XEN_NMI_VECTOR)) { |
ad5475f9 VK |
1217 | int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, xen_vcpu_nr(cpu), |
1218 | NULL); | |
6efa20e4 KRW |
1219 | if (rc < 0) |
1220 | printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc); | |
1221 | return; | |
1222 | } | |
072b2064 | 1223 | #endif |
6efa20e4 | 1224 | irq = per_cpu(ipi_to_irq, cpu)[vector]; |
f87e4cac JF |
1225 | BUG_ON(irq < 0); |
1226 | notify_remote_via_irq(irq); | |
1227 | } | |
1228 | ||
245b2e70 TH |
1229 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1230 | ||
38e20b07 | 1231 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 | 1232 | { |
780f36d8 | 1233 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
9a489f45 | 1234 | int cpu = get_cpu(); |
088c05a8 | 1235 | unsigned count; |
e46cdb66 | 1236 | |
229664be | 1237 | do { |
229664be | 1238 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1239 | |
b2e4ae69 | 1240 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1241 | goto out; |
e46cdb66 | 1242 | |
9a489f45 | 1243 | xen_evtchn_handle_events(cpu); |
e46cdb66 | 1244 | |
229664be JF |
1245 | BUG_ON(!irqs_disabled()); |
1246 | ||
780f36d8 CL |
1247 | count = __this_cpu_read(xed_nesting_count); |
1248 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1249 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1250 | |
1251 | out: | |
38e20b07 SY |
1252 | |
1253 | put_cpu(); | |
1254 | } | |
1255 | ||
1256 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1257 | { | |
1258 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1259 | ||
772aebce | 1260 | irq_enter(); |
0ec53ecf | 1261 | #ifdef CONFIG_X86 |
99c8b79d | 1262 | inc_irq_stat(irq_hv_callback_count); |
d06eb3ee | 1263 | #endif |
38e20b07 SY |
1264 | |
1265 | __xen_evtchn_do_upcall(); | |
1266 | ||
3445a8fd JF |
1267 | irq_exit(); |
1268 | set_irq_regs(old_regs); | |
38e20b07 | 1269 | } |
3445a8fd | 1270 | |
38e20b07 SY |
1271 | void xen_hvm_evtchn_do_upcall(void) |
1272 | { | |
1273 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1274 | } |
183d03cc | 1275 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1276 | |
eb1e305f JF |
1277 | /* Rebind a new event channel to an existing irq. */ |
1278 | void rebind_evtchn_irq(int evtchn, int irq) | |
1279 | { | |
d77bbd4d JF |
1280 | struct irq_info *info = info_for_irq(irq); |
1281 | ||
94032c50 KRW |
1282 | if (WARN_ON(!info)) |
1283 | return; | |
1284 | ||
eb1e305f JF |
1285 | /* Make sure the irq is masked, since the new event channel |
1286 | will also be masked. */ | |
1287 | disable_irq(irq); | |
1288 | ||
77365948 | 1289 | mutex_lock(&irq_mapping_update_lock); |
eb1e305f JF |
1290 | |
1291 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
d0b075ff | 1292 | BUG_ON(get_evtchn_to_irq(evtchn) != -1); |
eb1e305f | 1293 | /* Expect irq to have been bound before, |
d77bbd4d JF |
1294 | so there should be a proper type */ |
1295 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1296 | |
96d4c588 | 1297 | (void)xen_irq_info_evtchn_setup(irq, evtchn); |
eb1e305f | 1298 | |
77365948 | 1299 | mutex_unlock(&irq_mapping_update_lock); |
eb1e305f | 1300 | |
5cec9883 BO |
1301 | bind_evtchn_to_cpu(evtchn, info->cpu); |
1302 | /* This will be deferred until interrupt is processed */ | |
1303 | irq_set_affinity(irq, cpumask_of(info->cpu)); | |
eb1e305f JF |
1304 | |
1305 | /* Unmask the event channel. */ | |
1306 | enable_irq(irq); | |
1307 | } | |
1308 | ||
e46cdb66 | 1309 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
bce5963b | 1310 | static int xen_rebind_evtchn_to_cpu(int evtchn, unsigned int tcpu) |
e46cdb66 JF |
1311 | { |
1312 | struct evtchn_bind_vcpu bind_vcpu; | |
4704fe4f | 1313 | int masked; |
e46cdb66 | 1314 | |
be49472f IC |
1315 | if (!VALID_EVTCHN(evtchn)) |
1316 | return -1; | |
1317 | ||
84d582d2 BO |
1318 | if (!xen_support_evtchn_rebind()) |
1319 | return -1; | |
1320 | ||
e46cdb66 JF |
1321 | /* Send future instances of this interrupt to other vcpu. */ |
1322 | bind_vcpu.port = evtchn; | |
8058c0b8 | 1323 | bind_vcpu.vcpu = xen_vcpu_nr(tcpu); |
e46cdb66 | 1324 | |
4704fe4f DV |
1325 | /* |
1326 | * Mask the event while changing the VCPU binding to prevent | |
1327 | * it being delivered on an unexpected VCPU. | |
1328 | */ | |
3f70fa82 | 1329 | masked = test_and_set_mask(evtchn); |
4704fe4f | 1330 | |
e46cdb66 JF |
1331 | /* |
1332 | * If this fails, it usually just indicates that we're dealing with a | |
1333 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1334 | * it, but don't do the xenlinux-level rebind in that case. | |
1335 | */ | |
1336 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1337 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1338 | |
4704fe4f DV |
1339 | if (!masked) |
1340 | unmask_evtchn(evtchn); | |
1341 | ||
d5dedd45 YL |
1342 | return 0; |
1343 | } | |
e46cdb66 | 1344 | |
c9e265e0 TG |
1345 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1346 | bool force) | |
e46cdb66 | 1347 | { |
753fbd23 | 1348 | unsigned tcpu = cpumask_first_and(dest, cpu_online_mask); |
6e6c5b96 | 1349 | int ret = xen_rebind_evtchn_to_cpu(evtchn_from_irq(data->irq), tcpu); |
d5dedd45 | 1350 | |
ef1c2cc8 TG |
1351 | if (!ret) |
1352 | irq_data_update_effective_affinity(data, cpumask_of(tcpu)); | |
1353 | ||
1354 | return ret; | |
e46cdb66 JF |
1355 | } |
1356 | ||
bce5963b JG |
1357 | /* To be called with desc->lock held. */ |
1358 | int xen_set_affinity_evtchn(struct irq_desc *desc, unsigned int tcpu) | |
1359 | { | |
1360 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1361 | ||
1362 | return set_affinity_irq(d, cpumask_of(tcpu), false); | |
1363 | } | |
1364 | EXPORT_SYMBOL_GPL(xen_set_affinity_evtchn); | |
1365 | ||
c9e265e0 | 1366 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1367 | { |
c9e265e0 | 1368 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1369 | |
1370 | if (VALID_EVTCHN(evtchn)) | |
1371 | unmask_evtchn(evtchn); | |
1372 | } | |
1373 | ||
c9e265e0 | 1374 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1375 | { |
c9e265e0 | 1376 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1377 | |
1378 | if (VALID_EVTCHN(evtchn)) | |
1379 | mask_evtchn(evtchn); | |
1380 | } | |
1381 | ||
c9e265e0 | 1382 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1383 | { |
c9e265e0 | 1384 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1385 | |
ff1e22e7 BO |
1386 | if (!VALID_EVTCHN(evtchn)) |
1387 | return; | |
e46cdb66 | 1388 | |
f0f39387 RL |
1389 | if (unlikely(irqd_is_setaffinity_pending(data)) && |
1390 | likely(!irqd_irq_disabled(data))) { | |
ff1e22e7 BO |
1391 | int masked = test_and_set_mask(evtchn); |
1392 | ||
1393 | clear_evtchn(evtchn); | |
1394 | ||
1395 | irq_move_masked_irq(data); | |
1396 | ||
1397 | if (!masked) | |
1398 | unmask_evtchn(evtchn); | |
1399 | } else | |
7e186bdd SS |
1400 | clear_evtchn(evtchn); |
1401 | } | |
1402 | ||
1403 | static void mask_ack_dynirq(struct irq_data *data) | |
1404 | { | |
1405 | disable_dynirq(data); | |
1406 | ack_dynirq(data); | |
e46cdb66 JF |
1407 | } |
1408 | ||
c9e265e0 | 1409 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1410 | { |
4640ddf5 DV |
1411 | unsigned int evtchn = evtchn_from_irq(data->irq); |
1412 | int masked; | |
1413 | ||
1414 | if (!VALID_EVTCHN(evtchn)) | |
1415 | return 0; | |
1416 | ||
1417 | masked = test_and_set_mask(evtchn); | |
1418 | set_evtchn(evtchn); | |
1419 | if (!masked) | |
1420 | unmask_evtchn(evtchn); | |
1421 | ||
1422 | return 1; | |
e46cdb66 JF |
1423 | } |
1424 | ||
0a85226f | 1425 | static void restore_pirqs(void) |
9a069c33 SS |
1426 | { |
1427 | int pirq, rc, irq, gsi; | |
1428 | struct physdev_map_pirq map_irq; | |
69c358ce | 1429 | struct irq_info *info; |
9a069c33 | 1430 | |
69c358ce IC |
1431 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1432 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1433 | continue; |
1434 | ||
69c358ce IC |
1435 | pirq = info->u.pirq.pirq; |
1436 | gsi = info->u.pirq.gsi; | |
1437 | irq = info->irq; | |
1438 | ||
9a069c33 SS |
1439 | /* save/restore of PT devices doesn't work, so at this point the |
1440 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1441 | if (!gsi) |
1442 | continue; | |
1443 | ||
1444 | map_irq.domid = DOMID_SELF; | |
1445 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1446 | map_irq.index = gsi; | |
1447 | map_irq.pirq = pirq; | |
1448 | ||
1449 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1450 | if (rc) { | |
283c0972 JP |
1451 | pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", |
1452 | gsi, irq, pirq, rc); | |
9158c358 | 1453 | xen_free_irq(irq); |
9a069c33 SS |
1454 | continue; |
1455 | } | |
1456 | ||
1457 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1458 | ||
c9e265e0 | 1459 | __startup_pirq(irq); |
9a069c33 SS |
1460 | } |
1461 | } | |
1462 | ||
0e91398f JF |
1463 | static void restore_cpu_virqs(unsigned int cpu) |
1464 | { | |
1465 | struct evtchn_bind_virq bind_virq; | |
1466 | int virq, irq, evtchn; | |
1467 | ||
1468 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1469 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1470 | continue; | |
1471 | ||
ced40d0f | 1472 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1473 | |
1474 | /* Get a new binding from Xen. */ | |
1475 | bind_virq.virq = virq; | |
8058c0b8 | 1476 | bind_virq.vcpu = xen_vcpu_nr(cpu); |
0e91398f JF |
1477 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
1478 | &bind_virq) != 0) | |
1479 | BUG(); | |
1480 | evtchn = bind_virq.port; | |
1481 | ||
1482 | /* Record the new mapping. */ | |
96d4c588 | 1483 | (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
0e91398f | 1484 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1485 | } |
1486 | } | |
1487 | ||
1488 | static void restore_cpu_ipis(unsigned int cpu) | |
1489 | { | |
1490 | struct evtchn_bind_ipi bind_ipi; | |
1491 | int ipi, irq, evtchn; | |
1492 | ||
1493 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1494 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1495 | continue; | |
1496 | ||
ced40d0f | 1497 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1498 | |
1499 | /* Get a new binding from Xen. */ | |
8058c0b8 | 1500 | bind_ipi.vcpu = xen_vcpu_nr(cpu); |
0e91398f JF |
1501 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, |
1502 | &bind_ipi) != 0) | |
1503 | BUG(); | |
1504 | evtchn = bind_ipi.port; | |
1505 | ||
1506 | /* Record the new mapping. */ | |
96d4c588 | 1507 | (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
0e91398f | 1508 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1509 | } |
1510 | } | |
1511 | ||
2d9e1e2f JF |
1512 | /* Clear an irq's pending state, in preparation for polling on it */ |
1513 | void xen_clear_irq_pending(int irq) | |
1514 | { | |
1515 | int evtchn = evtchn_from_irq(irq); | |
1516 | ||
1517 | if (VALID_EVTCHN(evtchn)) | |
1518 | clear_evtchn(evtchn); | |
1519 | } | |
d9a8814f | 1520 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1521 | void xen_set_irq_pending(int irq) |
1522 | { | |
1523 | int evtchn = evtchn_from_irq(irq); | |
1524 | ||
1525 | if (VALID_EVTCHN(evtchn)) | |
1526 | set_evtchn(evtchn); | |
1527 | } | |
1528 | ||
1529 | bool xen_test_irq_pending(int irq) | |
1530 | { | |
1531 | int evtchn = evtchn_from_irq(irq); | |
1532 | bool ret = false; | |
1533 | ||
1534 | if (VALID_EVTCHN(evtchn)) | |
1535 | ret = test_evtchn(evtchn); | |
1536 | ||
1537 | return ret; | |
1538 | } | |
1539 | ||
d9a8814f KRW |
1540 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1541 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1542 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1543 | { |
1544 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1545 | ||
1546 | if (VALID_EVTCHN(evtchn)) { | |
1547 | struct sched_poll poll; | |
1548 | ||
1549 | poll.nr_ports = 1; | |
d9a8814f | 1550 | poll.timeout = timeout; |
ff3c5362 | 1551 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1552 | |
1553 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1554 | BUG(); | |
1555 | } | |
1556 | } | |
d9a8814f KRW |
1557 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1558 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1559 | * irq will be disabled so it won't deliver an interrupt. */ | |
1560 | void xen_poll_irq(int irq) | |
1561 | { | |
1562 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1563 | } | |
2d9e1e2f | 1564 | |
c7c2c3a2 KRW |
1565 | /* Check whether the IRQ line is shared with other guests. */ |
1566 | int xen_test_irq_shared(int irq) | |
1567 | { | |
1568 | struct irq_info *info = info_for_irq(irq); | |
94032c50 KRW |
1569 | struct physdev_irq_status_query irq_status; |
1570 | ||
1571 | if (WARN_ON(!info)) | |
1572 | return -ENOENT; | |
1573 | ||
1574 | irq_status.irq = info->u.pirq.pirq; | |
c7c2c3a2 KRW |
1575 | |
1576 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) | |
1577 | return 0; | |
1578 | return !(irq_status.flags & XENIRQSTAT_shared); | |
1579 | } | |
1580 | EXPORT_SYMBOL_GPL(xen_test_irq_shared); | |
1581 | ||
0e91398f JF |
1582 | void xen_irq_resume(void) |
1583 | { | |
fd21069d | 1584 | unsigned int cpu; |
6cb6537d | 1585 | struct irq_info *info; |
0e91398f | 1586 | |
0e91398f | 1587 | /* New event-channel space is not 'live' yet. */ |
1fe56551 | 1588 | xen_evtchn_resume(); |
0e91398f JF |
1589 | |
1590 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1591 | list_for_each_entry(info, &xen_irq_list_head, list) |
1592 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f | 1593 | |
d0b075ff | 1594 | clear_evtchn_to_irq_all(); |
0e91398f JF |
1595 | |
1596 | for_each_possible_cpu(cpu) { | |
1597 | restore_cpu_virqs(cpu); | |
1598 | restore_cpu_ipis(cpu); | |
1599 | } | |
6903591f | 1600 | |
0a85226f | 1601 | restore_pirqs(); |
0e91398f JF |
1602 | } |
1603 | ||
e46cdb66 | 1604 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1605 | .name = "xen-dyn", |
54a353a0 | 1606 | |
c9e265e0 TG |
1607 | .irq_disable = disable_dynirq, |
1608 | .irq_mask = disable_dynirq, | |
1609 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1610 | |
7e186bdd SS |
1611 | .irq_ack = ack_dynirq, |
1612 | .irq_mask_ack = mask_ack_dynirq, | |
1613 | ||
c9e265e0 TG |
1614 | .irq_set_affinity = set_affinity_irq, |
1615 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1616 | }; |
1617 | ||
d46a78b0 | 1618 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1619 | .name = "xen-pirq", |
d46a78b0 | 1620 | |
c9e265e0 TG |
1621 | .irq_startup = startup_pirq, |
1622 | .irq_shutdown = shutdown_pirq, | |
c9e265e0 | 1623 | .irq_enable = enable_pirq, |
c9e265e0 | 1624 | .irq_disable = disable_pirq, |
d46a78b0 | 1625 | |
7e186bdd SS |
1626 | .irq_mask = disable_dynirq, |
1627 | .irq_unmask = enable_dynirq, | |
1628 | ||
1629 | .irq_ack = eoi_pirq, | |
1630 | .irq_eoi = eoi_pirq, | |
1631 | .irq_mask_ack = mask_ack_pirq, | |
d46a78b0 | 1632 | |
c9e265e0 | 1633 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1634 | |
c9e265e0 | 1635 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1636 | }; |
1637 | ||
aaca4964 | 1638 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1639 | .name = "xen-percpu", |
aaca4964 | 1640 | |
c9e265e0 TG |
1641 | .irq_disable = disable_dynirq, |
1642 | .irq_mask = disable_dynirq, | |
1643 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1644 | |
c9e265e0 | 1645 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1646 | }; |
1647 | ||
38e20b07 SY |
1648 | int xen_set_callback_via(uint64_t via) |
1649 | { | |
1650 | struct xen_hvm_param a; | |
1651 | a.domid = DOMID_SELF; | |
1652 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1653 | a.value = via; | |
1654 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1655 | } | |
1656 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1657 | ||
ca65f9fc | 1658 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1659 | /* Vector callbacks are better than PCI interrupts to receive event |
1660 | * channel notifications because we can receive vector callbacks on any | |
1661 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1662 | void xen_callback_vector(void) | |
1663 | { | |
1664 | int rc; | |
1665 | uint64_t callback_via; | |
72a9b186 | 1666 | |
84d582d2 BO |
1667 | if (xen_have_vector_callback) { |
1668 | callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR); | |
1669 | rc = xen_set_callback_via(callback_via); | |
1670 | if (rc) { | |
1671 | pr_err("Request for Xen HVM callback vector failed\n"); | |
1672 | xen_have_vector_callback = 0; | |
1673 | return; | |
1674 | } | |
867cefb4 | 1675 | pr_info_once("Xen HVM callback vector for event delivery is enabled\n"); |
4447ac11 TG |
1676 | alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, |
1677 | xen_hvm_callback_vector); | |
84d582d2 | 1678 | } |
38e20b07 | 1679 | } |
ca65f9fc SS |
1680 | #else |
1681 | void xen_callback_vector(void) {} | |
1682 | #endif | |
38e20b07 | 1683 | |
1fe56551 DV |
1684 | #undef MODULE_PARAM_PREFIX |
1685 | #define MODULE_PARAM_PREFIX "xen." | |
1686 | ||
1687 | static bool fifo_events = true; | |
1688 | module_param(fifo_events, bool, 0); | |
1689 | ||
2e3d8860 | 1690 | void __init xen_init_IRQ(void) |
e46cdb66 | 1691 | { |
1fe56551 | 1692 | int ret = -EINVAL; |
e91b2b11 | 1693 | unsigned int evtchn; |
1fe56551 DV |
1694 | |
1695 | if (fifo_events) | |
1696 | ret = xen_evtchn_fifo_init(); | |
1697 | if (ret < 0) | |
1698 | xen_evtchn_2l_init(); | |
ab9a1cca | 1699 | |
d0b075ff DV |
1700 | evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()), |
1701 | sizeof(*evtchn_to_irq), GFP_KERNEL); | |
9d093e29 | 1702 | BUG_ON(!evtchn_to_irq); |
e46cdb66 | 1703 | |
e46cdb66 | 1704 | /* No event channels are 'live' right now. */ |
e91b2b11 JG |
1705 | for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++) |
1706 | mask_evtchn(evtchn); | |
e46cdb66 | 1707 | |
9846ff10 SS |
1708 | pirq_needs_eoi = pirq_needs_eoi_flag; |
1709 | ||
0ec53ecf | 1710 | #ifdef CONFIG_X86 |
2771374d | 1711 | if (xen_pv_domain()) { |
2771374d MR |
1712 | if (xen_initial_domain()) |
1713 | pci_xen_initial_domain(); | |
1714 | } | |
1715 | if (xen_feature(XENFEAT_hvm_callback_vector)) | |
38e20b07 | 1716 | xen_callback_vector(); |
2771374d MR |
1717 | |
1718 | if (xen_hvm_domain()) { | |
38e20b07 | 1719 | native_init_IRQ(); |
3942b740 SS |
1720 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1721 | * __acpi_register_gsi can point at the right function */ | |
1722 | pci_xen_hvm_init(); | |
38e20b07 | 1723 | } else { |
0ec53ecf | 1724 | int rc; |
9846ff10 SS |
1725 | struct physdev_pirq_eoi_gmfn eoi_gmfn; |
1726 | ||
9846ff10 | 1727 | pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO); |
0df4f266 | 1728 | eoi_gmfn.gmfn = virt_to_gfn(pirq_eoi_map); |
9846ff10 SS |
1729 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn); |
1730 | if (rc != 0) { | |
1731 | free_page((unsigned long) pirq_eoi_map); | |
1732 | pirq_eoi_map = NULL; | |
1733 | } else | |
1734 | pirq_needs_eoi = pirq_check_eoi_map; | |
38e20b07 | 1735 | } |
0ec53ecf | 1736 | #endif |
e46cdb66 | 1737 | } |