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CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
JF
26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
JF
38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
9846ff10 42#include <asm/xen/page.h>
42a1de56 43#include <asm/xen/pci.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
SY
49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
e46cdb66
JF
52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
SY
55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
6efa20e4 59#include <xen/interface/vcpu.h>
0ec53ecf 60#include <asm/hw_irq.h>
e46cdb66 61
e46cdb66
JF
62/*
63 * This lock protects updates to the following mapping and reference-count
64 * arrays. The lock does not need to be acquired to read the mapping tables.
65 */
77365948 66static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 67
6cb6537d
IC
68static LIST_HEAD(xen_irq_list_head);
69
e46cdb66 70/* IRQ <-> VIRQ mapping. */
204fba4a 71static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 72
f87e4cac 73/* IRQ <-> IPI mapping */
204fba4a 74static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 75
ced40d0f
JF
76/* Interrupt types. */
77enum xen_irq_type {
d77bbd4d 78 IRQT_UNBOUND = 0,
f87e4cac
JF
79 IRQT_PIRQ,
80 IRQT_VIRQ,
81 IRQT_IPI,
82 IRQT_EVTCHN
83};
e46cdb66 84
ced40d0f
JF
85/*
86 * Packed IRQ information:
87 * type - enum xen_irq_type
88 * event channel - irq->event channel mapping
89 * cpu - cpu this event channel is bound to
90 * index - type-specific information:
dec02dea 91 * PIRQ - physical IRQ, GSI, flags, and owner domain
ced40d0f
JF
92 * VIRQ - virq number
93 * IPI - IPI vector
94 * EVTCHN -
95 */
088c05a8 96struct irq_info {
6cb6537d 97 struct list_head list;
420eb554 98 int refcnt;
ced40d0f 99 enum xen_irq_type type; /* type */
6cb6537d 100 unsigned irq;
ced40d0f
JF
101 unsigned short evtchn; /* event channel */
102 unsigned short cpu; /* cpu bound */
103
104 union {
105 unsigned short virq;
106 enum ipi_vector ipi;
107 struct {
7a043f11 108 unsigned short pirq;
ced40d0f 109 unsigned short gsi;
d46a78b0 110 unsigned char flags;
beafbdc1 111 uint16_t domid;
ced40d0f
JF
112 } pirq;
113 } u;
114};
d46a78b0 115#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 116#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 117
b21ddbf5 118static int *evtchn_to_irq;
bf86ad80 119#ifdef CONFIG_X86
9846ff10 120static unsigned long *pirq_eoi_map;
bf86ad80 121#endif
9846ff10 122static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 123
c81611c4
IC
124/*
125 * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
126 * careful to only use bitops which allow for this (e.g
127 * test_bit/find_first_bit and friends but not __ffs) and to pass
128 * BITS_PER_EVTCHN_WORD as the bitmask length.
129 */
130#define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
131/*
132 * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
133 * array. Primarily to avoid long lines (hence the terse name).
134 */
135#define BM(x) (unsigned long *)(x)
136/* Find the first set bit in a evtchn mask */
137#define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
138
139static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
cb60d114 140 cpu_evtchn_mask);
e46cdb66 141
e46cdb66
JF
142/* Xen will never allocate port zero for any purpose. */
143#define VALID_EVTCHN(chn) ((chn) != 0)
144
e46cdb66 145static struct irq_chip xen_dynamic_chip;
aaca4964 146static struct irq_chip xen_percpu_chip;
d46a78b0 147static struct irq_chip xen_pirq_chip;
7e186bdd
SS
148static void enable_dynirq(struct irq_data *data);
149static void disable_dynirq(struct irq_data *data);
e46cdb66 150
9158c358
IC
151/* Get info for IRQ */
152static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 153{
c442b806 154 return irq_get_handler_data(irq);
ced40d0f
JF
155}
156
9158c358
IC
157/* Constructors for packed IRQ information. */
158static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 159 unsigned irq,
9158c358
IC
160 enum xen_irq_type type,
161 unsigned short evtchn,
162 unsigned short cpu)
ced40d0f 163{
9158c358
IC
164
165 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
166
167 info->type = type;
6cb6537d 168 info->irq = irq;
9158c358
IC
169 info->evtchn = evtchn;
170 info->cpu = cpu;
3d4cfa37
IC
171
172 evtchn_to_irq[evtchn] = irq;
934f585e
JG
173
174 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
ced40d0f
JF
175}
176
9158c358
IC
177static void xen_irq_info_evtchn_init(unsigned irq,
178 unsigned short evtchn)
ced40d0f 179{
9158c358
IC
180 struct irq_info *info = info_for_irq(irq);
181
3d4cfa37 182 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
183}
184
3d4cfa37
IC
185static void xen_irq_info_ipi_init(unsigned cpu,
186 unsigned irq,
9158c358
IC
187 unsigned short evtchn,
188 enum ipi_vector ipi)
e46cdb66 189{
9158c358
IC
190 struct irq_info *info = info_for_irq(irq);
191
3d4cfa37 192 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
193
194 info->u.ipi = ipi;
3d4cfa37
IC
195
196 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
197}
198
3d4cfa37
IC
199static void xen_irq_info_virq_init(unsigned cpu,
200 unsigned irq,
9158c358
IC
201 unsigned short evtchn,
202 unsigned short virq)
ced40d0f 203{
9158c358
IC
204 struct irq_info *info = info_for_irq(irq);
205
3d4cfa37 206 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
207
208 info->u.virq = virq;
3d4cfa37
IC
209
210 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
211}
212
9158c358
IC
213static void xen_irq_info_pirq_init(unsigned irq,
214 unsigned short evtchn,
215 unsigned short pirq,
216 unsigned short gsi,
beafbdc1 217 uint16_t domid,
9158c358 218 unsigned char flags)
ced40d0f 219{
9158c358
IC
220 struct irq_info *info = info_for_irq(irq);
221
3d4cfa37 222 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
223
224 info->u.pirq.pirq = pirq;
225 info->u.pirq.gsi = gsi;
beafbdc1 226 info->u.pirq.domid = domid;
9158c358 227 info->u.pirq.flags = flags;
e46cdb66
JF
228}
229
230/*
231 * Accessors for packed IRQ information.
232 */
ced40d0f 233static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 234{
110e7c7e
JJ
235 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
236 return 0;
237
ced40d0f 238 return info_for_irq(irq)->evtchn;
e46cdb66
JF
239}
240
d4c04536
IC
241unsigned irq_from_evtchn(unsigned int evtchn)
242{
243 return evtchn_to_irq[evtchn];
244}
245EXPORT_SYMBOL_GPL(irq_from_evtchn);
246
ced40d0f 247static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 248{
ced40d0f
JF
249 struct irq_info *info = info_for_irq(irq);
250
251 BUG_ON(info == NULL);
252 BUG_ON(info->type != IRQT_IPI);
253
254 return info->u.ipi;
255}
256
257static unsigned virq_from_irq(unsigned irq)
258{
259 struct irq_info *info = info_for_irq(irq);
260
261 BUG_ON(info == NULL);
262 BUG_ON(info->type != IRQT_VIRQ);
263
264 return info->u.virq;
265}
266
7a043f11
SS
267static unsigned pirq_from_irq(unsigned irq)
268{
269 struct irq_info *info = info_for_irq(irq);
270
271 BUG_ON(info == NULL);
272 BUG_ON(info->type != IRQT_PIRQ);
273
274 return info->u.pirq.pirq;
275}
276
ced40d0f
JF
277static enum xen_irq_type type_from_irq(unsigned irq)
278{
279 return info_for_irq(irq)->type;
280}
281
282static unsigned cpu_from_irq(unsigned irq)
283{
284 return info_for_irq(irq)->cpu;
285}
286
287static unsigned int cpu_from_evtchn(unsigned int evtchn)
288{
289 int irq = evtchn_to_irq[evtchn];
290 unsigned ret = 0;
291
292 if (irq != -1)
293 ret = cpu_from_irq(irq);
294
295 return ret;
e46cdb66
JF
296}
297
bf86ad80 298#ifdef CONFIG_X86
9846ff10 299static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 300{
521394e4 301 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 302}
bf86ad80 303#endif
d46a78b0 304
9846ff10
SS
305static bool pirq_needs_eoi_flag(unsigned irq)
306{
307 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
308 BUG_ON(info->type != IRQT_PIRQ);
309
310 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
311}
312
c81611c4
IC
313static inline xen_ulong_t active_evtchns(unsigned int cpu,
314 struct shared_info *sh,
315 unsigned int idx)
e46cdb66 316{
088c05a8 317 return sh->evtchn_pending[idx] &
cb60d114 318 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 319 ~sh->evtchn_mask[idx];
e46cdb66
JF
320}
321
322static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
323{
324 int irq = evtchn_to_irq[chn];
325
326 BUG_ON(irq == -1);
327#ifdef CONFIG_SMP
c9e265e0 328 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
329#endif
330
c81611c4
IC
331 clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
332 set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
e46cdb66 333
ca62ce8c 334 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
335}
336
e46cdb66
JF
337static inline void clear_evtchn(int port)
338{
339 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 340 sync_clear_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
341}
342
343static inline void set_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 346 sync_set_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
347}
348
168d2f46
JF
349static inline int test_evtchn(int port)
350{
351 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 352 return sync_test_bit(port, BM(&s->evtchn_pending[0]));
168d2f46
JF
353}
354
3f70fa82
WL
355static inline int test_and_set_mask(int port)
356{
357 struct shared_info *s = HYPERVISOR_shared_info;
358 return sync_test_and_set_bit(port, BM(&s->evtchn_mask[0]));
359}
360
e46cdb66
JF
361
362/**
363 * notify_remote_via_irq - send event to remote end of event channel via irq
364 * @irq: irq of event channel to send event to
365 *
366 * Unlike notify_remote_via_evtchn(), this is safe to use across
367 * save/restore. Notifications on a broken connection are silently
368 * dropped.
369 */
370void notify_remote_via_irq(int irq)
371{
372 int evtchn = evtchn_from_irq(irq);
373
374 if (VALID_EVTCHN(evtchn))
375 notify_remote_via_evtchn(evtchn);
376}
377EXPORT_SYMBOL_GPL(notify_remote_via_irq);
378
379static void mask_evtchn(int port)
380{
381 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 382 sync_set_bit(port, BM(&s->evtchn_mask[0]));
e46cdb66
JF
383}
384
385static void unmask_evtchn(int port)
386{
387 struct shared_info *s = HYPERVISOR_shared_info;
388 unsigned int cpu = get_cpu();
b5e57923 389 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
JF
390
391 BUG_ON(!irqs_disabled());
392
b5e57923
SS
393 if (unlikely((cpu != cpu_from_evtchn(port))))
394 do_hypercall = 1;
c26377e6
DV
395 else {
396 /*
397 * Need to clear the mask before checking pending to
398 * avoid a race with an event becoming pending.
399 *
400 * EVTCHNOP_unmask will only trigger an upcall if the
401 * mask bit was set, so if a hypercall is needed
402 * remask the event.
403 */
404 sync_clear_bit(port, BM(&s->evtchn_mask[0]));
c81611c4 405 evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
b5e57923 406
c26377e6
DV
407 if (unlikely(evtchn_pending && xen_hvm_domain())) {
408 sync_set_bit(port, BM(&s->evtchn_mask[0]));
409 do_hypercall = 1;
410 }
411 }
b5e57923
SS
412
413 /* Slow path (hypercall) if this is a non-local port or if this is
414 * an hvm domain and an event is pending (hvm domains don't have
415 * their own implementation of irq_enable). */
416 if (do_hypercall) {
e46cdb66
JF
417 struct evtchn_unmask unmask = { .port = port };
418 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
419 } else {
780f36d8 420 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66 421
e46cdb66
JF
422 /*
423 * The following is basically the equivalent of
424 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
425 * the interrupt edge' if the channel is masked.
426 */
b5e57923 427 if (evtchn_pending &&
c81611c4
IC
428 !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
429 BM(&vcpu_info->evtchn_pending_sel)))
e46cdb66
JF
430 vcpu_info->evtchn_upcall_pending = 1;
431 }
432
433 put_cpu();
434}
435
6cb6537d
IC
436static void xen_irq_init(unsigned irq)
437{
438 struct irq_info *info;
b5328cd1 439#ifdef CONFIG_SMP
6cb6537d
IC
440 struct irq_desc *desc = irq_to_desc(irq);
441
442 /* By default all event channels notify CPU#0. */
443 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 444#endif
6cb6537d 445
ca62ce8c
IC
446 info = kzalloc(sizeof(*info), GFP_KERNEL);
447 if (info == NULL)
448 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
449
450 info->type = IRQT_UNBOUND;
420eb554 451 info->refcnt = -1;
6cb6537d 452
c442b806 453 irq_set_handler_data(irq, info);
ca62ce8c 454
6cb6537d
IC
455 list_add_tail(&info->list, &xen_irq_list_head);
456}
457
7bee9768 458static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 459{
89911501
IC
460 int first = 0;
461 int irq;
0794bfc7
KRW
462
463#ifdef CONFIG_X86_IO_APIC
89911501
IC
464 /*
465 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 466 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
467 * e.g. those corresponding to event channels or MSIs
468 * etc. from the range above those "real" GSIs to avoid
469 * collisions.
470 */
471 if (xen_initial_domain() || xen_hvm_domain())
472 first = get_nr_irqs_gsi();
0794bfc7
KRW
473#endif
474
89911501 475 irq = irq_alloc_desc_from(first, -1);
3a69e916 476
e6599225
KRW
477 if (irq >= 0)
478 xen_irq_init(irq);
ced40d0f 479
e46cdb66 480 return irq;
d46a78b0
JF
481}
482
7bee9768 483static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
484{
485 int irq;
486
89911501
IC
487 /*
488 * A PV guest has no concept of a GSI (since it has no ACPI
489 * nor access to/knowledge of the physical APICs). Therefore
490 * all IRQs are dynamically allocated from the entire IRQ
491 * space.
492 */
493 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
494 return xen_allocate_irq_dynamic();
495
496 /* Legacy IRQ descriptors are already allocated by the arch. */
497 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
498 irq = gsi;
499 else
500 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 501
6cb6537d 502 xen_irq_init(irq);
c9df1ce5
IC
503
504 return irq;
505}
506
507static void xen_free_irq(unsigned irq)
508{
c442b806 509 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 510
94032c50
KRW
511 if (WARN_ON(!info))
512 return;
513
6cb6537d 514 list_del(&info->list);
9158c358 515
c442b806 516 irq_set_handler_data(irq, NULL);
ca62ce8c 517
420eb554
DDG
518 WARN_ON(info->refcnt > 0);
519
ca62ce8c
IC
520 kfree(info);
521
72146104
IC
522 /* Legacy IRQ descriptors are managed by the arch. */
523 if (irq < NR_IRQS_LEGACY)
524 return;
525
c9df1ce5
IC
526 irq_free_desc(irq);
527}
528
d46a78b0
JF
529static void pirq_query_unmask(int irq)
530{
531 struct physdev_irq_status_query irq_status;
532 struct irq_info *info = info_for_irq(irq);
533
534 BUG_ON(info->type != IRQT_PIRQ);
535
7a043f11 536 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
537 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
538 irq_status.flags = 0;
539
540 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
541 if (irq_status.flags & XENIRQSTAT_needs_eoi)
542 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
543}
544
545static bool probing_irq(int irq)
546{
547 struct irq_desc *desc = irq_to_desc(irq);
548
549 return desc && desc->action == NULL;
550}
551
7e186bdd
SS
552static void eoi_pirq(struct irq_data *data)
553{
554 int evtchn = evtchn_from_irq(data->irq);
555 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
556 int rc = 0;
557
558 irq_move_irq(data);
559
560 if (VALID_EVTCHN(evtchn))
561 clear_evtchn(evtchn);
562
563 if (pirq_needs_eoi(data->irq)) {
564 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
565 WARN_ON(rc);
566 }
567}
568
569static void mask_ack_pirq(struct irq_data *data)
570{
571 disable_dynirq(data);
572 eoi_pirq(data);
573}
574
c9e265e0 575static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
576{
577 struct evtchn_bind_pirq bind_pirq;
578 struct irq_info *info = info_for_irq(irq);
579 int evtchn = evtchn_from_irq(irq);
15ebbb82 580 int rc;
d46a78b0
JF
581
582 BUG_ON(info->type != IRQT_PIRQ);
583
584 if (VALID_EVTCHN(evtchn))
585 goto out;
586
7a043f11 587 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 588 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
589 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
590 BIND_PIRQ__WILL_SHARE : 0;
591 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
592 if (rc != 0) {
d46a78b0 593 if (!probing_irq(irq))
283c0972 594 pr_info("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
595 return 0;
596 }
597 evtchn = bind_pirq.port;
598
599 pirq_query_unmask(irq);
600
601 evtchn_to_irq[evtchn] = irq;
602 bind_evtchn_to_cpu(evtchn, 0);
603 info->evtchn = evtchn;
604
605out:
606 unmask_evtchn(evtchn);
7e186bdd 607 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
608
609 return 0;
610}
611
c9e265e0
TG
612static unsigned int startup_pirq(struct irq_data *data)
613{
614 return __startup_pirq(data->irq);
615}
616
617static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
618{
619 struct evtchn_close close;
c9e265e0 620 unsigned int irq = data->irq;
d46a78b0
JF
621 struct irq_info *info = info_for_irq(irq);
622 int evtchn = evtchn_from_irq(irq);
623
624 BUG_ON(info->type != IRQT_PIRQ);
625
626 if (!VALID_EVTCHN(evtchn))
627 return;
628
629 mask_evtchn(evtchn);
630
631 close.port = evtchn;
632 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
633 BUG();
634
635 bind_evtchn_to_cpu(evtchn, 0);
636 evtchn_to_irq[evtchn] = -1;
637 info->evtchn = 0;
638}
639
c9e265e0 640static void enable_pirq(struct irq_data *data)
d46a78b0 641{
c9e265e0 642 startup_pirq(data);
d46a78b0
JF
643}
644
c9e265e0 645static void disable_pirq(struct irq_data *data)
d46a78b0 646{
7e186bdd 647 disable_dynirq(data);
d46a78b0
JF
648}
649
68c2c39a 650int xen_irq_from_gsi(unsigned gsi)
d46a78b0 651{
6cb6537d 652 struct irq_info *info;
d46a78b0 653
6cb6537d
IC
654 list_for_each_entry(info, &xen_irq_list_head, list) {
655 if (info->type != IRQT_PIRQ)
d46a78b0
JF
656 continue;
657
6cb6537d
IC
658 if (info->u.pirq.gsi == gsi)
659 return info->irq;
d46a78b0
JF
660 }
661
662 return -1;
663}
68c2c39a 664EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 665
653378ac
IC
666/*
667 * Do not make any assumptions regarding the relationship between the
668 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
669 *
670 * Note: We don't assign an event channel until the irq actually started
671 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
672 *
673 * Shareable implies level triggered, not shareable implies edge
674 * triggered here.
d46a78b0 675 */
f4d0635b
IC
676int xen_bind_pirq_gsi_to_irq(unsigned gsi,
677 unsigned pirq, int shareable, char *name)
d46a78b0 678{
a0e18116 679 int irq = -1;
d46a78b0
JF
680 struct physdev_irq irq_op;
681
77365948 682 mutex_lock(&irq_mapping_update_lock);
d46a78b0 683
68c2c39a 684 irq = xen_irq_from_gsi(gsi);
d46a78b0 685 if (irq != -1) {
283c0972
JP
686 pr_info("%s: returning irq %d for gsi %u\n",
687 __func__, irq, gsi);
420eb554 688 goto out;
d46a78b0
JF
689 }
690
c9df1ce5 691 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
692 if (irq < 0)
693 goto out;
d46a78b0 694
d46a78b0 695 irq_op.irq = irq;
b5401a96
AN
696 irq_op.vector = 0;
697
698 /* Only the privileged domain can do this. For non-priv, the pcifront
699 * driver provides a PCI bus that does the call to do exactly
700 * this in the priv domain. */
701 if (xen_initial_domain() &&
702 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 703 xen_free_irq(irq);
d46a78b0
JF
704 irq = -ENOSPC;
705 goto out;
706 }
707
dec02dea 708 xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 709 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 710
7e186bdd
SS
711 pirq_query_unmask(irq);
712 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
713 * type of interrupt: if the interrupt is an edge triggered
714 * interrupt we use handle_edge_irq.
7e186bdd 715 *
e5ac0bda
SS
716 * On the other hand if the interrupt is level triggered we use
717 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 718 * interrupts.
e5ac0bda 719 *
7e186bdd
SS
720 * Depending on the Xen version, pirq_needs_eoi might return true
721 * not only for level triggered interrupts but for edge triggered
722 * interrupts too. In any case Xen always honors the eoi mechanism,
723 * not injecting any more pirqs of the same kind if the first one
724 * hasn't received an eoi yet. Therefore using the fasteoi handler
725 * is the right choice either way.
726 */
e5ac0bda 727 if (shareable)
7e186bdd
SS
728 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
729 handle_fasteoi_irq, name);
730 else
731 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
732 handle_edge_irq, name);
733
d46a78b0 734out:
77365948 735 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
736
737 return irq;
738}
739
f731e3ef 740#ifdef CONFIG_PCI_MSI
bf480d95 741int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 742{
5cad61a6 743 int rc;
cbf6aa89 744 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 745
bf480d95 746 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 747 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 748
5cad61a6
IC
749 WARN_ONCE(rc == -ENOSYS,
750 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
751
752 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
753}
754
bf480d95 755int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 756 int pirq, const char *name, domid_t domid)
809f9267 757{
bf480d95 758 int irq, ret;
4b41df7f 759
77365948 760 mutex_lock(&irq_mapping_update_lock);
809f9267 761
4b41df7f 762 irq = xen_allocate_irq_dynamic();
e6599225 763 if (irq < 0)
bb5d079a 764 goto out;
809f9267 765
7e186bdd
SS
766 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
767 name);
809f9267 768
dec02dea 769 xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0);
5f6fb454 770 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
771 if (ret < 0)
772 goto error_irq;
809f9267 773out:
77365948 774 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 775 return irq;
bf480d95 776error_irq:
77365948 777 mutex_unlock(&irq_mapping_update_lock);
bf480d95 778 xen_free_irq(irq);
e6599225 779 return ret;
809f9267 780}
f731e3ef
QH
781#endif
782
b5401a96
AN
783int xen_destroy_irq(int irq)
784{
785 struct irq_desc *desc;
38aa66fc
JF
786 struct physdev_unmap_pirq unmap_irq;
787 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
788 int rc = -ENOENT;
789
77365948 790 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
791
792 desc = irq_to_desc(irq);
793 if (!desc)
794 goto out;
795
38aa66fc 796 if (xen_initial_domain()) {
12334715 797 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 798 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 799 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
800 /* If another domain quits without making the pci_disable_msix
801 * call, the Xen hypervisor takes care of freeing the PIRQs
802 * (free_domain_pirqs).
803 */
804 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 805 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
806 info->u.pirq.domid, info->u.pirq.pirq);
807 else if (rc) {
283c0972 808 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
809 goto out;
810 }
811 }
b5401a96 812
c9df1ce5 813 xen_free_irq(irq);
b5401a96
AN
814
815out:
77365948 816 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
817 return rc;
818}
819
af42b8d1 820int xen_irq_from_pirq(unsigned pirq)
d46a78b0 821{
69c358ce 822 int irq;
d46a78b0 823
69c358ce 824 struct irq_info *info;
e46cdb66 825
77365948 826 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
827
828 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 829 if (info->type != IRQT_PIRQ)
69c358ce
IC
830 continue;
831 irq = info->irq;
832 if (info->u.pirq.pirq == pirq)
833 goto out;
834 }
835 irq = -1;
836out:
77365948 837 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
838
839 return irq;
af42b8d1
SS
840}
841
e6197acc
KRW
842
843int xen_pirq_from_irq(unsigned irq)
844{
845 return pirq_from_irq(irq);
846}
847EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 848int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
849{
850 int irq;
851
77365948 852 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
853
854 irq = evtchn_to_irq[evtchn];
855
856 if (irq == -1) {
c9df1ce5 857 irq = xen_allocate_irq_dynamic();
68ba45ff 858 if (irq < 0)
7bee9768 859 goto out;
e46cdb66 860
c442b806 861 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 862 handle_edge_irq, "event");
e46cdb66 863
9158c358 864 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
865 } else {
866 struct irq_info *info = info_for_irq(irq);
867 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
868 }
869
7bee9768 870out:
77365948 871 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
872
873 return irq;
874}
b536b4b9 875EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 876
f87e4cac
JF
877static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
878{
879 struct evtchn_bind_ipi bind_ipi;
880 int evtchn, irq;
881
77365948 882 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
883
884 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 885
f87e4cac 886 if (irq == -1) {
c9df1ce5 887 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
888 if (irq < 0)
889 goto out;
890
c442b806 891 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 892 handle_percpu_irq, "ipi");
f87e4cac
JF
893
894 bind_ipi.vcpu = cpu;
895 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
896 &bind_ipi) != 0)
897 BUG();
898 evtchn = bind_ipi.port;
899
3d4cfa37 900 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
901
902 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
903 } else {
904 struct irq_info *info = info_for_irq(irq);
905 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
906 }
907
f87e4cac 908 out:
77365948 909 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
910 return irq;
911}
912
2e820f58
IC
913static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
914 unsigned int remote_port)
915{
916 struct evtchn_bind_interdomain bind_interdomain;
917 int err;
918
919 bind_interdomain.remote_dom = remote_domain;
920 bind_interdomain.remote_port = remote_port;
921
922 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
923 &bind_interdomain);
924
925 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
926}
927
62cc5fc7
OH
928static int find_virq(unsigned int virq, unsigned int cpu)
929{
930 struct evtchn_status status;
931 int port, rc = -ENOENT;
932
933 memset(&status, 0, sizeof(status));
934 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
935 status.dom = DOMID_SELF;
936 status.port = port;
937 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
938 if (rc < 0)
939 continue;
940 if (status.status != EVTCHNSTAT_virq)
941 continue;
942 if (status.u.virq == virq && status.vcpu == cpu) {
943 rc = port;
944 break;
945 }
946 }
947 return rc;
948}
f87e4cac 949
4fe7d5a7 950int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
951{
952 struct evtchn_bind_virq bind_virq;
62cc5fc7 953 int evtchn, irq, ret;
e46cdb66 954
77365948 955 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
956
957 irq = per_cpu(virq_to_irq, cpu)[virq];
958
959 if (irq == -1) {
c9df1ce5 960 irq = xen_allocate_irq_dynamic();
68ba45ff 961 if (irq < 0)
7bee9768 962 goto out;
a52521f1 963
c442b806 964 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
965 handle_percpu_irq, "virq");
966
e46cdb66
JF
967 bind_virq.virq = virq;
968 bind_virq.vcpu = cpu;
62cc5fc7
OH
969 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
970 &bind_virq);
971 if (ret == 0)
972 evtchn = bind_virq.port;
973 else {
974 if (ret == -EEXIST)
975 ret = find_virq(virq, cpu);
976 BUG_ON(ret < 0);
977 evtchn = ret;
978 }
e46cdb66 979
3d4cfa37 980 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
981
982 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
983 } else {
984 struct irq_info *info = info_for_irq(irq);
985 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
986 }
987
7bee9768 988out:
77365948 989 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
990
991 return irq;
992}
993
994static void unbind_from_irq(unsigned int irq)
995{
996 struct evtchn_close close;
997 int evtchn = evtchn_from_irq(irq);
420eb554 998 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 999
94032c50
KRW
1000 if (WARN_ON(!info))
1001 return;
1002
77365948 1003 mutex_lock(&irq_mapping_update_lock);
e46cdb66 1004
420eb554
DDG
1005 if (info->refcnt > 0) {
1006 info->refcnt--;
1007 if (info->refcnt != 0)
1008 goto done;
1009 }
1010
d77bbd4d 1011 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
1012 close.port = evtchn;
1013 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
1014 BUG();
1015
1016 switch (type_from_irq(irq)) {
1017 case IRQT_VIRQ:
1018 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1019 [virq_from_irq(irq)] = -1;
e46cdb66 1020 break;
d68d82af
AN
1021 case IRQT_IPI:
1022 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1023 [ipi_from_irq(irq)] = -1;
d68d82af 1024 break;
e46cdb66
JF
1025 default:
1026 break;
1027 }
1028
1029 /* Closed ports are implicitly re-bound to VCPU0. */
1030 bind_evtchn_to_cpu(evtchn, 0);
1031
1032 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1033 }
1034
ca62ce8c 1035 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1036
9158c358 1037 xen_free_irq(irq);
e46cdb66 1038
420eb554 1039 done:
77365948 1040 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1041}
1042
1043int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1044 irq_handler_t handler,
e46cdb66
JF
1045 unsigned long irqflags,
1046 const char *devname, void *dev_id)
1047{
361ae8cb 1048 int irq, retval;
e46cdb66
JF
1049
1050 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1051 if (irq < 0)
1052 return irq;
e46cdb66
JF
1053 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1054 if (retval != 0) {
1055 unbind_from_irq(irq);
1056 return retval;
1057 }
1058
1059 return irq;
1060}
1061EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1062
2e820f58
IC
1063int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1064 unsigned int remote_port,
1065 irq_handler_t handler,
1066 unsigned long irqflags,
1067 const char *devname,
1068 void *dev_id)
1069{
1070 int irq, retval;
1071
1072 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1073 if (irq < 0)
1074 return irq;
1075
1076 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1077 if (retval != 0) {
1078 unbind_from_irq(irq);
1079 return retval;
1080 }
1081
1082 return irq;
1083}
1084EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1085
e46cdb66 1086int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1087 irq_handler_t handler,
e46cdb66
JF
1088 unsigned long irqflags, const char *devname, void *dev_id)
1089{
361ae8cb 1090 int irq, retval;
e46cdb66
JF
1091
1092 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1093 if (irq < 0)
1094 return irq;
e46cdb66
JF
1095 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1096 if (retval != 0) {
1097 unbind_from_irq(irq);
1098 return retval;
1099 }
1100
1101 return irq;
1102}
1103EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1104
f87e4cac
JF
1105int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1106 unsigned int cpu,
1107 irq_handler_t handler,
1108 unsigned long irqflags,
1109 const char *devname,
1110 void *dev_id)
1111{
1112 int irq, retval;
1113
1114 irq = bind_ipi_to_irq(ipi, cpu);
1115 if (irq < 0)
1116 return irq;
1117
9bab0b7f 1118 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1119 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1120 if (retval != 0) {
1121 unbind_from_irq(irq);
1122 return retval;
1123 }
1124
1125 return irq;
1126}
1127
e46cdb66
JF
1128void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1129{
94032c50
KRW
1130 struct irq_info *info = irq_get_handler_data(irq);
1131
1132 if (WARN_ON(!info))
1133 return;
e46cdb66
JF
1134 free_irq(irq, dev_id);
1135 unbind_from_irq(irq);
1136}
1137EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1138
420eb554
DDG
1139int evtchn_make_refcounted(unsigned int evtchn)
1140{
1141 int irq = evtchn_to_irq[evtchn];
1142 struct irq_info *info;
1143
1144 if (irq == -1)
1145 return -ENOENT;
1146
1147 info = irq_get_handler_data(irq);
1148
1149 if (!info)
1150 return -ENOENT;
1151
1152 WARN_ON(info->refcnt != -1);
1153
1154 info->refcnt = 1;
1155
1156 return 0;
1157}
1158EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1159
1160int evtchn_get(unsigned int evtchn)
1161{
1162 int irq;
1163 struct irq_info *info;
1164 int err = -ENOENT;
1165
c3b3f16d
DDG
1166 if (evtchn >= NR_EVENT_CHANNELS)
1167 return -EINVAL;
1168
420eb554
DDG
1169 mutex_lock(&irq_mapping_update_lock);
1170
1171 irq = evtchn_to_irq[evtchn];
1172 if (irq == -1)
1173 goto done;
1174
1175 info = irq_get_handler_data(irq);
1176
1177 if (!info)
1178 goto done;
1179
1180 err = -EINVAL;
1181 if (info->refcnt <= 0)
1182 goto done;
1183
1184 info->refcnt++;
1185 err = 0;
1186 done:
1187 mutex_unlock(&irq_mapping_update_lock);
1188
1189 return err;
1190}
1191EXPORT_SYMBOL_GPL(evtchn_get);
1192
1193void evtchn_put(unsigned int evtchn)
1194{
1195 int irq = evtchn_to_irq[evtchn];
1196 if (WARN_ON(irq == -1))
1197 return;
1198 unbind_from_irq(irq);
1199}
1200EXPORT_SYMBOL_GPL(evtchn_put);
1201
f87e4cac
JF
1202void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1203{
6efa20e4
KRW
1204 int irq;
1205
072b2064 1206#ifdef CONFIG_X86
6efa20e4
KRW
1207 if (unlikely(vector == XEN_NMI_VECTOR)) {
1208 int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
1209 if (rc < 0)
1210 printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
1211 return;
1212 }
072b2064 1213#endif
6efa20e4 1214 irq = per_cpu(ipi_to_irq, cpu)[vector];
f87e4cac
JF
1215 BUG_ON(irq < 0);
1216 notify_remote_via_irq(irq);
1217}
1218
ee523ca1
JF
1219irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1220{
1221 struct shared_info *sh = HYPERVISOR_shared_info;
1222 int cpu = smp_processor_id();
c81611c4 1223 xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1224 int i;
1225 unsigned long flags;
1226 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1227 struct vcpu_info *v;
ee523ca1
JF
1228
1229 spin_lock_irqsave(&debug_lock, flags);
1230
cb52e6d9 1231 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1232
1233 for_each_online_cpu(i) {
cb52e6d9
IC
1234 int pending;
1235 v = per_cpu(xen_vcpu, i);
1236 pending = (get_irq_regs() && i == cpu)
1237 ? xen_irqs_disabled(get_irq_regs())
1238 : v->evtchn_upcall_mask;
c81611c4 1239 printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
cb52e6d9
IC
1240 pending, v->evtchn_upcall_pending,
1241 (int)(sizeof(v->evtchn_pending_sel)*2),
1242 v->evtchn_pending_sel);
1243 }
1244 v = per_cpu(xen_vcpu, cpu);
1245
1246 printk("\npending:\n ");
1247 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
c81611c4
IC
1248 printk("%0*"PRI_xen_ulong"%s",
1249 (int)sizeof(sh->evtchn_pending[0])*2,
cb52e6d9
IC
1250 sh->evtchn_pending[i],
1251 i % 8 == 0 ? "\n " : " ");
1252 printk("\nglobal mask:\n ");
1253 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4 1254 printk("%0*"PRI_xen_ulong"%s",
cb52e6d9
IC
1255 (int)(sizeof(sh->evtchn_mask[0])*2),
1256 sh->evtchn_mask[i],
1257 i % 8 == 0 ? "\n " : " ");
1258
1259 printk("\nglobally unmasked:\n ");
1260 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4
IC
1261 printk("%0*"PRI_xen_ulong"%s",
1262 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9
IC
1263 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1264 i % 8 == 0 ? "\n " : " ");
1265
1266 printk("\nlocal cpu%d mask:\n ", cpu);
c81611c4
IC
1267 for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
1268 printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
cb52e6d9
IC
1269 cpu_evtchn[i],
1270 i % 8 == 0 ? "\n " : " ");
1271
1272 printk("\nlocally unmasked:\n ");
1273 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
c81611c4 1274 xen_ulong_t pending = sh->evtchn_pending[i]
cb52e6d9
IC
1275 & ~sh->evtchn_mask[i]
1276 & cpu_evtchn[i];
c81611c4
IC
1277 printk("%0*"PRI_xen_ulong"%s",
1278 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9 1279 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1280 }
ee523ca1
JF
1281
1282 printk("\npending list:\n");
cb52e6d9 1283 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
c81611c4
IC
1284 if (sync_test_bit(i, BM(sh->evtchn_pending))) {
1285 int word_idx = i / BITS_PER_EVTCHN_WORD;
cb52e6d9 1286 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1287 cpu_from_evtchn(i), i,
cb52e6d9 1288 evtchn_to_irq[i],
c81611c4 1289 sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
cb52e6d9 1290 ? "" : " l2-clear",
c81611c4 1291 !sync_test_bit(i, BM(sh->evtchn_mask))
cb52e6d9 1292 ? "" : " globally-masked",
c81611c4 1293 sync_test_bit(i, BM(cpu_evtchn))
cb52e6d9 1294 ? "" : " locally-masked");
ee523ca1
JF
1295 }
1296 }
1297
1298 spin_unlock_irqrestore(&debug_lock, flags);
1299
1300 return IRQ_HANDLED;
1301}
1302
245b2e70 1303static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1304static DEFINE_PER_CPU(unsigned int, current_word_idx);
1305static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1306
ab7f863e
SR
1307/*
1308 * Mask out the i least significant bits of w
1309 */
c81611c4 1310#define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
245b2e70 1311
e46cdb66
JF
1312/*
1313 * Search the CPUs pending events bitmasks. For each one found, map
1314 * the event number to an irq, and feed it into do_IRQ() for
1315 * handling.
1316 *
1317 * Xen uses a two-level bitmap to speed searching. The first level is
1318 * a bitset of words which contain pending event bits. The second
1319 * level is a bitset of pending events themselves.
1320 */
38e20b07 1321static void __xen_evtchn_do_upcall(void)
e46cdb66 1322{
24b51c2f 1323 int start_word_idx, start_bit_idx;
ab7f863e 1324 int word_idx, bit_idx;
bee980d9 1325 int i, irq;
e46cdb66
JF
1326 int cpu = get_cpu();
1327 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1328 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1329 unsigned count;
e46cdb66 1330
229664be 1331 do {
c81611c4 1332 xen_ulong_t pending_words;
bee980d9
KF
1333 xen_ulong_t pending_bits;
1334 struct irq_desc *desc;
e46cdb66 1335
229664be 1336 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1337
b2e4ae69 1338 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1339 goto out;
e46cdb66 1340
c81611c4
IC
1341 /*
1342 * Master flag must be cleared /before/ clearing
1343 * selector flag. xchg_xen_ulong must contain an
1344 * appropriate barrier.
1345 */
bee980d9
KF
1346 if ((irq = per_cpu(virq_to_irq, cpu)[VIRQ_TIMER]) != -1) {
1347 int evtchn = evtchn_from_irq(irq);
1348 word_idx = evtchn / BITS_PER_LONG;
1349 pending_bits = evtchn % BITS_PER_LONG;
1350 if (active_evtchns(cpu, s, word_idx) & (1ULL << pending_bits)) {
1351 desc = irq_to_desc(irq);
1352 if (desc)
1353 generic_handle_irq_desc(irq, desc);
1354 }
1355 }
1356
c81611c4 1357 pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1358
24b51c2f
KF
1359 start_word_idx = __this_cpu_read(current_word_idx);
1360 start_bit_idx = __this_cpu_read(current_bit_idx);
1361
1362 word_idx = start_word_idx;
ab7f863e 1363
24b51c2f 1364 for (i = 0; pending_words != 0; i++) {
c81611c4 1365 xen_ulong_t words;
229664be 1366
ab7f863e
SR
1367 words = MASK_LSBS(pending_words, word_idx);
1368
1369 /*
ada6814c 1370 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1371 */
1372 if (words == 0) {
ada6814c
KF
1373 word_idx = 0;
1374 bit_idx = 0;
ab7f863e
SR
1375 continue;
1376 }
c81611c4 1377 word_idx = EVTCHN_FIRST_BIT(words);
229664be 1378
24b51c2f
KF
1379 pending_bits = active_evtchns(cpu, s, word_idx);
1380 bit_idx = 0; /* usually scan entire word from start */
3ef0296a
DV
1381 /*
1382 * We scan the starting word in two parts.
1383 *
1384 * 1st time: start in the middle, scanning the
1385 * upper bits.
1386 *
1387 * 2nd time: scan the whole word (not just the
1388 * parts skipped in the first pass) -- if an
1389 * event in the previously scanned bits is
1390 * pending again it would just be scanned on
1391 * the next loop anyway.
1392 */
24b51c2f 1393 if (word_idx == start_word_idx) {
24b51c2f 1394 if (i == 0)
24b51c2f 1395 bit_idx = start_bit_idx;
24b51c2f
KF
1396 }
1397
ab7f863e 1398 do {
c81611c4 1399 xen_ulong_t bits;
bee980d9 1400 int port;
229664be 1401
ab7f863e
SR
1402 bits = MASK_LSBS(pending_bits, bit_idx);
1403
1404 /* If we masked out all events, move on. */
ada6814c 1405 if (bits == 0)
ab7f863e 1406 break;
ab7f863e 1407
c81611c4 1408 bit_idx = EVTCHN_FIRST_BIT(bits);
ab7f863e
SR
1409
1410 /* Process port. */
c81611c4 1411 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
ab7f863e
SR
1412 irq = evtchn_to_irq[port];
1413
ca4dbc66
EB
1414 if (irq != -1) {
1415 desc = irq_to_desc(irq);
1416 if (desc)
1417 generic_handle_irq_desc(irq, desc);
1418 }
ab7f863e 1419
c81611c4 1420 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
ada6814c
KF
1421
1422 /* Next caller starts at last processed + 1 */
1423 __this_cpu_write(current_word_idx,
1424 bit_idx ? word_idx :
c81611c4 1425 (word_idx+1) % BITS_PER_EVTCHN_WORD);
ada6814c
KF
1426 __this_cpu_write(current_bit_idx, bit_idx);
1427 } while (bit_idx != 0);
ab7f863e 1428
24b51c2f
KF
1429 /* Scan start_l1i twice; all others once. */
1430 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1431 pending_words &= ~(1UL << word_idx);
ada6814c 1432
c81611c4 1433 word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
e46cdb66 1434 }
e46cdb66 1435
229664be
JF
1436 BUG_ON(!irqs_disabled());
1437
780f36d8
CL
1438 count = __this_cpu_read(xed_nesting_count);
1439 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1440 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1441
1442out:
38e20b07
SY
1443
1444 put_cpu();
1445}
1446
1447void xen_evtchn_do_upcall(struct pt_regs *regs)
1448{
1449 struct pt_regs *old_regs = set_irq_regs(regs);
1450
772aebce 1451 irq_enter();
0ec53ecf 1452#ifdef CONFIG_X86
38e20b07 1453 exit_idle();
0ec53ecf 1454#endif
38e20b07
SY
1455
1456 __xen_evtchn_do_upcall();
1457
3445a8fd
JF
1458 irq_exit();
1459 set_irq_regs(old_regs);
38e20b07 1460}
3445a8fd 1461
38e20b07
SY
1462void xen_hvm_evtchn_do_upcall(void)
1463{
1464 __xen_evtchn_do_upcall();
e46cdb66 1465}
183d03cc 1466EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1467
eb1e305f
JF
1468/* Rebind a new event channel to an existing irq. */
1469void rebind_evtchn_irq(int evtchn, int irq)
1470{
d77bbd4d
JF
1471 struct irq_info *info = info_for_irq(irq);
1472
94032c50
KRW
1473 if (WARN_ON(!info))
1474 return;
1475
eb1e305f
JF
1476 /* Make sure the irq is masked, since the new event channel
1477 will also be masked. */
1478 disable_irq(irq);
1479
77365948 1480 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1481
1482 /* After resume the irq<->evtchn mappings are all cleared out */
1483 BUG_ON(evtchn_to_irq[evtchn] != -1);
1484 /* Expect irq to have been bound before,
d77bbd4d
JF
1485 so there should be a proper type */
1486 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1487
9158c358 1488 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1489
77365948 1490 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1491
1492 /* new event channels are always bound to cpu 0 */
0de26520 1493 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1494
1495 /* Unmask the event channel. */
1496 enable_irq(irq);
1497}
1498
e46cdb66 1499/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1500static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1501{
1502 struct evtchn_bind_vcpu bind_vcpu;
1503 int evtchn = evtchn_from_irq(irq);
4704fe4f 1504 int masked;
e46cdb66 1505
be49472f
IC
1506 if (!VALID_EVTCHN(evtchn))
1507 return -1;
1508
1509 /*
1510 * Events delivered via platform PCI interrupts are always
1511 * routed to vcpu 0 and hence cannot be rebound.
1512 */
1513 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1514 return -1;
e46cdb66
JF
1515
1516 /* Send future instances of this interrupt to other vcpu. */
1517 bind_vcpu.port = evtchn;
1518 bind_vcpu.vcpu = tcpu;
1519
4704fe4f
DV
1520 /*
1521 * Mask the event while changing the VCPU binding to prevent
1522 * it being delivered on an unexpected VCPU.
1523 */
3f70fa82 1524 masked = test_and_set_mask(evtchn);
4704fe4f 1525
e46cdb66
JF
1526 /*
1527 * If this fails, it usually just indicates that we're dealing with a
1528 * virq or IPI channel, which don't actually need to be rebound. Ignore
1529 * it, but don't do the xenlinux-level rebind in that case.
1530 */
1531 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1532 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1533
4704fe4f
DV
1534 if (!masked)
1535 unmask_evtchn(evtchn);
1536
d5dedd45
YL
1537 return 0;
1538}
e46cdb66 1539
c9e265e0
TG
1540static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1541 bool force)
e46cdb66 1542{
0de26520 1543 unsigned tcpu = cpumask_first(dest);
d5dedd45 1544
c9e265e0 1545 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1546}
1547
87295185 1548static int retrigger_evtchn(int evtchn)
642e0c88 1549{
87295185 1550 int masked;
642e0c88
IY
1551
1552 if (!VALID_EVTCHN(evtchn))
87295185 1553 return 0;
642e0c88 1554
3f70fa82 1555 masked = test_and_set_mask(evtchn);
76ec8d64 1556 set_evtchn(evtchn);
642e0c88
IY
1557 if (!masked)
1558 unmask_evtchn(evtchn);
1559
1560 return 1;
1561}
1562
87295185
DV
1563int resend_irq_on_evtchn(unsigned int irq)
1564{
1565 return retrigger_evtchn(evtchn_from_irq(irq));
1566}
1567
c9e265e0 1568static void enable_dynirq(struct irq_data *data)
e46cdb66 1569{
c9e265e0 1570 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1571
1572 if (VALID_EVTCHN(evtchn))
1573 unmask_evtchn(evtchn);
1574}
1575
c9e265e0 1576static void disable_dynirq(struct irq_data *data)
e46cdb66 1577{
c9e265e0 1578 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1579
1580 if (VALID_EVTCHN(evtchn))
1581 mask_evtchn(evtchn);
1582}
1583
c9e265e0 1584static void ack_dynirq(struct irq_data *data)
e46cdb66 1585{
c9e265e0 1586 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1587
7e186bdd 1588 irq_move_irq(data);
e46cdb66
JF
1589
1590 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1591 clear_evtchn(evtchn);
1592}
1593
1594static void mask_ack_dynirq(struct irq_data *data)
1595{
1596 disable_dynirq(data);
1597 ack_dynirq(data);
e46cdb66
JF
1598}
1599
c9e265e0 1600static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1601{
87295185 1602 return retrigger_evtchn(evtchn_from_irq(data->irq));
e46cdb66
JF
1603}
1604
0a85226f 1605static void restore_pirqs(void)
9a069c33
SS
1606{
1607 int pirq, rc, irq, gsi;
1608 struct physdev_map_pirq map_irq;
69c358ce 1609 struct irq_info *info;
9a069c33 1610
69c358ce
IC
1611 list_for_each_entry(info, &xen_irq_list_head, list) {
1612 if (info->type != IRQT_PIRQ)
9a069c33
SS
1613 continue;
1614
69c358ce
IC
1615 pirq = info->u.pirq.pirq;
1616 gsi = info->u.pirq.gsi;
1617 irq = info->irq;
1618
9a069c33
SS
1619 /* save/restore of PT devices doesn't work, so at this point the
1620 * only devices present are GSI based emulated devices */
9a069c33
SS
1621 if (!gsi)
1622 continue;
1623
1624 map_irq.domid = DOMID_SELF;
1625 map_irq.type = MAP_PIRQ_TYPE_GSI;
1626 map_irq.index = gsi;
1627 map_irq.pirq = pirq;
1628
1629 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1630 if (rc) {
283c0972
JP
1631 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1632 gsi, irq, pirq, rc);
9158c358 1633 xen_free_irq(irq);
9a069c33
SS
1634 continue;
1635 }
1636
1637 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1638
c9e265e0 1639 __startup_pirq(irq);
9a069c33
SS
1640 }
1641}
1642
0e91398f
JF
1643static void restore_cpu_virqs(unsigned int cpu)
1644{
1645 struct evtchn_bind_virq bind_virq;
1646 int virq, irq, evtchn;
1647
1648 for (virq = 0; virq < NR_VIRQS; virq++) {
1649 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1650 continue;
1651
ced40d0f 1652 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1653
1654 /* Get a new binding from Xen. */
1655 bind_virq.virq = virq;
1656 bind_virq.vcpu = cpu;
1657 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1658 &bind_virq) != 0)
1659 BUG();
1660 evtchn = bind_virq.port;
1661
1662 /* Record the new mapping. */
3d4cfa37 1663 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1664 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1665 }
1666}
1667
1668static void restore_cpu_ipis(unsigned int cpu)
1669{
1670 struct evtchn_bind_ipi bind_ipi;
1671 int ipi, irq, evtchn;
1672
1673 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1674 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1675 continue;
1676
ced40d0f 1677 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1678
1679 /* Get a new binding from Xen. */
1680 bind_ipi.vcpu = cpu;
1681 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1682 &bind_ipi) != 0)
1683 BUG();
1684 evtchn = bind_ipi.port;
1685
1686 /* Record the new mapping. */
3d4cfa37 1687 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1688 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1689 }
1690}
1691
2d9e1e2f
JF
1692/* Clear an irq's pending state, in preparation for polling on it */
1693void xen_clear_irq_pending(int irq)
1694{
1695 int evtchn = evtchn_from_irq(irq);
1696
1697 if (VALID_EVTCHN(evtchn))
1698 clear_evtchn(evtchn);
1699}
d9a8814f 1700EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1701void xen_set_irq_pending(int irq)
1702{
1703 int evtchn = evtchn_from_irq(irq);
1704
1705 if (VALID_EVTCHN(evtchn))
1706 set_evtchn(evtchn);
1707}
1708
1709bool xen_test_irq_pending(int irq)
1710{
1711 int evtchn = evtchn_from_irq(irq);
1712 bool ret = false;
1713
1714 if (VALID_EVTCHN(evtchn))
1715 ret = test_evtchn(evtchn);
1716
1717 return ret;
1718}
1719
d9a8814f
KRW
1720/* Poll waiting for an irq to become pending with timeout. In the usual case,
1721 * the irq will be disabled so it won't deliver an interrupt. */
1722void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1723{
1724 evtchn_port_t evtchn = evtchn_from_irq(irq);
1725
1726 if (VALID_EVTCHN(evtchn)) {
1727 struct sched_poll poll;
1728
1729 poll.nr_ports = 1;
d9a8814f 1730 poll.timeout = timeout;
ff3c5362 1731 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1732
1733 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1734 BUG();
1735 }
1736}
d9a8814f
KRW
1737EXPORT_SYMBOL(xen_poll_irq_timeout);
1738/* Poll waiting for an irq to become pending. In the usual case, the
1739 * irq will be disabled so it won't deliver an interrupt. */
1740void xen_poll_irq(int irq)
1741{
1742 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1743}
2d9e1e2f 1744
c7c2c3a2
KRW
1745/* Check whether the IRQ line is shared with other guests. */
1746int xen_test_irq_shared(int irq)
1747{
1748 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1749 struct physdev_irq_status_query irq_status;
1750
1751 if (WARN_ON(!info))
1752 return -ENOENT;
1753
1754 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1755
1756 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1757 return 0;
1758 return !(irq_status.flags & XENIRQSTAT_shared);
1759}
1760EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1761
0e91398f
JF
1762void xen_irq_resume(void)
1763{
6cb6537d
IC
1764 unsigned int cpu, evtchn;
1765 struct irq_info *info;
0e91398f 1766
0e91398f
JF
1767 /* New event-channel space is not 'live' yet. */
1768 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1769 mask_evtchn(evtchn);
1770
1771 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1772 list_for_each_entry(info, &xen_irq_list_head, list)
1773 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1774
1775 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1776 evtchn_to_irq[evtchn] = -1;
1777
1778 for_each_possible_cpu(cpu) {
1779 restore_cpu_virqs(cpu);
1780 restore_cpu_ipis(cpu);
1781 }
6903591f 1782
0a85226f 1783 restore_pirqs();
0e91398f
JF
1784}
1785
e46cdb66 1786static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1787 .name = "xen-dyn",
54a353a0 1788
c9e265e0
TG
1789 .irq_disable = disable_dynirq,
1790 .irq_mask = disable_dynirq,
1791 .irq_unmask = enable_dynirq,
54a353a0 1792
7e186bdd
SS
1793 .irq_ack = ack_dynirq,
1794 .irq_mask_ack = mask_ack_dynirq,
1795
c9e265e0
TG
1796 .irq_set_affinity = set_affinity_irq,
1797 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1798};
1799
d46a78b0 1800static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1801 .name = "xen-pirq",
d46a78b0 1802
c9e265e0
TG
1803 .irq_startup = startup_pirq,
1804 .irq_shutdown = shutdown_pirq,
c9e265e0 1805 .irq_enable = enable_pirq,
c9e265e0 1806 .irq_disable = disable_pirq,
d46a78b0 1807
7e186bdd
SS
1808 .irq_mask = disable_dynirq,
1809 .irq_unmask = enable_dynirq,
1810
1811 .irq_ack = eoi_pirq,
1812 .irq_eoi = eoi_pirq,
1813 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1814
c9e265e0 1815 .irq_set_affinity = set_affinity_irq,
d46a78b0 1816
c9e265e0 1817 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1818};
1819
aaca4964 1820static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1821 .name = "xen-percpu",
aaca4964 1822
c9e265e0
TG
1823 .irq_disable = disable_dynirq,
1824 .irq_mask = disable_dynirq,
1825 .irq_unmask = enable_dynirq,
aaca4964 1826
c9e265e0 1827 .irq_ack = ack_dynirq,
aaca4964
JF
1828};
1829
38e20b07
SY
1830int xen_set_callback_via(uint64_t via)
1831{
1832 struct xen_hvm_param a;
1833 a.domid = DOMID_SELF;
1834 a.index = HVM_PARAM_CALLBACK_IRQ;
1835 a.value = via;
1836 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1837}
1838EXPORT_SYMBOL_GPL(xen_set_callback_via);
1839
ca65f9fc 1840#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1841/* Vector callbacks are better than PCI interrupts to receive event
1842 * channel notifications because we can receive vector callbacks on any
1843 * vcpu and we don't need PCI support or APIC interactions. */
1844void xen_callback_vector(void)
1845{
1846 int rc;
1847 uint64_t callback_via;
1848 if (xen_have_vector_callback) {
bc2b0331 1849 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1850 rc = xen_set_callback_via(callback_via);
1851 if (rc) {
283c0972 1852 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1853 xen_have_vector_callback = 0;
1854 return;
1855 }
283c0972 1856 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1857 /* in the restore case the vector has already been allocated */
bc2b0331
S
1858 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1859 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1860 xen_hvm_callback_vector);
38e20b07
SY
1861 }
1862}
ca65f9fc
SS
1863#else
1864void xen_callback_vector(void) {}
1865#endif
38e20b07 1866
2e3d8860 1867void __init xen_init_IRQ(void)
e46cdb66 1868{
0ec53ecf 1869 int i;
c7a3589e 1870
b21ddbf5
JF
1871 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1872 GFP_KERNEL);
9d093e29 1873 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1874 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1875 evtchn_to_irq[i] = -1;
e46cdb66 1876
e46cdb66
JF
1877 /* No event channels are 'live' right now. */
1878 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1879 mask_evtchn(i);
1880
9846ff10
SS
1881 pirq_needs_eoi = pirq_needs_eoi_flag;
1882
0ec53ecf 1883#ifdef CONFIG_X86
38e20b07
SY
1884 if (xen_hvm_domain()) {
1885 xen_callback_vector();
1886 native_init_IRQ();
3942b740
SS
1887 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1888 * __acpi_register_gsi can point at the right function */
1889 pci_xen_hvm_init();
38e20b07 1890 } else {
0ec53ecf 1891 int rc;
9846ff10
SS
1892 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1893
38e20b07 1894 irq_ctx_init(smp_processor_id());
38aa66fc 1895 if (xen_initial_domain())
a0ee0567 1896 pci_xen_initial_domain();
9846ff10
SS
1897
1898 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1899 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1900 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1901 if (rc != 0) {
1902 free_page((unsigned long) pirq_eoi_map);
1903 pirq_eoi_map = NULL;
1904 } else
1905 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1906 }
0ec53ecf 1907#endif
e46cdb66 1908}