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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e46cdb66 JF |
2 | /* |
3 | * Xen event channels | |
4 | * | |
5 | * Xen models interrupts with abstract event channels. Because each | |
6 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
7 | * must dynamically map irqs<->event channels. The event channels | |
8 | * interface with the rest of the kernel by defining a xen interrupt | |
25985edc | 9 | * chip. When an event is received, it is mapped to an irq and sent |
e46cdb66 JF |
10 | * through the normal interrupt processing path. |
11 | * | |
12 | * There are four kinds of events which can be mapped to an event | |
13 | * channel: | |
14 | * | |
15 | * 1. Inter-domain notifications. This includes all the virtual | |
16 | * device events, since they're driven by front-ends in another domain | |
17 | * (typically dom0). | |
18 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
19 | * 3. IPIs. | |
d46a78b0 | 20 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
21 | * |
22 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
23 | */ | |
24 | ||
283c0972 JP |
25 | #define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt |
26 | ||
e46cdb66 JF |
27 | #include <linux/linkage.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/irq.h> | |
59aa56bf | 30 | #include <linux/moduleparam.h> |
e46cdb66 | 31 | #include <linux/string.h> |
57c8a661 | 32 | #include <linux/memblock.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
b21ddbf5 | 34 | #include <linux/irqnr.h> |
f731e3ef | 35 | #include <linux/pci.h> |
e46cdb66 | 36 | |
0ec53ecf | 37 | #ifdef CONFIG_X86 |
38e20b07 | 38 | #include <asm/desc.h> |
e46cdb66 JF |
39 | #include <asm/ptrace.h> |
40 | #include <asm/irq.h> | |
0794bfc7 | 41 | #include <asm/io_apic.h> |
b4ff8389 | 42 | #include <asm/i8259.h> |
42a1de56 | 43 | #include <asm/xen/pci.h> |
0ec53ecf SS |
44 | #endif |
45 | #include <asm/sync_bitops.h> | |
e46cdb66 | 46 | #include <asm/xen/hypercall.h> |
8d1b8753 | 47 | #include <asm/xen/hypervisor.h> |
a001c9d9 | 48 | #include <xen/page.h> |
e46cdb66 | 49 | |
38e20b07 SY |
50 | #include <xen/xen.h> |
51 | #include <xen/hvm.h> | |
e04d0d07 | 52 | #include <xen/xen-ops.h> |
e46cdb66 JF |
53 | #include <xen/events.h> |
54 | #include <xen/interface/xen.h> | |
55 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
56 | #include <xen/interface/hvm/hvm_op.h> |
57 | #include <xen/interface/hvm/params.h> | |
0ec53ecf SS |
58 | #include <xen/interface/physdev.h> |
59 | #include <xen/interface/sched.h> | |
6efa20e4 | 60 | #include <xen/interface/vcpu.h> |
0ec53ecf | 61 | #include <asm/hw_irq.h> |
e46cdb66 | 62 | |
9a489f45 DV |
63 | #include "events_internal.h" |
64 | ||
ab9a1cca DV |
65 | const struct evtchn_ops *evtchn_ops; |
66 | ||
e46cdb66 JF |
67 | /* |
68 | * This lock protects updates to the following mapping and reference-count | |
69 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
70 | */ | |
77365948 | 71 | static DEFINE_MUTEX(irq_mapping_update_lock); |
e46cdb66 | 72 | |
6cb6537d IC |
73 | static LIST_HEAD(xen_irq_list_head); |
74 | ||
e46cdb66 | 75 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 76 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 77 | |
f87e4cac | 78 | /* IRQ <-> IPI mapping */ |
204fba4a | 79 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 80 | |
d0b075ff | 81 | int **evtchn_to_irq; |
bf86ad80 | 82 | #ifdef CONFIG_X86 |
9846ff10 | 83 | static unsigned long *pirq_eoi_map; |
bf86ad80 | 84 | #endif |
9846ff10 | 85 | static bool (*pirq_needs_eoi)(unsigned irq); |
3b32f574 | 86 | |
d0b075ff DV |
87 | #define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq))) |
88 | #define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq))) | |
89 | #define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq)) | |
90 | ||
e46cdb66 JF |
91 | /* Xen will never allocate port zero for any purpose. */ |
92 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
93 | ||
e46cdb66 | 94 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 95 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 96 | static struct irq_chip xen_pirq_chip; |
7e186bdd SS |
97 | static void enable_dynirq(struct irq_data *data); |
98 | static void disable_dynirq(struct irq_data *data); | |
e46cdb66 | 99 | |
d0b075ff DV |
100 | static void clear_evtchn_to_irq_row(unsigned row) |
101 | { | |
102 | unsigned col; | |
103 | ||
104 | for (col = 0; col < EVTCHN_PER_ROW; col++) | |
105 | evtchn_to_irq[row][col] = -1; | |
106 | } | |
107 | ||
108 | static void clear_evtchn_to_irq_all(void) | |
109 | { | |
110 | unsigned row; | |
111 | ||
112 | for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) { | |
113 | if (evtchn_to_irq[row] == NULL) | |
114 | continue; | |
115 | clear_evtchn_to_irq_row(row); | |
116 | } | |
117 | } | |
118 | ||
119 | static int set_evtchn_to_irq(unsigned evtchn, unsigned irq) | |
120 | { | |
121 | unsigned row; | |
122 | unsigned col; | |
123 | ||
124 | if (evtchn >= xen_evtchn_max_channels()) | |
125 | return -EINVAL; | |
126 | ||
127 | row = EVTCHN_ROW(evtchn); | |
128 | col = EVTCHN_COL(evtchn); | |
129 | ||
130 | if (evtchn_to_irq[row] == NULL) { | |
131 | /* Unallocated irq entries return -1 anyway */ | |
132 | if (irq == -1) | |
133 | return 0; | |
134 | ||
135 | evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL); | |
136 | if (evtchn_to_irq[row] == NULL) | |
137 | return -ENOMEM; | |
138 | ||
139 | clear_evtchn_to_irq_row(row); | |
140 | } | |
141 | ||
4dca864b | 142 | evtchn_to_irq[row][col] = irq; |
d0b075ff DV |
143 | return 0; |
144 | } | |
145 | ||
146 | int get_evtchn_to_irq(unsigned evtchn) | |
147 | { | |
148 | if (evtchn >= xen_evtchn_max_channels()) | |
149 | return -1; | |
150 | if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL) | |
151 | return -1; | |
152 | return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)]; | |
153 | } | |
154 | ||
9158c358 | 155 | /* Get info for IRQ */ |
9a489f45 | 156 | struct irq_info *info_for_irq(unsigned irq) |
ced40d0f | 157 | { |
c442b806 | 158 | return irq_get_handler_data(irq); |
ced40d0f JF |
159 | } |
160 | ||
9158c358 | 161 | /* Constructors for packed IRQ information. */ |
96d4c588 | 162 | static int xen_irq_info_common_setup(struct irq_info *info, |
3d4cfa37 | 163 | unsigned irq, |
9158c358 | 164 | enum xen_irq_type type, |
d0b075ff | 165 | unsigned evtchn, |
9158c358 | 166 | unsigned short cpu) |
ced40d0f | 167 | { |
d0b075ff | 168 | int ret; |
9158c358 IC |
169 | |
170 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
171 | ||
172 | info->type = type; | |
6cb6537d | 173 | info->irq = irq; |
9158c358 IC |
174 | info->evtchn = evtchn; |
175 | info->cpu = cpu; | |
3d4cfa37 | 176 | |
d0b075ff DV |
177 | ret = set_evtchn_to_irq(evtchn, irq); |
178 | if (ret < 0) | |
179 | return ret; | |
934f585e JG |
180 | |
181 | irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN); | |
96d4c588 | 182 | |
08385875 | 183 | return xen_evtchn_port_setup(info); |
ced40d0f JF |
184 | } |
185 | ||
96d4c588 | 186 | static int xen_irq_info_evtchn_setup(unsigned irq, |
d0b075ff | 187 | unsigned evtchn) |
ced40d0f | 188 | { |
9158c358 IC |
189 | struct irq_info *info = info_for_irq(irq); |
190 | ||
96d4c588 | 191 | return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
192 | } |
193 | ||
96d4c588 | 194 | static int xen_irq_info_ipi_setup(unsigned cpu, |
3d4cfa37 | 195 | unsigned irq, |
d0b075ff | 196 | unsigned evtchn, |
9158c358 | 197 | enum ipi_vector ipi) |
e46cdb66 | 198 | { |
9158c358 IC |
199 | struct irq_info *info = info_for_irq(irq); |
200 | ||
9158c358 | 201 | info->u.ipi = ipi; |
3d4cfa37 IC |
202 | |
203 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
96d4c588 DV |
204 | |
205 | return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0); | |
ced40d0f JF |
206 | } |
207 | ||
96d4c588 | 208 | static int xen_irq_info_virq_setup(unsigned cpu, |
3d4cfa37 | 209 | unsigned irq, |
d0b075ff DV |
210 | unsigned evtchn, |
211 | unsigned virq) | |
ced40d0f | 212 | { |
9158c358 IC |
213 | struct irq_info *info = info_for_irq(irq); |
214 | ||
9158c358 | 215 | info->u.virq = virq; |
3d4cfa37 IC |
216 | |
217 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
96d4c588 DV |
218 | |
219 | return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0); | |
ced40d0f JF |
220 | } |
221 | ||
96d4c588 | 222 | static int xen_irq_info_pirq_setup(unsigned irq, |
d0b075ff DV |
223 | unsigned evtchn, |
224 | unsigned pirq, | |
225 | unsigned gsi, | |
beafbdc1 | 226 | uint16_t domid, |
9158c358 | 227 | unsigned char flags) |
ced40d0f | 228 | { |
9158c358 IC |
229 | struct irq_info *info = info_for_irq(irq); |
230 | ||
9158c358 IC |
231 | info->u.pirq.pirq = pirq; |
232 | info->u.pirq.gsi = gsi; | |
beafbdc1 | 233 | info->u.pirq.domid = domid; |
9158c358 | 234 | info->u.pirq.flags = flags; |
96d4c588 DV |
235 | |
236 | return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0); | |
e46cdb66 JF |
237 | } |
238 | ||
d0b075ff DV |
239 | static void xen_irq_info_cleanup(struct irq_info *info) |
240 | { | |
241 | set_evtchn_to_irq(info->evtchn, -1); | |
242 | info->evtchn = 0; | |
243 | } | |
244 | ||
e46cdb66 JF |
245 | /* |
246 | * Accessors for packed IRQ information. | |
247 | */ | |
9a489f45 | 248 | unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 249 | { |
474b8fea | 250 | if (unlikely(WARN(irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
110e7c7e JJ |
251 | return 0; |
252 | ||
ced40d0f | 253 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
254 | } |
255 | ||
d4c04536 IC |
256 | unsigned irq_from_evtchn(unsigned int evtchn) |
257 | { | |
d0b075ff | 258 | return get_evtchn_to_irq(evtchn); |
d4c04536 IC |
259 | } |
260 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
261 | ||
9a489f45 DV |
262 | int irq_from_virq(unsigned int cpu, unsigned int virq) |
263 | { | |
264 | return per_cpu(virq_to_irq, cpu)[virq]; | |
265 | } | |
266 | ||
ced40d0f | 267 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 268 | { |
ced40d0f JF |
269 | struct irq_info *info = info_for_irq(irq); |
270 | ||
271 | BUG_ON(info == NULL); | |
272 | BUG_ON(info->type != IRQT_IPI); | |
273 | ||
274 | return info->u.ipi; | |
275 | } | |
276 | ||
277 | static unsigned virq_from_irq(unsigned irq) | |
278 | { | |
279 | struct irq_info *info = info_for_irq(irq); | |
280 | ||
281 | BUG_ON(info == NULL); | |
282 | BUG_ON(info->type != IRQT_VIRQ); | |
283 | ||
284 | return info->u.virq; | |
285 | } | |
286 | ||
7a043f11 SS |
287 | static unsigned pirq_from_irq(unsigned irq) |
288 | { | |
289 | struct irq_info *info = info_for_irq(irq); | |
290 | ||
291 | BUG_ON(info == NULL); | |
292 | BUG_ON(info->type != IRQT_PIRQ); | |
293 | ||
294 | return info->u.pirq.pirq; | |
295 | } | |
296 | ||
ced40d0f JF |
297 | static enum xen_irq_type type_from_irq(unsigned irq) |
298 | { | |
299 | return info_for_irq(irq)->type; | |
300 | } | |
301 | ||
9a489f45 | 302 | unsigned cpu_from_irq(unsigned irq) |
ced40d0f JF |
303 | { |
304 | return info_for_irq(irq)->cpu; | |
305 | } | |
306 | ||
9a489f45 | 307 | unsigned int cpu_from_evtchn(unsigned int evtchn) |
ced40d0f | 308 | { |
d0b075ff | 309 | int irq = get_evtchn_to_irq(evtchn); |
ced40d0f JF |
310 | unsigned ret = 0; |
311 | ||
312 | if (irq != -1) | |
313 | ret = cpu_from_irq(irq); | |
314 | ||
315 | return ret; | |
e46cdb66 JF |
316 | } |
317 | ||
bf86ad80 | 318 | #ifdef CONFIG_X86 |
9846ff10 | 319 | static bool pirq_check_eoi_map(unsigned irq) |
d46a78b0 | 320 | { |
521394e4 | 321 | return test_bit(pirq_from_irq(irq), pirq_eoi_map); |
9846ff10 | 322 | } |
bf86ad80 | 323 | #endif |
d46a78b0 | 324 | |
9846ff10 SS |
325 | static bool pirq_needs_eoi_flag(unsigned irq) |
326 | { | |
327 | struct irq_info *info = info_for_irq(irq); | |
d46a78b0 JF |
328 | BUG_ON(info->type != IRQT_PIRQ); |
329 | ||
330 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
331 | } | |
332 | ||
e46cdb66 JF |
333 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) |
334 | { | |
d0b075ff | 335 | int irq = get_evtchn_to_irq(chn); |
9a489f45 | 336 | struct irq_info *info = info_for_irq(irq); |
e46cdb66 JF |
337 | |
338 | BUG_ON(irq == -1); | |
339 | #ifdef CONFIG_SMP | |
c149e4cd | 340 | cpumask_copy(irq_get_affinity_mask(irq), cpumask_of(cpu)); |
e46cdb66 | 341 | #endif |
9a489f45 | 342 | xen_evtchn_port_bind_to_cpu(info, cpu); |
168d2f46 | 343 | |
9a489f45 | 344 | info->cpu = cpu; |
3f70fa82 WL |
345 | } |
346 | ||
e46cdb66 JF |
347 | /** |
348 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
349 | * @irq: irq of event channel to send event to | |
350 | * | |
351 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
352 | * save/restore. Notifications on a broken connection are silently | |
353 | * dropped. | |
354 | */ | |
355 | void notify_remote_via_irq(int irq) | |
356 | { | |
357 | int evtchn = evtchn_from_irq(irq); | |
358 | ||
359 | if (VALID_EVTCHN(evtchn)) | |
360 | notify_remote_via_evtchn(evtchn); | |
361 | } | |
362 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
363 | ||
6cb6537d IC |
364 | static void xen_irq_init(unsigned irq) |
365 | { | |
366 | struct irq_info *info; | |
b5328cd1 | 367 | #ifdef CONFIG_SMP |
6cb6537d | 368 | /* By default all event channels notify CPU#0. */ |
c149e4cd | 369 | cpumask_copy(irq_get_affinity_mask(irq), cpumask_of(0)); |
44626e4a | 370 | #endif |
6cb6537d | 371 | |
ca62ce8c IC |
372 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
373 | if (info == NULL) | |
374 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
375 | |
376 | info->type = IRQT_UNBOUND; | |
420eb554 | 377 | info->refcnt = -1; |
6cb6537d | 378 | |
c442b806 | 379 | irq_set_handler_data(irq, info); |
ca62ce8c | 380 | |
6cb6537d IC |
381 | list_add_tail(&info->list, &xen_irq_list_head); |
382 | } | |
383 | ||
4892c9b4 | 384 | static int __must_check xen_allocate_irqs_dynamic(int nvec) |
0794bfc7 | 385 | { |
d07c9f18 | 386 | int i, irq = irq_alloc_descs(-1, 0, nvec, -1); |
3a69e916 | 387 | |
4892c9b4 RPM |
388 | if (irq >= 0) { |
389 | for (i = 0; i < nvec; i++) | |
390 | xen_irq_init(irq + i); | |
391 | } | |
ced40d0f | 392 | |
e46cdb66 | 393 | return irq; |
d46a78b0 JF |
394 | } |
395 | ||
4892c9b4 RPM |
396 | static inline int __must_check xen_allocate_irq_dynamic(void) |
397 | { | |
398 | ||
399 | return xen_allocate_irqs_dynamic(1); | |
400 | } | |
401 | ||
7bee9768 | 402 | static int __must_check xen_allocate_irq_gsi(unsigned gsi) |
c9df1ce5 IC |
403 | { |
404 | int irq; | |
405 | ||
89911501 IC |
406 | /* |
407 | * A PV guest has no concept of a GSI (since it has no ACPI | |
408 | * nor access to/knowledge of the physical APICs). Therefore | |
409 | * all IRQs are dynamically allocated from the entire IRQ | |
410 | * space. | |
411 | */ | |
412 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
413 | return xen_allocate_irq_dynamic(); |
414 | ||
415 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
b4ff8389 | 416 | if (gsi < nr_legacy_irqs()) |
6cb6537d IC |
417 | irq = gsi; |
418 | else | |
419 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 420 | |
6cb6537d | 421 | xen_irq_init(irq); |
c9df1ce5 IC |
422 | |
423 | return irq; | |
424 | } | |
425 | ||
426 | static void xen_free_irq(unsigned irq) | |
427 | { | |
c442b806 | 428 | struct irq_info *info = irq_get_handler_data(irq); |
6cb6537d | 429 | |
94032c50 KRW |
430 | if (WARN_ON(!info)) |
431 | return; | |
432 | ||
6cb6537d | 433 | list_del(&info->list); |
9158c358 | 434 | |
c442b806 | 435 | irq_set_handler_data(irq, NULL); |
ca62ce8c | 436 | |
420eb554 DDG |
437 | WARN_ON(info->refcnt > 0); |
438 | ||
ca62ce8c IC |
439 | kfree(info); |
440 | ||
72146104 | 441 | /* Legacy IRQ descriptors are managed by the arch. */ |
b4ff8389 | 442 | if (irq < nr_legacy_irqs()) |
72146104 IC |
443 | return; |
444 | ||
c9df1ce5 IC |
445 | irq_free_desc(irq); |
446 | } | |
447 | ||
d0b075ff DV |
448 | static void xen_evtchn_close(unsigned int port) |
449 | { | |
450 | struct evtchn_close close; | |
451 | ||
452 | close.port = port; | |
453 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
454 | BUG(); | |
d0b075ff DV |
455 | } |
456 | ||
d46a78b0 JF |
457 | static void pirq_query_unmask(int irq) |
458 | { | |
459 | struct physdev_irq_status_query irq_status; | |
460 | struct irq_info *info = info_for_irq(irq); | |
461 | ||
462 | BUG_ON(info->type != IRQT_PIRQ); | |
463 | ||
7a043f11 | 464 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
465 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
466 | irq_status.flags = 0; | |
467 | ||
468 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
469 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
470 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
471 | } | |
472 | ||
7e186bdd SS |
473 | static void eoi_pirq(struct irq_data *data) |
474 | { | |
475 | int evtchn = evtchn_from_irq(data->irq); | |
476 | struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) }; | |
477 | int rc = 0; | |
478 | ||
ff1e22e7 BO |
479 | if (!VALID_EVTCHN(evtchn)) |
480 | return; | |
7e186bdd | 481 | |
f0f39387 RL |
482 | if (unlikely(irqd_is_setaffinity_pending(data)) && |
483 | likely(!irqd_irq_disabled(data))) { | |
ff1e22e7 BO |
484 | int masked = test_and_set_mask(evtchn); |
485 | ||
486 | clear_evtchn(evtchn); | |
487 | ||
488 | irq_move_masked_irq(data); | |
489 | ||
490 | if (!masked) | |
491 | unmask_evtchn(evtchn); | |
492 | } else | |
7e186bdd SS |
493 | clear_evtchn(evtchn); |
494 | ||
495 | if (pirq_needs_eoi(data->irq)) { | |
496 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
497 | WARN_ON(rc); | |
498 | } | |
499 | } | |
500 | ||
501 | static void mask_ack_pirq(struct irq_data *data) | |
502 | { | |
503 | disable_dynirq(data); | |
504 | eoi_pirq(data); | |
505 | } | |
506 | ||
c9e265e0 | 507 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
508 | { |
509 | struct evtchn_bind_pirq bind_pirq; | |
510 | struct irq_info *info = info_for_irq(irq); | |
511 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 512 | int rc; |
d46a78b0 JF |
513 | |
514 | BUG_ON(info->type != IRQT_PIRQ); | |
515 | ||
516 | if (VALID_EVTCHN(evtchn)) | |
517 | goto out; | |
518 | ||
7a043f11 | 519 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 520 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
521 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
522 | BIND_PIRQ__WILL_SHARE : 0; | |
523 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
524 | if (rc != 0) { | |
02893afd | 525 | pr_warn("Failed to obtain physical IRQ %d\n", irq); |
d46a78b0 JF |
526 | return 0; |
527 | } | |
528 | evtchn = bind_pirq.port; | |
529 | ||
530 | pirq_query_unmask(irq); | |
531 | ||
d0b075ff | 532 | rc = set_evtchn_to_irq(evtchn, irq); |
85e40b05 JG |
533 | if (rc) |
534 | goto err; | |
535 | ||
d46a78b0 | 536 | info->evtchn = evtchn; |
16e6bd59 | 537 | bind_evtchn_to_cpu(evtchn, 0); |
d46a78b0 | 538 | |
85e40b05 JG |
539 | rc = xen_evtchn_port_setup(info); |
540 | if (rc) | |
541 | goto err; | |
542 | ||
d46a78b0 JF |
543 | out: |
544 | unmask_evtchn(evtchn); | |
7e186bdd | 545 | eoi_pirq(irq_get_irq_data(irq)); |
d46a78b0 JF |
546 | |
547 | return 0; | |
85e40b05 JG |
548 | |
549 | err: | |
550 | pr_err("irq%d: Failed to set port to irq mapping (%d)\n", irq, rc); | |
551 | xen_evtchn_close(evtchn); | |
552 | return 0; | |
d46a78b0 JF |
553 | } |
554 | ||
c9e265e0 TG |
555 | static unsigned int startup_pirq(struct irq_data *data) |
556 | { | |
557 | return __startup_pirq(data->irq); | |
558 | } | |
559 | ||
560 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 | 561 | { |
c9e265e0 | 562 | unsigned int irq = data->irq; |
d46a78b0 | 563 | struct irq_info *info = info_for_irq(irq); |
d0b075ff | 564 | unsigned evtchn = evtchn_from_irq(irq); |
d46a78b0 JF |
565 | |
566 | BUG_ON(info->type != IRQT_PIRQ); | |
567 | ||
568 | if (!VALID_EVTCHN(evtchn)) | |
569 | return; | |
570 | ||
571 | mask_evtchn(evtchn); | |
d0b075ff DV |
572 | xen_evtchn_close(evtchn); |
573 | xen_irq_info_cleanup(info); | |
d46a78b0 JF |
574 | } |
575 | ||
c9e265e0 | 576 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 577 | { |
020db9d3 | 578 | enable_dynirq(data); |
d46a78b0 JF |
579 | } |
580 | ||
c9e265e0 | 581 | static void disable_pirq(struct irq_data *data) |
d46a78b0 | 582 | { |
7e186bdd | 583 | disable_dynirq(data); |
d46a78b0 JF |
584 | } |
585 | ||
68c2c39a | 586 | int xen_irq_from_gsi(unsigned gsi) |
d46a78b0 | 587 | { |
6cb6537d | 588 | struct irq_info *info; |
d46a78b0 | 589 | |
6cb6537d IC |
590 | list_for_each_entry(info, &xen_irq_list_head, list) { |
591 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
592 | continue; |
593 | ||
6cb6537d IC |
594 | if (info->u.pirq.gsi == gsi) |
595 | return info->irq; | |
d46a78b0 JF |
596 | } |
597 | ||
598 | return -1; | |
599 | } | |
68c2c39a | 600 | EXPORT_SYMBOL_GPL(xen_irq_from_gsi); |
d46a78b0 | 601 | |
96d4c588 DV |
602 | static void __unbind_from_irq(unsigned int irq) |
603 | { | |
96d4c588 DV |
604 | int evtchn = evtchn_from_irq(irq); |
605 | struct irq_info *info = irq_get_handler_data(irq); | |
606 | ||
607 | if (info->refcnt > 0) { | |
608 | info->refcnt--; | |
609 | if (info->refcnt != 0) | |
610 | return; | |
611 | } | |
612 | ||
613 | if (VALID_EVTCHN(evtchn)) { | |
d0b075ff DV |
614 | unsigned int cpu = cpu_from_irq(irq); |
615 | ||
616 | xen_evtchn_close(evtchn); | |
96d4c588 DV |
617 | |
618 | switch (type_from_irq(irq)) { | |
619 | case IRQT_VIRQ: | |
d0b075ff | 620 | per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1; |
96d4c588 DV |
621 | break; |
622 | case IRQT_IPI: | |
d0b075ff | 623 | per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1; |
96d4c588 DV |
624 | break; |
625 | default: | |
626 | break; | |
627 | } | |
628 | ||
d0b075ff | 629 | xen_irq_info_cleanup(info); |
96d4c588 DV |
630 | } |
631 | ||
96d4c588 DV |
632 | xen_free_irq(irq); |
633 | } | |
634 | ||
653378ac IC |
635 | /* |
636 | * Do not make any assumptions regarding the relationship between the | |
637 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
638 | * |
639 | * Note: We don't assign an event channel until the irq actually started | |
640 | * up. Return an existing irq if we've already got one for the gsi. | |
e5ac0bda SS |
641 | * |
642 | * Shareable implies level triggered, not shareable implies edge | |
643 | * triggered here. | |
d46a78b0 | 644 | */ |
f4d0635b IC |
645 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
646 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 647 | { |
a0e18116 | 648 | int irq = -1; |
d46a78b0 | 649 | struct physdev_irq irq_op; |
96d4c588 | 650 | int ret; |
d46a78b0 | 651 | |
77365948 | 652 | mutex_lock(&irq_mapping_update_lock); |
d46a78b0 | 653 | |
68c2c39a | 654 | irq = xen_irq_from_gsi(gsi); |
d46a78b0 | 655 | if (irq != -1) { |
283c0972 JP |
656 | pr_info("%s: returning irq %d for gsi %u\n", |
657 | __func__, irq, gsi); | |
420eb554 | 658 | goto out; |
d46a78b0 JF |
659 | } |
660 | ||
c9df1ce5 | 661 | irq = xen_allocate_irq_gsi(gsi); |
7bee9768 IC |
662 | if (irq < 0) |
663 | goto out; | |
d46a78b0 | 664 | |
d46a78b0 | 665 | irq_op.irq = irq; |
b5401a96 AN |
666 | irq_op.vector = 0; |
667 | ||
668 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
669 | * driver provides a PCI bus that does the call to do exactly | |
670 | * this in the priv domain. */ | |
671 | if (xen_initial_domain() && | |
672 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 673 | xen_free_irq(irq); |
d46a78b0 JF |
674 | irq = -ENOSPC; |
675 | goto out; | |
676 | } | |
677 | ||
96d4c588 | 678 | ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF, |
9158c358 | 679 | shareable ? PIRQ_SHAREABLE : 0); |
96d4c588 DV |
680 | if (ret < 0) { |
681 | __unbind_from_irq(irq); | |
682 | irq = ret; | |
683 | goto out; | |
684 | } | |
d46a78b0 | 685 | |
7e186bdd SS |
686 | pirq_query_unmask(irq); |
687 | /* We try to use the handler with the appropriate semantic for the | |
e5ac0bda SS |
688 | * type of interrupt: if the interrupt is an edge triggered |
689 | * interrupt we use handle_edge_irq. | |
7e186bdd | 690 | * |
e5ac0bda SS |
691 | * On the other hand if the interrupt is level triggered we use |
692 | * handle_fasteoi_irq like the native code does for this kind of | |
7e186bdd | 693 | * interrupts. |
e5ac0bda | 694 | * |
7e186bdd SS |
695 | * Depending on the Xen version, pirq_needs_eoi might return true |
696 | * not only for level triggered interrupts but for edge triggered | |
697 | * interrupts too. In any case Xen always honors the eoi mechanism, | |
698 | * not injecting any more pirqs of the same kind if the first one | |
699 | * hasn't received an eoi yet. Therefore using the fasteoi handler | |
700 | * is the right choice either way. | |
701 | */ | |
e5ac0bda | 702 | if (shareable) |
7e186bdd SS |
703 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, |
704 | handle_fasteoi_irq, name); | |
705 | else | |
706 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, | |
707 | handle_edge_irq, name); | |
708 | ||
d46a78b0 | 709 | out: |
77365948 | 710 | mutex_unlock(&irq_mapping_update_lock); |
d46a78b0 JF |
711 | |
712 | return irq; | |
713 | } | |
714 | ||
f731e3ef | 715 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 716 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 717 | { |
5cad61a6 | 718 | int rc; |
cbf6aa89 | 719 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 720 | |
bf480d95 | 721 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 722 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 723 | |
5cad61a6 IC |
724 | WARN_ONCE(rc == -ENOSYS, |
725 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
726 | ||
727 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
728 | } |
729 | ||
bf480d95 | 730 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
4892c9b4 | 731 | int pirq, int nvec, const char *name, domid_t domid) |
809f9267 | 732 | { |
4892c9b4 | 733 | int i, irq, ret; |
4b41df7f | 734 | |
77365948 | 735 | mutex_lock(&irq_mapping_update_lock); |
809f9267 | 736 | |
4892c9b4 | 737 | irq = xen_allocate_irqs_dynamic(nvec); |
e6599225 | 738 | if (irq < 0) |
bb5d079a | 739 | goto out; |
809f9267 | 740 | |
4892c9b4 RPM |
741 | for (i = 0; i < nvec; i++) { |
742 | irq_set_chip_and_handler_name(irq + i, &xen_pirq_chip, handle_edge_irq, name); | |
743 | ||
744 | ret = xen_irq_info_pirq_setup(irq + i, 0, pirq + i, 0, domid, | |
745 | i == 0 ? 0 : PIRQ_MSI_GROUP); | |
746 | if (ret < 0) | |
747 | goto error_irq; | |
748 | } | |
809f9267 | 749 | |
5f6fb454 | 750 | ret = irq_set_msi_desc(irq, msidesc); |
bf480d95 IC |
751 | if (ret < 0) |
752 | goto error_irq; | |
809f9267 | 753 | out: |
77365948 | 754 | mutex_unlock(&irq_mapping_update_lock); |
4b41df7f | 755 | return irq; |
bf480d95 | 756 | error_irq: |
910f8bef RPM |
757 | while (nvec--) |
758 | __unbind_from_irq(irq + nvec); | |
77365948 | 759 | mutex_unlock(&irq_mapping_update_lock); |
e6599225 | 760 | return ret; |
809f9267 | 761 | } |
f731e3ef QH |
762 | #endif |
763 | ||
b5401a96 AN |
764 | int xen_destroy_irq(int irq) |
765 | { | |
38aa66fc JF |
766 | struct physdev_unmap_pirq unmap_irq; |
767 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
768 | int rc = -ENOENT; |
769 | ||
77365948 | 770 | mutex_lock(&irq_mapping_update_lock); |
b5401a96 | 771 | |
4892c9b4 RPM |
772 | /* |
773 | * If trying to remove a vector in a MSI group different | |
774 | * than the first one skip the PIRQ unmap unless this vector | |
775 | * is the first one in the group. | |
776 | */ | |
777 | if (xen_initial_domain() && !(info->u.pirq.flags & PIRQ_MSI_GROUP)) { | |
12334715 | 778 | unmap_irq.pirq = info->u.pirq.pirq; |
beafbdc1 | 779 | unmap_irq.domid = info->u.pirq.domid; |
38aa66fc | 780 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); |
1eff1ad0 KRW |
781 | /* If another domain quits without making the pci_disable_msix |
782 | * call, the Xen hypervisor takes care of freeing the PIRQs | |
783 | * (free_domain_pirqs). | |
784 | */ | |
785 | if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF)) | |
283c0972 | 786 | pr_info("domain %d does not have %d anymore\n", |
1eff1ad0 KRW |
787 | info->u.pirq.domid, info->u.pirq.pirq); |
788 | else if (rc) { | |
283c0972 | 789 | pr_warn("unmap irq failed %d\n", rc); |
38aa66fc JF |
790 | goto out; |
791 | } | |
792 | } | |
b5401a96 | 793 | |
c9df1ce5 | 794 | xen_free_irq(irq); |
b5401a96 AN |
795 | |
796 | out: | |
77365948 | 797 | mutex_unlock(&irq_mapping_update_lock); |
b5401a96 AN |
798 | return rc; |
799 | } | |
800 | ||
af42b8d1 | 801 | int xen_irq_from_pirq(unsigned pirq) |
d46a78b0 | 802 | { |
69c358ce | 803 | int irq; |
d46a78b0 | 804 | |
69c358ce | 805 | struct irq_info *info; |
e46cdb66 | 806 | |
77365948 | 807 | mutex_lock(&irq_mapping_update_lock); |
69c358ce IC |
808 | |
809 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
9bb9efe4 | 810 | if (info->type != IRQT_PIRQ) |
69c358ce IC |
811 | continue; |
812 | irq = info->irq; | |
813 | if (info->u.pirq.pirq == pirq) | |
814 | goto out; | |
815 | } | |
816 | irq = -1; | |
817 | out: | |
77365948 | 818 | mutex_unlock(&irq_mapping_update_lock); |
69c358ce IC |
819 | |
820 | return irq; | |
af42b8d1 SS |
821 | } |
822 | ||
e6197acc KRW |
823 | |
824 | int xen_pirq_from_irq(unsigned irq) | |
825 | { | |
826 | return pirq_from_irq(irq); | |
827 | } | |
828 | EXPORT_SYMBOL_GPL(xen_pirq_from_irq); | |
96d4c588 | 829 | |
b536b4b9 | 830 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
831 | { |
832 | int irq; | |
96d4c588 | 833 | int ret; |
e46cdb66 | 834 | |
d0b075ff DV |
835 | if (evtchn >= xen_evtchn_max_channels()) |
836 | return -ENOMEM; | |
837 | ||
77365948 | 838 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 | 839 | |
d0b075ff | 840 | irq = get_evtchn_to_irq(evtchn); |
e46cdb66 JF |
841 | |
842 | if (irq == -1) { | |
c9df1ce5 | 843 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 844 | if (irq < 0) |
7bee9768 | 845 | goto out; |
e46cdb66 | 846 | |
c442b806 | 847 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, |
7e186bdd | 848 | handle_edge_irq, "event"); |
e46cdb66 | 849 | |
96d4c588 DV |
850 | ret = xen_irq_info_evtchn_setup(irq, evtchn); |
851 | if (ret < 0) { | |
852 | __unbind_from_irq(irq); | |
853 | irq = ret; | |
854 | goto out; | |
855 | } | |
97253eee DV |
856 | /* New interdomain events are bound to VCPU 0. */ |
857 | bind_evtchn_to_cpu(evtchn, 0); | |
5e152e6c KRW |
858 | } else { |
859 | struct irq_info *info = info_for_irq(irq); | |
860 | WARN_ON(info == NULL || info->type != IRQT_EVTCHN); | |
e46cdb66 JF |
861 | } |
862 | ||
7bee9768 | 863 | out: |
77365948 | 864 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
865 | |
866 | return irq; | |
867 | } | |
b536b4b9 | 868 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 869 | |
f87e4cac JF |
870 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
871 | { | |
872 | struct evtchn_bind_ipi bind_ipi; | |
873 | int evtchn, irq; | |
96d4c588 | 874 | int ret; |
f87e4cac | 875 | |
77365948 | 876 | mutex_lock(&irq_mapping_update_lock); |
f87e4cac JF |
877 | |
878 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 879 | |
f87e4cac | 880 | if (irq == -1) { |
c9df1ce5 | 881 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
882 | if (irq < 0) |
883 | goto out; | |
884 | ||
c442b806 | 885 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
aaca4964 | 886 | handle_percpu_irq, "ipi"); |
f87e4cac | 887 | |
8058c0b8 | 888 | bind_ipi.vcpu = xen_vcpu_nr(cpu); |
f87e4cac JF |
889 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, |
890 | &bind_ipi) != 0) | |
891 | BUG(); | |
892 | evtchn = bind_ipi.port; | |
893 | ||
96d4c588 DV |
894 | ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
895 | if (ret < 0) { | |
896 | __unbind_from_irq(irq); | |
897 | irq = ret; | |
898 | goto out; | |
899 | } | |
f87e4cac | 900 | bind_evtchn_to_cpu(evtchn, cpu); |
5e152e6c KRW |
901 | } else { |
902 | struct irq_info *info = info_for_irq(irq); | |
903 | WARN_ON(info == NULL || info->type != IRQT_IPI); | |
f87e4cac JF |
904 | } |
905 | ||
f87e4cac | 906 | out: |
77365948 | 907 | mutex_unlock(&irq_mapping_update_lock); |
f87e4cac JF |
908 | return irq; |
909 | } | |
910 | ||
854072dd JG |
911 | int bind_interdomain_evtchn_to_irq(unsigned int remote_domain, |
912 | unsigned int remote_port) | |
2e820f58 IC |
913 | { |
914 | struct evtchn_bind_interdomain bind_interdomain; | |
915 | int err; | |
916 | ||
917 | bind_interdomain.remote_dom = remote_domain; | |
918 | bind_interdomain.remote_port = remote_port; | |
919 | ||
920 | err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, | |
921 | &bind_interdomain); | |
922 | ||
923 | return err ? : bind_evtchn_to_irq(bind_interdomain.local_port); | |
924 | } | |
854072dd | 925 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irq); |
2e820f58 | 926 | |
62cc5fc7 OH |
927 | static int find_virq(unsigned int virq, unsigned int cpu) |
928 | { | |
929 | struct evtchn_status status; | |
930 | int port, rc = -ENOENT; | |
931 | ||
932 | memset(&status, 0, sizeof(status)); | |
d0b075ff | 933 | for (port = 0; port < xen_evtchn_max_channels(); port++) { |
62cc5fc7 OH |
934 | status.dom = DOMID_SELF; |
935 | status.port = port; | |
936 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status); | |
937 | if (rc < 0) | |
938 | continue; | |
939 | if (status.status != EVTCHNSTAT_virq) | |
940 | continue; | |
b36585a0 | 941 | if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) { |
62cc5fc7 OH |
942 | rc = port; |
943 | break; | |
944 | } | |
945 | } | |
946 | return rc; | |
947 | } | |
f87e4cac | 948 | |
0dc0064a DV |
949 | /** |
950 | * xen_evtchn_nr_channels - number of usable event channel ports | |
951 | * | |
952 | * This may be less than the maximum supported by the current | |
953 | * hypervisor ABI. Use xen_evtchn_max_channels() for the maximum | |
954 | * supported. | |
955 | */ | |
956 | unsigned xen_evtchn_nr_channels(void) | |
957 | { | |
958 | return evtchn_ops->nr_channels(); | |
959 | } | |
960 | EXPORT_SYMBOL_GPL(xen_evtchn_nr_channels); | |
961 | ||
77bb3dfd | 962 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu, bool percpu) |
e46cdb66 JF |
963 | { |
964 | struct evtchn_bind_virq bind_virq; | |
62cc5fc7 | 965 | int evtchn, irq, ret; |
e46cdb66 | 966 | |
77365948 | 967 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
968 | |
969 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
970 | ||
971 | if (irq == -1) { | |
c9df1ce5 | 972 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 973 | if (irq < 0) |
7bee9768 | 974 | goto out; |
a52521f1 | 975 | |
77bb3dfd DV |
976 | if (percpu) |
977 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, | |
978 | handle_percpu_irq, "virq"); | |
979 | else | |
980 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, | |
981 | handle_edge_irq, "virq"); | |
a52521f1 | 982 | |
e46cdb66 | 983 | bind_virq.virq = virq; |
8058c0b8 | 984 | bind_virq.vcpu = xen_vcpu_nr(cpu); |
62cc5fc7 OH |
985 | ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
986 | &bind_virq); | |
987 | if (ret == 0) | |
988 | evtchn = bind_virq.port; | |
989 | else { | |
990 | if (ret == -EEXIST) | |
991 | ret = find_virq(virq, cpu); | |
992 | BUG_ON(ret < 0); | |
993 | evtchn = ret; | |
994 | } | |
e46cdb66 | 995 | |
96d4c588 DV |
996 | ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
997 | if (ret < 0) { | |
998 | __unbind_from_irq(irq); | |
999 | irq = ret; | |
1000 | goto out; | |
1001 | } | |
e46cdb66 JF |
1002 | |
1003 | bind_evtchn_to_cpu(evtchn, cpu); | |
5e152e6c KRW |
1004 | } else { |
1005 | struct irq_info *info = info_for_irq(irq); | |
1006 | WARN_ON(info == NULL || info->type != IRQT_VIRQ); | |
e46cdb66 JF |
1007 | } |
1008 | ||
7bee9768 | 1009 | out: |
77365948 | 1010 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1011 | |
1012 | return irq; | |
1013 | } | |
1014 | ||
1015 | static void unbind_from_irq(unsigned int irq) | |
1016 | { | |
77365948 | 1017 | mutex_lock(&irq_mapping_update_lock); |
96d4c588 | 1018 | __unbind_from_irq(irq); |
77365948 | 1019 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1020 | } |
1021 | ||
1022 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 1023 | irq_handler_t handler, |
e46cdb66 JF |
1024 | unsigned long irqflags, |
1025 | const char *devname, void *dev_id) | |
1026 | { | |
361ae8cb | 1027 | int irq, retval; |
e46cdb66 JF |
1028 | |
1029 | irq = bind_evtchn_to_irq(evtchn); | |
7bee9768 IC |
1030 | if (irq < 0) |
1031 | return irq; | |
e46cdb66 JF |
1032 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1033 | if (retval != 0) { | |
1034 | unbind_from_irq(irq); | |
1035 | return retval; | |
1036 | } | |
1037 | ||
1038 | return irq; | |
1039 | } | |
1040 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
1041 | ||
2e820f58 IC |
1042 | int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain, |
1043 | unsigned int remote_port, | |
1044 | irq_handler_t handler, | |
1045 | unsigned long irqflags, | |
1046 | const char *devname, | |
1047 | void *dev_id) | |
1048 | { | |
1049 | int irq, retval; | |
1050 | ||
1051 | irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port); | |
1052 | if (irq < 0) | |
1053 | return irq; | |
1054 | ||
1055 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
1056 | if (retval != 0) { | |
1057 | unbind_from_irq(irq); | |
1058 | return retval; | |
1059 | } | |
1060 | ||
1061 | return irq; | |
1062 | } | |
1063 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler); | |
1064 | ||
e46cdb66 | 1065 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, |
7c239975 | 1066 | irq_handler_t handler, |
e46cdb66 JF |
1067 | unsigned long irqflags, const char *devname, void *dev_id) |
1068 | { | |
361ae8cb | 1069 | int irq, retval; |
e46cdb66 | 1070 | |
77bb3dfd | 1071 | irq = bind_virq_to_irq(virq, cpu, irqflags & IRQF_PERCPU); |
7bee9768 IC |
1072 | if (irq < 0) |
1073 | return irq; | |
e46cdb66 JF |
1074 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1075 | if (retval != 0) { | |
1076 | unbind_from_irq(irq); | |
1077 | return retval; | |
1078 | } | |
1079 | ||
1080 | return irq; | |
1081 | } | |
1082 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
1083 | ||
f87e4cac JF |
1084 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
1085 | unsigned int cpu, | |
1086 | irq_handler_t handler, | |
1087 | unsigned long irqflags, | |
1088 | const char *devname, | |
1089 | void *dev_id) | |
1090 | { | |
1091 | int irq, retval; | |
1092 | ||
1093 | irq = bind_ipi_to_irq(ipi, cpu); | |
1094 | if (irq < 0) | |
1095 | return irq; | |
1096 | ||
9bab0b7f | 1097 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME; |
f87e4cac JF |
1098 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1099 | if (retval != 0) { | |
1100 | unbind_from_irq(irq); | |
1101 | return retval; | |
1102 | } | |
1103 | ||
1104 | return irq; | |
1105 | } | |
1106 | ||
e46cdb66 JF |
1107 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
1108 | { | |
94032c50 KRW |
1109 | struct irq_info *info = irq_get_handler_data(irq); |
1110 | ||
1111 | if (WARN_ON(!info)) | |
1112 | return; | |
e46cdb66 JF |
1113 | free_irq(irq, dev_id); |
1114 | unbind_from_irq(irq); | |
1115 | } | |
1116 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1117 | ||
6ccecb0f DV |
1118 | /** |
1119 | * xen_set_irq_priority() - set an event channel priority. | |
1120 | * @irq:irq bound to an event channel. | |
1121 | * @priority: priority between XEN_IRQ_PRIORITY_MAX and XEN_IRQ_PRIORITY_MIN. | |
1122 | */ | |
1123 | int xen_set_irq_priority(unsigned irq, unsigned priority) | |
1124 | { | |
1125 | struct evtchn_set_priority set_priority; | |
1126 | ||
1127 | set_priority.port = evtchn_from_irq(irq); | |
1128 | set_priority.priority = priority; | |
1129 | ||
1130 | return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority, | |
1131 | &set_priority); | |
1132 | } | |
1133 | EXPORT_SYMBOL_GPL(xen_set_irq_priority); | |
1134 | ||
420eb554 DDG |
1135 | int evtchn_make_refcounted(unsigned int evtchn) |
1136 | { | |
d0b075ff | 1137 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1138 | struct irq_info *info; |
1139 | ||
1140 | if (irq == -1) | |
1141 | return -ENOENT; | |
1142 | ||
1143 | info = irq_get_handler_data(irq); | |
1144 | ||
1145 | if (!info) | |
1146 | return -ENOENT; | |
1147 | ||
1148 | WARN_ON(info->refcnt != -1); | |
1149 | ||
1150 | info->refcnt = 1; | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | EXPORT_SYMBOL_GPL(evtchn_make_refcounted); | |
1155 | ||
1156 | int evtchn_get(unsigned int evtchn) | |
1157 | { | |
1158 | int irq; | |
1159 | struct irq_info *info; | |
1160 | int err = -ENOENT; | |
1161 | ||
d0b075ff | 1162 | if (evtchn >= xen_evtchn_max_channels()) |
c3b3f16d DDG |
1163 | return -EINVAL; |
1164 | ||
420eb554 DDG |
1165 | mutex_lock(&irq_mapping_update_lock); |
1166 | ||
d0b075ff | 1167 | irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1168 | if (irq == -1) |
1169 | goto done; | |
1170 | ||
1171 | info = irq_get_handler_data(irq); | |
1172 | ||
1173 | if (!info) | |
1174 | goto done; | |
1175 | ||
1176 | err = -EINVAL; | |
1177 | if (info->refcnt <= 0) | |
1178 | goto done; | |
1179 | ||
1180 | info->refcnt++; | |
1181 | err = 0; | |
1182 | done: | |
1183 | mutex_unlock(&irq_mapping_update_lock); | |
1184 | ||
1185 | return err; | |
1186 | } | |
1187 | EXPORT_SYMBOL_GPL(evtchn_get); | |
1188 | ||
1189 | void evtchn_put(unsigned int evtchn) | |
1190 | { | |
d0b075ff | 1191 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1192 | if (WARN_ON(irq == -1)) |
1193 | return; | |
1194 | unbind_from_irq(irq); | |
1195 | } | |
1196 | EXPORT_SYMBOL_GPL(evtchn_put); | |
1197 | ||
f87e4cac JF |
1198 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1199 | { | |
6efa20e4 KRW |
1200 | int irq; |
1201 | ||
072b2064 | 1202 | #ifdef CONFIG_X86 |
6efa20e4 | 1203 | if (unlikely(vector == XEN_NMI_VECTOR)) { |
ad5475f9 VK |
1204 | int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, xen_vcpu_nr(cpu), |
1205 | NULL); | |
6efa20e4 KRW |
1206 | if (rc < 0) |
1207 | printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc); | |
1208 | return; | |
1209 | } | |
072b2064 | 1210 | #endif |
6efa20e4 | 1211 | irq = per_cpu(ipi_to_irq, cpu)[vector]; |
f87e4cac JF |
1212 | BUG_ON(irq < 0); |
1213 | notify_remote_via_irq(irq); | |
1214 | } | |
1215 | ||
245b2e70 TH |
1216 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1217 | ||
38e20b07 | 1218 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 | 1219 | { |
780f36d8 | 1220 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
9a489f45 | 1221 | int cpu = get_cpu(); |
088c05a8 | 1222 | unsigned count; |
e46cdb66 | 1223 | |
229664be | 1224 | do { |
229664be | 1225 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1226 | |
b2e4ae69 | 1227 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1228 | goto out; |
e46cdb66 | 1229 | |
9a489f45 | 1230 | xen_evtchn_handle_events(cpu); |
e46cdb66 | 1231 | |
229664be JF |
1232 | BUG_ON(!irqs_disabled()); |
1233 | ||
780f36d8 CL |
1234 | count = __this_cpu_read(xed_nesting_count); |
1235 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1236 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1237 | |
1238 | out: | |
38e20b07 SY |
1239 | |
1240 | put_cpu(); | |
1241 | } | |
1242 | ||
1243 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1244 | { | |
1245 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1246 | ||
772aebce | 1247 | irq_enter(); |
0ec53ecf | 1248 | #ifdef CONFIG_X86 |
99c8b79d | 1249 | inc_irq_stat(irq_hv_callback_count); |
d06eb3ee | 1250 | #endif |
38e20b07 SY |
1251 | |
1252 | __xen_evtchn_do_upcall(); | |
1253 | ||
3445a8fd JF |
1254 | irq_exit(); |
1255 | set_irq_regs(old_regs); | |
38e20b07 | 1256 | } |
3445a8fd | 1257 | |
38e20b07 SY |
1258 | void xen_hvm_evtchn_do_upcall(void) |
1259 | { | |
1260 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1261 | } |
183d03cc | 1262 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1263 | |
eb1e305f JF |
1264 | /* Rebind a new event channel to an existing irq. */ |
1265 | void rebind_evtchn_irq(int evtchn, int irq) | |
1266 | { | |
d77bbd4d JF |
1267 | struct irq_info *info = info_for_irq(irq); |
1268 | ||
94032c50 KRW |
1269 | if (WARN_ON(!info)) |
1270 | return; | |
1271 | ||
eb1e305f JF |
1272 | /* Make sure the irq is masked, since the new event channel |
1273 | will also be masked. */ | |
1274 | disable_irq(irq); | |
1275 | ||
77365948 | 1276 | mutex_lock(&irq_mapping_update_lock); |
eb1e305f JF |
1277 | |
1278 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
d0b075ff | 1279 | BUG_ON(get_evtchn_to_irq(evtchn) != -1); |
eb1e305f | 1280 | /* Expect irq to have been bound before, |
d77bbd4d JF |
1281 | so there should be a proper type */ |
1282 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1283 | |
96d4c588 | 1284 | (void)xen_irq_info_evtchn_setup(irq, evtchn); |
eb1e305f | 1285 | |
77365948 | 1286 | mutex_unlock(&irq_mapping_update_lock); |
eb1e305f | 1287 | |
5cec9883 BO |
1288 | bind_evtchn_to_cpu(evtchn, info->cpu); |
1289 | /* This will be deferred until interrupt is processed */ | |
1290 | irq_set_affinity(irq, cpumask_of(info->cpu)); | |
eb1e305f JF |
1291 | |
1292 | /* Unmask the event channel. */ | |
1293 | enable_irq(irq); | |
1294 | } | |
1295 | ||
e46cdb66 | 1296 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
bce5963b | 1297 | static int xen_rebind_evtchn_to_cpu(int evtchn, unsigned int tcpu) |
e46cdb66 JF |
1298 | { |
1299 | struct evtchn_bind_vcpu bind_vcpu; | |
4704fe4f | 1300 | int masked; |
e46cdb66 | 1301 | |
be49472f IC |
1302 | if (!VALID_EVTCHN(evtchn)) |
1303 | return -1; | |
1304 | ||
84d582d2 BO |
1305 | if (!xen_support_evtchn_rebind()) |
1306 | return -1; | |
1307 | ||
e46cdb66 JF |
1308 | /* Send future instances of this interrupt to other vcpu. */ |
1309 | bind_vcpu.port = evtchn; | |
8058c0b8 | 1310 | bind_vcpu.vcpu = xen_vcpu_nr(tcpu); |
e46cdb66 | 1311 | |
4704fe4f DV |
1312 | /* |
1313 | * Mask the event while changing the VCPU binding to prevent | |
1314 | * it being delivered on an unexpected VCPU. | |
1315 | */ | |
3f70fa82 | 1316 | masked = test_and_set_mask(evtchn); |
4704fe4f | 1317 | |
e46cdb66 JF |
1318 | /* |
1319 | * If this fails, it usually just indicates that we're dealing with a | |
1320 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1321 | * it, but don't do the xenlinux-level rebind in that case. | |
1322 | */ | |
1323 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1324 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1325 | |
4704fe4f DV |
1326 | if (!masked) |
1327 | unmask_evtchn(evtchn); | |
1328 | ||
d5dedd45 YL |
1329 | return 0; |
1330 | } | |
e46cdb66 | 1331 | |
c9e265e0 TG |
1332 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1333 | bool force) | |
e46cdb66 | 1334 | { |
753fbd23 | 1335 | unsigned tcpu = cpumask_first_and(dest, cpu_online_mask); |
6e6c5b96 | 1336 | int ret = xen_rebind_evtchn_to_cpu(evtchn_from_irq(data->irq), tcpu); |
d5dedd45 | 1337 | |
ef1c2cc8 TG |
1338 | if (!ret) |
1339 | irq_data_update_effective_affinity(data, cpumask_of(tcpu)); | |
1340 | ||
1341 | return ret; | |
e46cdb66 JF |
1342 | } |
1343 | ||
bce5963b JG |
1344 | /* To be called with desc->lock held. */ |
1345 | int xen_set_affinity_evtchn(struct irq_desc *desc, unsigned int tcpu) | |
1346 | { | |
1347 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1348 | ||
1349 | return set_affinity_irq(d, cpumask_of(tcpu), false); | |
1350 | } | |
1351 | EXPORT_SYMBOL_GPL(xen_set_affinity_evtchn); | |
1352 | ||
c9e265e0 | 1353 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1354 | { |
c9e265e0 | 1355 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1356 | |
1357 | if (VALID_EVTCHN(evtchn)) | |
1358 | unmask_evtchn(evtchn); | |
1359 | } | |
1360 | ||
c9e265e0 | 1361 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1362 | { |
c9e265e0 | 1363 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1364 | |
1365 | if (VALID_EVTCHN(evtchn)) | |
1366 | mask_evtchn(evtchn); | |
1367 | } | |
1368 | ||
c9e265e0 | 1369 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1370 | { |
c9e265e0 | 1371 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1372 | |
ff1e22e7 BO |
1373 | if (!VALID_EVTCHN(evtchn)) |
1374 | return; | |
e46cdb66 | 1375 | |
f0f39387 RL |
1376 | if (unlikely(irqd_is_setaffinity_pending(data)) && |
1377 | likely(!irqd_irq_disabled(data))) { | |
ff1e22e7 BO |
1378 | int masked = test_and_set_mask(evtchn); |
1379 | ||
1380 | clear_evtchn(evtchn); | |
1381 | ||
1382 | irq_move_masked_irq(data); | |
1383 | ||
1384 | if (!masked) | |
1385 | unmask_evtchn(evtchn); | |
1386 | } else | |
7e186bdd SS |
1387 | clear_evtchn(evtchn); |
1388 | } | |
1389 | ||
1390 | static void mask_ack_dynirq(struct irq_data *data) | |
1391 | { | |
1392 | disable_dynirq(data); | |
1393 | ack_dynirq(data); | |
e46cdb66 JF |
1394 | } |
1395 | ||
c9e265e0 | 1396 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1397 | { |
4640ddf5 DV |
1398 | unsigned int evtchn = evtchn_from_irq(data->irq); |
1399 | int masked; | |
1400 | ||
1401 | if (!VALID_EVTCHN(evtchn)) | |
1402 | return 0; | |
1403 | ||
1404 | masked = test_and_set_mask(evtchn); | |
1405 | set_evtchn(evtchn); | |
1406 | if (!masked) | |
1407 | unmask_evtchn(evtchn); | |
1408 | ||
1409 | return 1; | |
e46cdb66 JF |
1410 | } |
1411 | ||
0a85226f | 1412 | static void restore_pirqs(void) |
9a069c33 SS |
1413 | { |
1414 | int pirq, rc, irq, gsi; | |
1415 | struct physdev_map_pirq map_irq; | |
69c358ce | 1416 | struct irq_info *info; |
9a069c33 | 1417 | |
69c358ce IC |
1418 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1419 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1420 | continue; |
1421 | ||
69c358ce IC |
1422 | pirq = info->u.pirq.pirq; |
1423 | gsi = info->u.pirq.gsi; | |
1424 | irq = info->irq; | |
1425 | ||
9a069c33 SS |
1426 | /* save/restore of PT devices doesn't work, so at this point the |
1427 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1428 | if (!gsi) |
1429 | continue; | |
1430 | ||
1431 | map_irq.domid = DOMID_SELF; | |
1432 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1433 | map_irq.index = gsi; | |
1434 | map_irq.pirq = pirq; | |
1435 | ||
1436 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1437 | if (rc) { | |
283c0972 JP |
1438 | pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", |
1439 | gsi, irq, pirq, rc); | |
9158c358 | 1440 | xen_free_irq(irq); |
9a069c33 SS |
1441 | continue; |
1442 | } | |
1443 | ||
1444 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1445 | ||
c9e265e0 | 1446 | __startup_pirq(irq); |
9a069c33 SS |
1447 | } |
1448 | } | |
1449 | ||
0e91398f JF |
1450 | static void restore_cpu_virqs(unsigned int cpu) |
1451 | { | |
1452 | struct evtchn_bind_virq bind_virq; | |
1453 | int virq, irq, evtchn; | |
1454 | ||
1455 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1456 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1457 | continue; | |
1458 | ||
ced40d0f | 1459 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1460 | |
1461 | /* Get a new binding from Xen. */ | |
1462 | bind_virq.virq = virq; | |
8058c0b8 | 1463 | bind_virq.vcpu = xen_vcpu_nr(cpu); |
0e91398f JF |
1464 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
1465 | &bind_virq) != 0) | |
1466 | BUG(); | |
1467 | evtchn = bind_virq.port; | |
1468 | ||
1469 | /* Record the new mapping. */ | |
96d4c588 | 1470 | (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
0e91398f | 1471 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1472 | } |
1473 | } | |
1474 | ||
1475 | static void restore_cpu_ipis(unsigned int cpu) | |
1476 | { | |
1477 | struct evtchn_bind_ipi bind_ipi; | |
1478 | int ipi, irq, evtchn; | |
1479 | ||
1480 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1481 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1482 | continue; | |
1483 | ||
ced40d0f | 1484 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1485 | |
1486 | /* Get a new binding from Xen. */ | |
8058c0b8 | 1487 | bind_ipi.vcpu = xen_vcpu_nr(cpu); |
0e91398f JF |
1488 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, |
1489 | &bind_ipi) != 0) | |
1490 | BUG(); | |
1491 | evtchn = bind_ipi.port; | |
1492 | ||
1493 | /* Record the new mapping. */ | |
96d4c588 | 1494 | (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
0e91398f | 1495 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1496 | } |
1497 | } | |
1498 | ||
2d9e1e2f JF |
1499 | /* Clear an irq's pending state, in preparation for polling on it */ |
1500 | void xen_clear_irq_pending(int irq) | |
1501 | { | |
1502 | int evtchn = evtchn_from_irq(irq); | |
1503 | ||
1504 | if (VALID_EVTCHN(evtchn)) | |
1505 | clear_evtchn(evtchn); | |
1506 | } | |
d9a8814f | 1507 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1508 | void xen_set_irq_pending(int irq) |
1509 | { | |
1510 | int evtchn = evtchn_from_irq(irq); | |
1511 | ||
1512 | if (VALID_EVTCHN(evtchn)) | |
1513 | set_evtchn(evtchn); | |
1514 | } | |
1515 | ||
1516 | bool xen_test_irq_pending(int irq) | |
1517 | { | |
1518 | int evtchn = evtchn_from_irq(irq); | |
1519 | bool ret = false; | |
1520 | ||
1521 | if (VALID_EVTCHN(evtchn)) | |
1522 | ret = test_evtchn(evtchn); | |
1523 | ||
1524 | return ret; | |
1525 | } | |
1526 | ||
d9a8814f KRW |
1527 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1528 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1529 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1530 | { |
1531 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1532 | ||
1533 | if (VALID_EVTCHN(evtchn)) { | |
1534 | struct sched_poll poll; | |
1535 | ||
1536 | poll.nr_ports = 1; | |
d9a8814f | 1537 | poll.timeout = timeout; |
ff3c5362 | 1538 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1539 | |
1540 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1541 | BUG(); | |
1542 | } | |
1543 | } | |
d9a8814f KRW |
1544 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1545 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1546 | * irq will be disabled so it won't deliver an interrupt. */ | |
1547 | void xen_poll_irq(int irq) | |
1548 | { | |
1549 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1550 | } | |
2d9e1e2f | 1551 | |
c7c2c3a2 KRW |
1552 | /* Check whether the IRQ line is shared with other guests. */ |
1553 | int xen_test_irq_shared(int irq) | |
1554 | { | |
1555 | struct irq_info *info = info_for_irq(irq); | |
94032c50 KRW |
1556 | struct physdev_irq_status_query irq_status; |
1557 | ||
1558 | if (WARN_ON(!info)) | |
1559 | return -ENOENT; | |
1560 | ||
1561 | irq_status.irq = info->u.pirq.pirq; | |
c7c2c3a2 KRW |
1562 | |
1563 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) | |
1564 | return 0; | |
1565 | return !(irq_status.flags & XENIRQSTAT_shared); | |
1566 | } | |
1567 | EXPORT_SYMBOL_GPL(xen_test_irq_shared); | |
1568 | ||
0e91398f JF |
1569 | void xen_irq_resume(void) |
1570 | { | |
fd21069d | 1571 | unsigned int cpu; |
6cb6537d | 1572 | struct irq_info *info; |
0e91398f | 1573 | |
0e91398f | 1574 | /* New event-channel space is not 'live' yet. */ |
1fe56551 | 1575 | xen_evtchn_resume(); |
0e91398f JF |
1576 | |
1577 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1578 | list_for_each_entry(info, &xen_irq_list_head, list) |
1579 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f | 1580 | |
d0b075ff | 1581 | clear_evtchn_to_irq_all(); |
0e91398f JF |
1582 | |
1583 | for_each_possible_cpu(cpu) { | |
1584 | restore_cpu_virqs(cpu); | |
1585 | restore_cpu_ipis(cpu); | |
1586 | } | |
6903591f | 1587 | |
0a85226f | 1588 | restore_pirqs(); |
0e91398f JF |
1589 | } |
1590 | ||
e46cdb66 | 1591 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1592 | .name = "xen-dyn", |
54a353a0 | 1593 | |
c9e265e0 TG |
1594 | .irq_disable = disable_dynirq, |
1595 | .irq_mask = disable_dynirq, | |
1596 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1597 | |
7e186bdd SS |
1598 | .irq_ack = ack_dynirq, |
1599 | .irq_mask_ack = mask_ack_dynirq, | |
1600 | ||
c9e265e0 TG |
1601 | .irq_set_affinity = set_affinity_irq, |
1602 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1603 | }; |
1604 | ||
d46a78b0 | 1605 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1606 | .name = "xen-pirq", |
d46a78b0 | 1607 | |
c9e265e0 TG |
1608 | .irq_startup = startup_pirq, |
1609 | .irq_shutdown = shutdown_pirq, | |
c9e265e0 | 1610 | .irq_enable = enable_pirq, |
c9e265e0 | 1611 | .irq_disable = disable_pirq, |
d46a78b0 | 1612 | |
7e186bdd SS |
1613 | .irq_mask = disable_dynirq, |
1614 | .irq_unmask = enable_dynirq, | |
1615 | ||
1616 | .irq_ack = eoi_pirq, | |
1617 | .irq_eoi = eoi_pirq, | |
1618 | .irq_mask_ack = mask_ack_pirq, | |
d46a78b0 | 1619 | |
c9e265e0 | 1620 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1621 | |
c9e265e0 | 1622 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1623 | }; |
1624 | ||
aaca4964 | 1625 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1626 | .name = "xen-percpu", |
aaca4964 | 1627 | |
c9e265e0 TG |
1628 | .irq_disable = disable_dynirq, |
1629 | .irq_mask = disable_dynirq, | |
1630 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1631 | |
c9e265e0 | 1632 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1633 | }; |
1634 | ||
38e20b07 SY |
1635 | int xen_set_callback_via(uint64_t via) |
1636 | { | |
1637 | struct xen_hvm_param a; | |
1638 | a.domid = DOMID_SELF; | |
1639 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1640 | a.value = via; | |
1641 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1642 | } | |
1643 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1644 | ||
ca65f9fc | 1645 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1646 | /* Vector callbacks are better than PCI interrupts to receive event |
1647 | * channel notifications because we can receive vector callbacks on any | |
1648 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1649 | void xen_callback_vector(void) | |
1650 | { | |
1651 | int rc; | |
1652 | uint64_t callback_via; | |
72a9b186 | 1653 | |
84d582d2 BO |
1654 | if (xen_have_vector_callback) { |
1655 | callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR); | |
1656 | rc = xen_set_callback_via(callback_via); | |
1657 | if (rc) { | |
1658 | pr_err("Request for Xen HVM callback vector failed\n"); | |
1659 | xen_have_vector_callback = 0; | |
1660 | return; | |
1661 | } | |
867cefb4 | 1662 | pr_info_once("Xen HVM callback vector for event delivery is enabled\n"); |
4447ac11 TG |
1663 | alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, |
1664 | xen_hvm_callback_vector); | |
84d582d2 | 1665 | } |
38e20b07 | 1666 | } |
ca65f9fc SS |
1667 | #else |
1668 | void xen_callback_vector(void) {} | |
1669 | #endif | |
38e20b07 | 1670 | |
1fe56551 DV |
1671 | #undef MODULE_PARAM_PREFIX |
1672 | #define MODULE_PARAM_PREFIX "xen." | |
1673 | ||
1674 | static bool fifo_events = true; | |
1675 | module_param(fifo_events, bool, 0); | |
1676 | ||
2e3d8860 | 1677 | void __init xen_init_IRQ(void) |
e46cdb66 | 1678 | { |
1fe56551 | 1679 | int ret = -EINVAL; |
e91b2b11 | 1680 | unsigned int evtchn; |
1fe56551 DV |
1681 | |
1682 | if (fifo_events) | |
1683 | ret = xen_evtchn_fifo_init(); | |
1684 | if (ret < 0) | |
1685 | xen_evtchn_2l_init(); | |
ab9a1cca | 1686 | |
d0b075ff DV |
1687 | evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()), |
1688 | sizeof(*evtchn_to_irq), GFP_KERNEL); | |
9d093e29 | 1689 | BUG_ON(!evtchn_to_irq); |
e46cdb66 | 1690 | |
e46cdb66 | 1691 | /* No event channels are 'live' right now. */ |
e91b2b11 JG |
1692 | for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++) |
1693 | mask_evtchn(evtchn); | |
e46cdb66 | 1694 | |
9846ff10 SS |
1695 | pirq_needs_eoi = pirq_needs_eoi_flag; |
1696 | ||
0ec53ecf | 1697 | #ifdef CONFIG_X86 |
2771374d | 1698 | if (xen_pv_domain()) { |
2771374d MR |
1699 | if (xen_initial_domain()) |
1700 | pci_xen_initial_domain(); | |
1701 | } | |
1702 | if (xen_feature(XENFEAT_hvm_callback_vector)) | |
38e20b07 | 1703 | xen_callback_vector(); |
2771374d MR |
1704 | |
1705 | if (xen_hvm_domain()) { | |
38e20b07 | 1706 | native_init_IRQ(); |
3942b740 SS |
1707 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1708 | * __acpi_register_gsi can point at the right function */ | |
1709 | pci_xen_hvm_init(); | |
38e20b07 | 1710 | } else { |
0ec53ecf | 1711 | int rc; |
9846ff10 SS |
1712 | struct physdev_pirq_eoi_gmfn eoi_gmfn; |
1713 | ||
9846ff10 | 1714 | pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO); |
0df4f266 | 1715 | eoi_gmfn.gmfn = virt_to_gfn(pirq_eoi_map); |
9846ff10 SS |
1716 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn); |
1717 | if (rc != 0) { | |
1718 | free_page((unsigned long) pirq_eoi_map); | |
1719 | pirq_eoi_map = NULL; | |
1720 | } else | |
1721 | pirq_needs_eoi = pirq_check_eoi_map; | |
38e20b07 | 1722 | } |
0ec53ecf | 1723 | #endif |
e46cdb66 | 1724 | } |