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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
25985edc | 8 | * chip. When an event is received, it is mapped to an irq and sent |
e46cdb66 JF |
9 | * through the normal interrupt processing path. |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
f731e3ef | 32 | #include <linux/pci.h> |
e46cdb66 | 33 | |
38e20b07 | 34 | #include <asm/desc.h> |
e46cdb66 JF |
35 | #include <asm/ptrace.h> |
36 | #include <asm/irq.h> | |
792dc4f6 | 37 | #include <asm/idle.h> |
0794bfc7 | 38 | #include <asm/io_apic.h> |
e46cdb66 | 39 | #include <asm/sync_bitops.h> |
42a1de56 | 40 | #include <asm/xen/pci.h> |
e46cdb66 | 41 | #include <asm/xen/hypercall.h> |
8d1b8753 | 42 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 43 | |
38e20b07 SY |
44 | #include <xen/xen.h> |
45 | #include <xen/hvm.h> | |
e04d0d07 | 46 | #include <xen/xen-ops.h> |
e46cdb66 JF |
47 | #include <xen/events.h> |
48 | #include <xen/interface/xen.h> | |
49 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
50 | #include <xen/interface/hvm/hvm_op.h> |
51 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 52 | |
e46cdb66 JF |
53 | /* |
54 | * This lock protects updates to the following mapping and reference-count | |
55 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
56 | */ | |
57 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
58 | ||
6cb6537d IC |
59 | static LIST_HEAD(xen_irq_list_head); |
60 | ||
e46cdb66 | 61 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 62 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 63 | |
f87e4cac | 64 | /* IRQ <-> IPI mapping */ |
204fba4a | 65 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 66 | |
ced40d0f JF |
67 | /* Interrupt types. */ |
68 | enum xen_irq_type { | |
d77bbd4d | 69 | IRQT_UNBOUND = 0, |
f87e4cac JF |
70 | IRQT_PIRQ, |
71 | IRQT_VIRQ, | |
72 | IRQT_IPI, | |
73 | IRQT_EVTCHN | |
74 | }; | |
e46cdb66 | 75 | |
ced40d0f JF |
76 | /* |
77 | * Packed IRQ information: | |
78 | * type - enum xen_irq_type | |
79 | * event channel - irq->event channel mapping | |
80 | * cpu - cpu this event channel is bound to | |
81 | * index - type-specific information: | |
42a1de56 SS |
82 | * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM |
83 | * guest, or GSI (real passthrough IRQ) of the device. | |
ced40d0f JF |
84 | * VIRQ - virq number |
85 | * IPI - IPI vector | |
86 | * EVTCHN - | |
87 | */ | |
88 | struct irq_info | |
89 | { | |
6cb6537d | 90 | struct list_head list; |
ced40d0f | 91 | enum xen_irq_type type; /* type */ |
6cb6537d | 92 | unsigned irq; |
ced40d0f JF |
93 | unsigned short evtchn; /* event channel */ |
94 | unsigned short cpu; /* cpu bound */ | |
95 | ||
96 | union { | |
97 | unsigned short virq; | |
98 | enum ipi_vector ipi; | |
99 | struct { | |
7a043f11 | 100 | unsigned short pirq; |
ced40d0f | 101 | unsigned short gsi; |
d46a78b0 JF |
102 | unsigned char vector; |
103 | unsigned char flags; | |
ced40d0f JF |
104 | } pirq; |
105 | } u; | |
106 | }; | |
d46a78b0 | 107 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 108 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 109 | |
b21ddbf5 | 110 | static int *evtchn_to_irq; |
3b32f574 | 111 | |
cb60d114 IC |
112 | static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG], |
113 | cpu_evtchn_mask); | |
e46cdb66 | 114 | |
e46cdb66 JF |
115 | /* Xen will never allocate port zero for any purpose. */ |
116 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
117 | ||
e46cdb66 | 118 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 119 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 120 | static struct irq_chip xen_pirq_chip; |
e46cdb66 | 121 | |
9158c358 IC |
122 | /* Get info for IRQ */ |
123 | static struct irq_info *info_for_irq(unsigned irq) | |
ced40d0f | 124 | { |
c442b806 | 125 | return irq_get_handler_data(irq); |
ced40d0f JF |
126 | } |
127 | ||
9158c358 IC |
128 | /* Constructors for packed IRQ information. */ |
129 | static void xen_irq_info_common_init(struct irq_info *info, | |
3d4cfa37 | 130 | unsigned irq, |
9158c358 IC |
131 | enum xen_irq_type type, |
132 | unsigned short evtchn, | |
133 | unsigned short cpu) | |
ced40d0f | 134 | { |
9158c358 IC |
135 | |
136 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
137 | ||
138 | info->type = type; | |
6cb6537d | 139 | info->irq = irq; |
9158c358 IC |
140 | info->evtchn = evtchn; |
141 | info->cpu = cpu; | |
3d4cfa37 IC |
142 | |
143 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f JF |
144 | } |
145 | ||
9158c358 IC |
146 | static void xen_irq_info_evtchn_init(unsigned irq, |
147 | unsigned short evtchn) | |
ced40d0f | 148 | { |
9158c358 IC |
149 | struct irq_info *info = info_for_irq(irq); |
150 | ||
3d4cfa37 | 151 | xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
152 | } |
153 | ||
3d4cfa37 IC |
154 | static void xen_irq_info_ipi_init(unsigned cpu, |
155 | unsigned irq, | |
9158c358 IC |
156 | unsigned short evtchn, |
157 | enum ipi_vector ipi) | |
e46cdb66 | 158 | { |
9158c358 IC |
159 | struct irq_info *info = info_for_irq(irq); |
160 | ||
3d4cfa37 | 161 | xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0); |
9158c358 IC |
162 | |
163 | info->u.ipi = ipi; | |
3d4cfa37 IC |
164 | |
165 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
ced40d0f JF |
166 | } |
167 | ||
3d4cfa37 IC |
168 | static void xen_irq_info_virq_init(unsigned cpu, |
169 | unsigned irq, | |
9158c358 IC |
170 | unsigned short evtchn, |
171 | unsigned short virq) | |
ced40d0f | 172 | { |
9158c358 IC |
173 | struct irq_info *info = info_for_irq(irq); |
174 | ||
3d4cfa37 | 175 | xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0); |
9158c358 IC |
176 | |
177 | info->u.virq = virq; | |
3d4cfa37 IC |
178 | |
179 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
ced40d0f JF |
180 | } |
181 | ||
9158c358 IC |
182 | static void xen_irq_info_pirq_init(unsigned irq, |
183 | unsigned short evtchn, | |
184 | unsigned short pirq, | |
185 | unsigned short gsi, | |
186 | unsigned short vector, | |
187 | unsigned char flags) | |
ced40d0f | 188 | { |
9158c358 IC |
189 | struct irq_info *info = info_for_irq(irq); |
190 | ||
3d4cfa37 | 191 | xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0); |
9158c358 IC |
192 | |
193 | info->u.pirq.pirq = pirq; | |
194 | info->u.pirq.gsi = gsi; | |
195 | info->u.pirq.vector = vector; | |
196 | info->u.pirq.flags = flags; | |
e46cdb66 JF |
197 | } |
198 | ||
199 | /* | |
200 | * Accessors for packed IRQ information. | |
201 | */ | |
ced40d0f | 202 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 203 | { |
110e7c7e JJ |
204 | if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
205 | return 0; | |
206 | ||
ced40d0f | 207 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
208 | } |
209 | ||
d4c04536 IC |
210 | unsigned irq_from_evtchn(unsigned int evtchn) |
211 | { | |
212 | return evtchn_to_irq[evtchn]; | |
213 | } | |
214 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
215 | ||
ced40d0f | 216 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 217 | { |
ced40d0f JF |
218 | struct irq_info *info = info_for_irq(irq); |
219 | ||
220 | BUG_ON(info == NULL); | |
221 | BUG_ON(info->type != IRQT_IPI); | |
222 | ||
223 | return info->u.ipi; | |
224 | } | |
225 | ||
226 | static unsigned virq_from_irq(unsigned irq) | |
227 | { | |
228 | struct irq_info *info = info_for_irq(irq); | |
229 | ||
230 | BUG_ON(info == NULL); | |
231 | BUG_ON(info->type != IRQT_VIRQ); | |
232 | ||
233 | return info->u.virq; | |
234 | } | |
235 | ||
7a043f11 SS |
236 | static unsigned pirq_from_irq(unsigned irq) |
237 | { | |
238 | struct irq_info *info = info_for_irq(irq); | |
239 | ||
240 | BUG_ON(info == NULL); | |
241 | BUG_ON(info->type != IRQT_PIRQ); | |
242 | ||
243 | return info->u.pirq.pirq; | |
244 | } | |
245 | ||
ced40d0f JF |
246 | static enum xen_irq_type type_from_irq(unsigned irq) |
247 | { | |
248 | return info_for_irq(irq)->type; | |
249 | } | |
250 | ||
251 | static unsigned cpu_from_irq(unsigned irq) | |
252 | { | |
253 | return info_for_irq(irq)->cpu; | |
254 | } | |
255 | ||
256 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
257 | { | |
258 | int irq = evtchn_to_irq[evtchn]; | |
259 | unsigned ret = 0; | |
260 | ||
261 | if (irq != -1) | |
262 | ret = cpu_from_irq(irq); | |
263 | ||
264 | return ret; | |
e46cdb66 JF |
265 | } |
266 | ||
d46a78b0 JF |
267 | static bool pirq_needs_eoi(unsigned irq) |
268 | { | |
269 | struct irq_info *info = info_for_irq(irq); | |
270 | ||
271 | BUG_ON(info->type != IRQT_PIRQ); | |
272 | ||
273 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
274 | } | |
275 | ||
e46cdb66 JF |
276 | static inline unsigned long active_evtchns(unsigned int cpu, |
277 | struct shared_info *sh, | |
278 | unsigned int idx) | |
279 | { | |
280 | return (sh->evtchn_pending[idx] & | |
cb60d114 | 281 | per_cpu(cpu_evtchn_mask, cpu)[idx] & |
e46cdb66 JF |
282 | ~sh->evtchn_mask[idx]); |
283 | } | |
284 | ||
285 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
286 | { | |
287 | int irq = evtchn_to_irq[chn]; | |
288 | ||
289 | BUG_ON(irq == -1); | |
290 | #ifdef CONFIG_SMP | |
c9e265e0 | 291 | cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu)); |
e46cdb66 JF |
292 | #endif |
293 | ||
cb60d114 IC |
294 | clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))); |
295 | set_bit(chn, per_cpu(cpu_evtchn_mask, cpu)); | |
e46cdb66 | 296 | |
ca62ce8c | 297 | info_for_irq(irq)->cpu = cpu; |
e46cdb66 JF |
298 | } |
299 | ||
300 | static void init_evtchn_cpu_bindings(void) | |
301 | { | |
1c6969ec | 302 | int i; |
e46cdb66 | 303 | #ifdef CONFIG_SMP |
6cb6537d | 304 | struct irq_info *info; |
10e58084 | 305 | |
e46cdb66 | 306 | /* By default all event channels notify CPU#0. */ |
6cb6537d IC |
307 | list_for_each_entry(info, &xen_irq_list_head, list) { |
308 | struct irq_desc *desc = irq_to_desc(info->irq); | |
c9e265e0 | 309 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); |
0b8f1efa | 310 | } |
e46cdb66 JF |
311 | #endif |
312 | ||
1c6969ec | 313 | for_each_possible_cpu(i) |
cb60d114 IC |
314 | memset(per_cpu(cpu_evtchn_mask, i), |
315 | (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i))); | |
e46cdb66 JF |
316 | } |
317 | ||
e46cdb66 JF |
318 | static inline void clear_evtchn(int port) |
319 | { | |
320 | struct shared_info *s = HYPERVISOR_shared_info; | |
321 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
322 | } | |
323 | ||
324 | static inline void set_evtchn(int port) | |
325 | { | |
326 | struct shared_info *s = HYPERVISOR_shared_info; | |
327 | sync_set_bit(port, &s->evtchn_pending[0]); | |
328 | } | |
329 | ||
168d2f46 JF |
330 | static inline int test_evtchn(int port) |
331 | { | |
332 | struct shared_info *s = HYPERVISOR_shared_info; | |
333 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
334 | } | |
335 | ||
e46cdb66 JF |
336 | |
337 | /** | |
338 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
339 | * @irq: irq of event channel to send event to | |
340 | * | |
341 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
342 | * save/restore. Notifications on a broken connection are silently | |
343 | * dropped. | |
344 | */ | |
345 | void notify_remote_via_irq(int irq) | |
346 | { | |
347 | int evtchn = evtchn_from_irq(irq); | |
348 | ||
349 | if (VALID_EVTCHN(evtchn)) | |
350 | notify_remote_via_evtchn(evtchn); | |
351 | } | |
352 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
353 | ||
354 | static void mask_evtchn(int port) | |
355 | { | |
356 | struct shared_info *s = HYPERVISOR_shared_info; | |
357 | sync_set_bit(port, &s->evtchn_mask[0]); | |
358 | } | |
359 | ||
360 | static void unmask_evtchn(int port) | |
361 | { | |
362 | struct shared_info *s = HYPERVISOR_shared_info; | |
363 | unsigned int cpu = get_cpu(); | |
364 | ||
365 | BUG_ON(!irqs_disabled()); | |
366 | ||
367 | /* Slow path (hypercall) if this is a non-local port. */ | |
368 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
369 | struct evtchn_unmask unmask = { .port = port }; | |
370 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
371 | } else { | |
780f36d8 | 372 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
e46cdb66 JF |
373 | |
374 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
375 | ||
376 | /* | |
377 | * The following is basically the equivalent of | |
378 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
379 | * the interrupt edge' if the channel is masked. | |
380 | */ | |
381 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
382 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
383 | &vcpu_info->evtchn_pending_sel)) | |
384 | vcpu_info->evtchn_upcall_pending = 1; | |
385 | } | |
386 | ||
387 | put_cpu(); | |
388 | } | |
389 | ||
6cb6537d IC |
390 | static void xen_irq_init(unsigned irq) |
391 | { | |
392 | struct irq_info *info; | |
393 | struct irq_desc *desc = irq_to_desc(irq); | |
394 | ||
44626e4a | 395 | #ifdef CONFIG_SMP |
6cb6537d IC |
396 | /* By default all event channels notify CPU#0. */ |
397 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); | |
44626e4a | 398 | #endif |
6cb6537d | 399 | |
ca62ce8c IC |
400 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
401 | if (info == NULL) | |
402 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
403 | |
404 | info->type = IRQT_UNBOUND; | |
405 | ||
c442b806 | 406 | irq_set_handler_data(irq, info); |
ca62ce8c | 407 | |
6cb6537d IC |
408 | list_add_tail(&info->list, &xen_irq_list_head); |
409 | } | |
410 | ||
7bee9768 | 411 | static int __must_check xen_allocate_irq_dynamic(void) |
0794bfc7 | 412 | { |
89911501 IC |
413 | int first = 0; |
414 | int irq; | |
0794bfc7 KRW |
415 | |
416 | #ifdef CONFIG_X86_IO_APIC | |
89911501 IC |
417 | /* |
418 | * For an HVM guest or domain 0 which see "real" (emulated or | |
25985edc | 419 | * actual respectively) GSIs we allocate dynamic IRQs |
89911501 IC |
420 | * e.g. those corresponding to event channels or MSIs |
421 | * etc. from the range above those "real" GSIs to avoid | |
422 | * collisions. | |
423 | */ | |
424 | if (xen_initial_domain() || xen_hvm_domain()) | |
425 | first = get_nr_irqs_gsi(); | |
0794bfc7 KRW |
426 | #endif |
427 | ||
89911501 | 428 | irq = irq_alloc_desc_from(first, -1); |
3a69e916 | 429 | |
6cb6537d | 430 | xen_irq_init(irq); |
ced40d0f | 431 | |
e46cdb66 | 432 | return irq; |
d46a78b0 JF |
433 | } |
434 | ||
7bee9768 | 435 | static int __must_check xen_allocate_irq_gsi(unsigned gsi) |
c9df1ce5 IC |
436 | { |
437 | int irq; | |
438 | ||
89911501 IC |
439 | /* |
440 | * A PV guest has no concept of a GSI (since it has no ACPI | |
441 | * nor access to/knowledge of the physical APICs). Therefore | |
442 | * all IRQs are dynamically allocated from the entire IRQ | |
443 | * space. | |
444 | */ | |
445 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
446 | return xen_allocate_irq_dynamic(); |
447 | ||
448 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
449 | if (gsi < NR_IRQS_LEGACY) | |
6cb6537d IC |
450 | irq = gsi; |
451 | else | |
452 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 453 | |
6cb6537d | 454 | xen_irq_init(irq); |
c9df1ce5 IC |
455 | |
456 | return irq; | |
457 | } | |
458 | ||
459 | static void xen_free_irq(unsigned irq) | |
460 | { | |
c442b806 | 461 | struct irq_info *info = irq_get_handler_data(irq); |
6cb6537d IC |
462 | |
463 | list_del(&info->list); | |
9158c358 | 464 | |
c442b806 | 465 | irq_set_handler_data(irq, NULL); |
ca62ce8c IC |
466 | |
467 | kfree(info); | |
468 | ||
72146104 IC |
469 | /* Legacy IRQ descriptors are managed by the arch. */ |
470 | if (irq < NR_IRQS_LEGACY) | |
471 | return; | |
472 | ||
c9df1ce5 IC |
473 | irq_free_desc(irq); |
474 | } | |
475 | ||
d46a78b0 JF |
476 | static void pirq_unmask_notify(int irq) |
477 | { | |
7a043f11 | 478 | struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) }; |
d46a78b0 JF |
479 | |
480 | if (unlikely(pirq_needs_eoi(irq))) { | |
481 | int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
482 | WARN_ON(rc); | |
483 | } | |
484 | } | |
485 | ||
486 | static void pirq_query_unmask(int irq) | |
487 | { | |
488 | struct physdev_irq_status_query irq_status; | |
489 | struct irq_info *info = info_for_irq(irq); | |
490 | ||
491 | BUG_ON(info->type != IRQT_PIRQ); | |
492 | ||
7a043f11 | 493 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
494 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
495 | irq_status.flags = 0; | |
496 | ||
497 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
498 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
499 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
500 | } | |
501 | ||
502 | static bool probing_irq(int irq) | |
503 | { | |
504 | struct irq_desc *desc = irq_to_desc(irq); | |
505 | ||
506 | return desc && desc->action == NULL; | |
507 | } | |
508 | ||
c9e265e0 | 509 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
510 | { |
511 | struct evtchn_bind_pirq bind_pirq; | |
512 | struct irq_info *info = info_for_irq(irq); | |
513 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 514 | int rc; |
d46a78b0 JF |
515 | |
516 | BUG_ON(info->type != IRQT_PIRQ); | |
517 | ||
518 | if (VALID_EVTCHN(evtchn)) | |
519 | goto out; | |
520 | ||
7a043f11 | 521 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 522 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
523 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
524 | BIND_PIRQ__WILL_SHARE : 0; | |
525 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
526 | if (rc != 0) { | |
d46a78b0 JF |
527 | if (!probing_irq(irq)) |
528 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
529 | irq); | |
530 | return 0; | |
531 | } | |
532 | evtchn = bind_pirq.port; | |
533 | ||
534 | pirq_query_unmask(irq); | |
535 | ||
536 | evtchn_to_irq[evtchn] = irq; | |
537 | bind_evtchn_to_cpu(evtchn, 0); | |
538 | info->evtchn = evtchn; | |
539 | ||
540 | out: | |
541 | unmask_evtchn(evtchn); | |
542 | pirq_unmask_notify(irq); | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
c9e265e0 TG |
547 | static unsigned int startup_pirq(struct irq_data *data) |
548 | { | |
549 | return __startup_pirq(data->irq); | |
550 | } | |
551 | ||
552 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 JF |
553 | { |
554 | struct evtchn_close close; | |
c9e265e0 | 555 | unsigned int irq = data->irq; |
d46a78b0 JF |
556 | struct irq_info *info = info_for_irq(irq); |
557 | int evtchn = evtchn_from_irq(irq); | |
558 | ||
559 | BUG_ON(info->type != IRQT_PIRQ); | |
560 | ||
561 | if (!VALID_EVTCHN(evtchn)) | |
562 | return; | |
563 | ||
564 | mask_evtchn(evtchn); | |
565 | ||
566 | close.port = evtchn; | |
567 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
568 | BUG(); | |
569 | ||
570 | bind_evtchn_to_cpu(evtchn, 0); | |
571 | evtchn_to_irq[evtchn] = -1; | |
572 | info->evtchn = 0; | |
573 | } | |
574 | ||
c9e265e0 | 575 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 576 | { |
c9e265e0 | 577 | startup_pirq(data); |
d46a78b0 JF |
578 | } |
579 | ||
c9e265e0 | 580 | static void disable_pirq(struct irq_data *data) |
d46a78b0 JF |
581 | { |
582 | } | |
583 | ||
c9e265e0 | 584 | static void ack_pirq(struct irq_data *data) |
d46a78b0 | 585 | { |
c9e265e0 | 586 | int evtchn = evtchn_from_irq(data->irq); |
d46a78b0 | 587 | |
a3b975c4 | 588 | irq_move_irq(data); |
d46a78b0 JF |
589 | |
590 | if (VALID_EVTCHN(evtchn)) { | |
591 | mask_evtchn(evtchn); | |
592 | clear_evtchn(evtchn); | |
593 | } | |
594 | } | |
595 | ||
d46a78b0 JF |
596 | static int find_irq_by_gsi(unsigned gsi) |
597 | { | |
6cb6537d | 598 | struct irq_info *info; |
d46a78b0 | 599 | |
6cb6537d IC |
600 | list_for_each_entry(info, &xen_irq_list_head, list) { |
601 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
602 | continue; |
603 | ||
6cb6537d IC |
604 | if (info->u.pirq.gsi == gsi) |
605 | return info->irq; | |
d46a78b0 JF |
606 | } |
607 | ||
608 | return -1; | |
609 | } | |
610 | ||
f4d0635b | 611 | int xen_allocate_pirq_gsi(unsigned gsi) |
7a043f11 | 612 | { |
f4d0635b | 613 | return gsi; |
7a043f11 SS |
614 | } |
615 | ||
653378ac IC |
616 | /* |
617 | * Do not make any assumptions regarding the relationship between the | |
618 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
619 | * |
620 | * Note: We don't assign an event channel until the irq actually started | |
621 | * up. Return an existing irq if we've already got one for the gsi. | |
d46a78b0 | 622 | */ |
f4d0635b IC |
623 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
624 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 625 | { |
a0e18116 | 626 | int irq = -1; |
d46a78b0 JF |
627 | struct physdev_irq irq_op; |
628 | ||
629 | spin_lock(&irq_mapping_update_lock); | |
630 | ||
631 | irq = find_irq_by_gsi(gsi); | |
632 | if (irq != -1) { | |
7a043f11 | 633 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 JF |
634 | irq, gsi); |
635 | goto out; /* XXX need refcount? */ | |
636 | } | |
637 | ||
c9df1ce5 | 638 | irq = xen_allocate_irq_gsi(gsi); |
7bee9768 IC |
639 | if (irq < 0) |
640 | goto out; | |
d46a78b0 | 641 | |
c442b806 TG |
642 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq, |
643 | name); | |
d46a78b0 JF |
644 | |
645 | irq_op.irq = irq; | |
b5401a96 AN |
646 | irq_op.vector = 0; |
647 | ||
648 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
649 | * driver provides a PCI bus that does the call to do exactly | |
650 | * this in the priv domain. */ | |
651 | if (xen_initial_domain() && | |
652 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 653 | xen_free_irq(irq); |
d46a78b0 JF |
654 | irq = -ENOSPC; |
655 | goto out; | |
656 | } | |
657 | ||
9158c358 IC |
658 | xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, |
659 | shareable ? PIRQ_SHAREABLE : 0); | |
d46a78b0 JF |
660 | |
661 | out: | |
662 | spin_unlock(&irq_mapping_update_lock); | |
663 | ||
664 | return irq; | |
665 | } | |
666 | ||
f731e3ef | 667 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 668 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 669 | { |
5cad61a6 | 670 | int rc; |
cbf6aa89 | 671 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 672 | |
bf480d95 | 673 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 674 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 675 | |
5cad61a6 IC |
676 | WARN_ONCE(rc == -ENOSYS, |
677 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
678 | ||
679 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
680 | } |
681 | ||
bf480d95 | 682 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
ca1d8fe9 | 683 | int pirq, int vector, const char *name) |
809f9267 | 684 | { |
bf480d95 | 685 | int irq, ret; |
4b41df7f | 686 | |
809f9267 SS |
687 | spin_lock(&irq_mapping_update_lock); |
688 | ||
4b41df7f IC |
689 | irq = xen_allocate_irq_dynamic(); |
690 | if (irq == -1) | |
bb5d079a | 691 | goto out; |
809f9267 | 692 | |
c442b806 TG |
693 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq, |
694 | name); | |
809f9267 | 695 | |
9158c358 | 696 | xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0); |
5f6fb454 | 697 | ret = irq_set_msi_desc(irq, msidesc); |
bf480d95 IC |
698 | if (ret < 0) |
699 | goto error_irq; | |
809f9267 SS |
700 | out: |
701 | spin_unlock(&irq_mapping_update_lock); | |
4b41df7f | 702 | return irq; |
bf480d95 IC |
703 | error_irq: |
704 | spin_unlock(&irq_mapping_update_lock); | |
705 | xen_free_irq(irq); | |
706 | return -1; | |
809f9267 | 707 | } |
f731e3ef QH |
708 | #endif |
709 | ||
b5401a96 AN |
710 | int xen_destroy_irq(int irq) |
711 | { | |
712 | struct irq_desc *desc; | |
38aa66fc JF |
713 | struct physdev_unmap_pirq unmap_irq; |
714 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
715 | int rc = -ENOENT; |
716 | ||
717 | spin_lock(&irq_mapping_update_lock); | |
718 | ||
719 | desc = irq_to_desc(irq); | |
720 | if (!desc) | |
721 | goto out; | |
722 | ||
38aa66fc | 723 | if (xen_initial_domain()) { |
12334715 | 724 | unmap_irq.pirq = info->u.pirq.pirq; |
38aa66fc JF |
725 | unmap_irq.domid = DOMID_SELF; |
726 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); | |
727 | if (rc) { | |
728 | printk(KERN_WARNING "unmap irq failed %d\n", rc); | |
729 | goto out; | |
730 | } | |
731 | } | |
b5401a96 | 732 | |
c9df1ce5 | 733 | xen_free_irq(irq); |
b5401a96 AN |
734 | |
735 | out: | |
736 | spin_unlock(&irq_mapping_update_lock); | |
737 | return rc; | |
738 | } | |
739 | ||
af42b8d1 | 740 | int xen_irq_from_pirq(unsigned pirq) |
d46a78b0 | 741 | { |
69c358ce | 742 | int irq; |
d46a78b0 | 743 | |
69c358ce | 744 | struct irq_info *info; |
e46cdb66 | 745 | |
69c358ce IC |
746 | spin_lock(&irq_mapping_update_lock); |
747 | ||
748 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
749 | if (info == NULL || info->type != IRQT_PIRQ) | |
750 | continue; | |
751 | irq = info->irq; | |
752 | if (info->u.pirq.pirq == pirq) | |
753 | goto out; | |
754 | } | |
755 | irq = -1; | |
756 | out: | |
a7b807ce | 757 | spin_unlock(&irq_mapping_update_lock); |
69c358ce IC |
758 | |
759 | return irq; | |
af42b8d1 SS |
760 | } |
761 | ||
b536b4b9 | 762 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
763 | { |
764 | int irq; | |
765 | ||
766 | spin_lock(&irq_mapping_update_lock); | |
767 | ||
768 | irq = evtchn_to_irq[evtchn]; | |
769 | ||
770 | if (irq == -1) { | |
c9df1ce5 | 771 | irq = xen_allocate_irq_dynamic(); |
7bee9768 IC |
772 | if (irq == -1) |
773 | goto out; | |
e46cdb66 | 774 | |
c442b806 | 775 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, |
3588fe2e | 776 | handle_fasteoi_irq, "event"); |
e46cdb66 | 777 | |
9158c358 | 778 | xen_irq_info_evtchn_init(irq, evtchn); |
e46cdb66 JF |
779 | } |
780 | ||
7bee9768 | 781 | out: |
e46cdb66 JF |
782 | spin_unlock(&irq_mapping_update_lock); |
783 | ||
784 | return irq; | |
785 | } | |
b536b4b9 | 786 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 787 | |
f87e4cac JF |
788 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
789 | { | |
790 | struct evtchn_bind_ipi bind_ipi; | |
791 | int evtchn, irq; | |
792 | ||
793 | spin_lock(&irq_mapping_update_lock); | |
794 | ||
795 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 796 | |
f87e4cac | 797 | if (irq == -1) { |
c9df1ce5 | 798 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
799 | if (irq < 0) |
800 | goto out; | |
801 | ||
c442b806 | 802 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
aaca4964 | 803 | handle_percpu_irq, "ipi"); |
f87e4cac JF |
804 | |
805 | bind_ipi.vcpu = cpu; | |
806 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
807 | &bind_ipi) != 0) | |
808 | BUG(); | |
809 | evtchn = bind_ipi.port; | |
810 | ||
3d4cfa37 | 811 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
f87e4cac JF |
812 | |
813 | bind_evtchn_to_cpu(evtchn, cpu); | |
814 | } | |
815 | ||
f87e4cac JF |
816 | out: |
817 | spin_unlock(&irq_mapping_update_lock); | |
818 | return irq; | |
819 | } | |
820 | ||
2e820f58 IC |
821 | static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain, |
822 | unsigned int remote_port) | |
823 | { | |
824 | struct evtchn_bind_interdomain bind_interdomain; | |
825 | int err; | |
826 | ||
827 | bind_interdomain.remote_dom = remote_domain; | |
828 | bind_interdomain.remote_port = remote_port; | |
829 | ||
830 | err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, | |
831 | &bind_interdomain); | |
832 | ||
833 | return err ? : bind_evtchn_to_irq(bind_interdomain.local_port); | |
834 | } | |
835 | ||
f87e4cac | 836 | |
4fe7d5a7 | 837 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
838 | { |
839 | struct evtchn_bind_virq bind_virq; | |
840 | int evtchn, irq; | |
841 | ||
842 | spin_lock(&irq_mapping_update_lock); | |
843 | ||
844 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
845 | ||
846 | if (irq == -1) { | |
c9df1ce5 | 847 | irq = xen_allocate_irq_dynamic(); |
7bee9768 IC |
848 | if (irq == -1) |
849 | goto out; | |
a52521f1 | 850 | |
c442b806 | 851 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
a52521f1 JF |
852 | handle_percpu_irq, "virq"); |
853 | ||
e46cdb66 JF |
854 | bind_virq.virq = virq; |
855 | bind_virq.vcpu = cpu; | |
856 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
857 | &bind_virq) != 0) | |
858 | BUG(); | |
859 | evtchn = bind_virq.port; | |
860 | ||
3d4cfa37 | 861 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
e46cdb66 JF |
862 | |
863 | bind_evtchn_to_cpu(evtchn, cpu); | |
864 | } | |
865 | ||
7bee9768 | 866 | out: |
e46cdb66 JF |
867 | spin_unlock(&irq_mapping_update_lock); |
868 | ||
869 | return irq; | |
870 | } | |
871 | ||
872 | static void unbind_from_irq(unsigned int irq) | |
873 | { | |
874 | struct evtchn_close close; | |
875 | int evtchn = evtchn_from_irq(irq); | |
876 | ||
877 | spin_lock(&irq_mapping_update_lock); | |
878 | ||
d77bbd4d | 879 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
880 | close.port = evtchn; |
881 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
882 | BUG(); | |
883 | ||
884 | switch (type_from_irq(irq)) { | |
885 | case IRQT_VIRQ: | |
886 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 887 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 888 | break; |
d68d82af AN |
889 | case IRQT_IPI: |
890 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 891 | [ipi_from_irq(irq)] = -1; |
d68d82af | 892 | break; |
e46cdb66 JF |
893 | default: |
894 | break; | |
895 | } | |
896 | ||
897 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
898 | bind_evtchn_to_cpu(evtchn, 0); | |
899 | ||
900 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
901 | } |
902 | ||
ca62ce8c | 903 | BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND); |
e46cdb66 | 904 | |
9158c358 | 905 | xen_free_irq(irq); |
e46cdb66 JF |
906 | |
907 | spin_unlock(&irq_mapping_update_lock); | |
908 | } | |
909 | ||
910 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 911 | irq_handler_t handler, |
e46cdb66 JF |
912 | unsigned long irqflags, |
913 | const char *devname, void *dev_id) | |
914 | { | |
361ae8cb | 915 | int irq, retval; |
e46cdb66 JF |
916 | |
917 | irq = bind_evtchn_to_irq(evtchn); | |
7bee9768 IC |
918 | if (irq < 0) |
919 | return irq; | |
e46cdb66 JF |
920 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
921 | if (retval != 0) { | |
922 | unbind_from_irq(irq); | |
923 | return retval; | |
924 | } | |
925 | ||
926 | return irq; | |
927 | } | |
928 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
929 | ||
2e820f58 IC |
930 | int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain, |
931 | unsigned int remote_port, | |
932 | irq_handler_t handler, | |
933 | unsigned long irqflags, | |
934 | const char *devname, | |
935 | void *dev_id) | |
936 | { | |
937 | int irq, retval; | |
938 | ||
939 | irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port); | |
940 | if (irq < 0) | |
941 | return irq; | |
942 | ||
943 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
944 | if (retval != 0) { | |
945 | unbind_from_irq(irq); | |
946 | return retval; | |
947 | } | |
948 | ||
949 | return irq; | |
950 | } | |
951 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler); | |
952 | ||
e46cdb66 | 953 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, |
7c239975 | 954 | irq_handler_t handler, |
e46cdb66 JF |
955 | unsigned long irqflags, const char *devname, void *dev_id) |
956 | { | |
361ae8cb | 957 | int irq, retval; |
e46cdb66 JF |
958 | |
959 | irq = bind_virq_to_irq(virq, cpu); | |
7bee9768 IC |
960 | if (irq < 0) |
961 | return irq; | |
e46cdb66 JF |
962 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
963 | if (retval != 0) { | |
964 | unbind_from_irq(irq); | |
965 | return retval; | |
966 | } | |
967 | ||
968 | return irq; | |
969 | } | |
970 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
971 | ||
f87e4cac JF |
972 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
973 | unsigned int cpu, | |
974 | irq_handler_t handler, | |
975 | unsigned long irqflags, | |
976 | const char *devname, | |
977 | void *dev_id) | |
978 | { | |
979 | int irq, retval; | |
980 | ||
981 | irq = bind_ipi_to_irq(ipi, cpu); | |
982 | if (irq < 0) | |
983 | return irq; | |
984 | ||
676dc3cf | 985 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME; |
f87e4cac JF |
986 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
987 | if (retval != 0) { | |
988 | unbind_from_irq(irq); | |
989 | return retval; | |
990 | } | |
991 | ||
992 | return irq; | |
993 | } | |
994 | ||
e46cdb66 JF |
995 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
996 | { | |
997 | free_irq(irq, dev_id); | |
998 | unbind_from_irq(irq); | |
999 | } | |
1000 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1001 | ||
f87e4cac JF |
1002 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1003 | { | |
1004 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
1005 | BUG_ON(irq < 0); | |
1006 | notify_remote_via_irq(irq); | |
1007 | } | |
1008 | ||
ee523ca1 JF |
1009 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
1010 | { | |
1011 | struct shared_info *sh = HYPERVISOR_shared_info; | |
1012 | int cpu = smp_processor_id(); | |
cb60d114 | 1013 | unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu); |
ee523ca1 JF |
1014 | int i; |
1015 | unsigned long flags; | |
1016 | static DEFINE_SPINLOCK(debug_lock); | |
cb52e6d9 | 1017 | struct vcpu_info *v; |
ee523ca1 JF |
1018 | |
1019 | spin_lock_irqsave(&debug_lock, flags); | |
1020 | ||
cb52e6d9 | 1021 | printk("\nvcpu %d\n ", cpu); |
ee523ca1 JF |
1022 | |
1023 | for_each_online_cpu(i) { | |
cb52e6d9 IC |
1024 | int pending; |
1025 | v = per_cpu(xen_vcpu, i); | |
1026 | pending = (get_irq_regs() && i == cpu) | |
1027 | ? xen_irqs_disabled(get_irq_regs()) | |
1028 | : v->evtchn_upcall_mask; | |
1029 | printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i, | |
1030 | pending, v->evtchn_upcall_pending, | |
1031 | (int)(sizeof(v->evtchn_pending_sel)*2), | |
1032 | v->evtchn_pending_sel); | |
1033 | } | |
1034 | v = per_cpu(xen_vcpu, cpu); | |
1035 | ||
1036 | printk("\npending:\n "); | |
1037 | for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
1038 | printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2, | |
1039 | sh->evtchn_pending[i], | |
1040 | i % 8 == 0 ? "\n " : " "); | |
1041 | printk("\nglobal mask:\n "); | |
1042 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1043 | printk("%0*lx%s", | |
1044 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
1045 | sh->evtchn_mask[i], | |
1046 | i % 8 == 0 ? "\n " : " "); | |
1047 | ||
1048 | printk("\nglobally unmasked:\n "); | |
1049 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1050 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1051 | sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
1052 | i % 8 == 0 ? "\n " : " "); | |
1053 | ||
1054 | printk("\nlocal cpu%d mask:\n ", cpu); | |
1055 | for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--) | |
1056 | printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2), | |
1057 | cpu_evtchn[i], | |
1058 | i % 8 == 0 ? "\n " : " "); | |
1059 | ||
1060 | printk("\nlocally unmasked:\n "); | |
1061 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) { | |
1062 | unsigned long pending = sh->evtchn_pending[i] | |
1063 | & ~sh->evtchn_mask[i] | |
1064 | & cpu_evtchn[i]; | |
1065 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1066 | pending, i % 8 == 0 ? "\n " : " "); | |
ee523ca1 | 1067 | } |
ee523ca1 JF |
1068 | |
1069 | printk("\npending list:\n"); | |
cb52e6d9 | 1070 | for (i = 0; i < NR_EVENT_CHANNELS; i++) { |
ee523ca1 | 1071 | if (sync_test_bit(i, sh->evtchn_pending)) { |
cb52e6d9 IC |
1072 | int word_idx = i / BITS_PER_LONG; |
1073 | printk(" %d: event %d -> irq %d%s%s%s\n", | |
ced40d0f | 1074 | cpu_from_evtchn(i), i, |
cb52e6d9 IC |
1075 | evtchn_to_irq[i], |
1076 | sync_test_bit(word_idx, &v->evtchn_pending_sel) | |
1077 | ? "" : " l2-clear", | |
1078 | !sync_test_bit(i, sh->evtchn_mask) | |
1079 | ? "" : " globally-masked", | |
1080 | sync_test_bit(i, cpu_evtchn) | |
1081 | ? "" : " locally-masked"); | |
ee523ca1 JF |
1082 | } |
1083 | } | |
1084 | ||
1085 | spin_unlock_irqrestore(&debug_lock, flags); | |
1086 | ||
1087 | return IRQ_HANDLED; | |
1088 | } | |
1089 | ||
245b2e70 | 1090 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
ada6814c KF |
1091 | static DEFINE_PER_CPU(unsigned int, current_word_idx); |
1092 | static DEFINE_PER_CPU(unsigned int, current_bit_idx); | |
245b2e70 | 1093 | |
ab7f863e SR |
1094 | /* |
1095 | * Mask out the i least significant bits of w | |
1096 | */ | |
1097 | #define MASK_LSBS(w, i) (w & ((~0UL) << i)) | |
245b2e70 | 1098 | |
e46cdb66 JF |
1099 | /* |
1100 | * Search the CPUs pending events bitmasks. For each one found, map | |
1101 | * the event number to an irq, and feed it into do_IRQ() for | |
1102 | * handling. | |
1103 | * | |
1104 | * Xen uses a two-level bitmap to speed searching. The first level is | |
1105 | * a bitset of words which contain pending event bits. The second | |
1106 | * level is a bitset of pending events themselves. | |
1107 | */ | |
38e20b07 | 1108 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 | 1109 | { |
24b51c2f | 1110 | int start_word_idx, start_bit_idx; |
ab7f863e | 1111 | int word_idx, bit_idx; |
24b51c2f | 1112 | int i; |
e46cdb66 JF |
1113 | int cpu = get_cpu(); |
1114 | struct shared_info *s = HYPERVISOR_shared_info; | |
780f36d8 | 1115 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
229664be | 1116 | unsigned count; |
e46cdb66 | 1117 | |
229664be JF |
1118 | do { |
1119 | unsigned long pending_words; | |
e46cdb66 | 1120 | |
229664be | 1121 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1122 | |
b2e4ae69 | 1123 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1124 | goto out; |
e46cdb66 | 1125 | |
e849c3e9 IY |
1126 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
1127 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 1128 | wmb(); |
e849c3e9 | 1129 | #endif |
229664be | 1130 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
ab7f863e | 1131 | |
24b51c2f KF |
1132 | start_word_idx = __this_cpu_read(current_word_idx); |
1133 | start_bit_idx = __this_cpu_read(current_bit_idx); | |
1134 | ||
1135 | word_idx = start_word_idx; | |
ab7f863e | 1136 | |
24b51c2f | 1137 | for (i = 0; pending_words != 0; i++) { |
229664be | 1138 | unsigned long pending_bits; |
ab7f863e | 1139 | unsigned long words; |
229664be | 1140 | |
ab7f863e SR |
1141 | words = MASK_LSBS(pending_words, word_idx); |
1142 | ||
1143 | /* | |
ada6814c | 1144 | * If we masked out all events, wrap to beginning. |
ab7f863e SR |
1145 | */ |
1146 | if (words == 0) { | |
ada6814c KF |
1147 | word_idx = 0; |
1148 | bit_idx = 0; | |
ab7f863e SR |
1149 | continue; |
1150 | } | |
1151 | word_idx = __ffs(words); | |
229664be | 1152 | |
24b51c2f KF |
1153 | pending_bits = active_evtchns(cpu, s, word_idx); |
1154 | bit_idx = 0; /* usually scan entire word from start */ | |
1155 | if (word_idx == start_word_idx) { | |
1156 | /* We scan the starting word in two parts */ | |
1157 | if (i == 0) | |
1158 | /* 1st time: start in the middle */ | |
1159 | bit_idx = start_bit_idx; | |
1160 | else | |
1161 | /* 2nd time: mask bits done already */ | |
1162 | bit_idx &= (1UL << start_bit_idx) - 1; | |
1163 | } | |
1164 | ||
ab7f863e SR |
1165 | do { |
1166 | unsigned long bits; | |
1167 | int port, irq; | |
ca4dbc66 | 1168 | struct irq_desc *desc; |
229664be | 1169 | |
ab7f863e SR |
1170 | bits = MASK_LSBS(pending_bits, bit_idx); |
1171 | ||
1172 | /* If we masked out all events, move on. */ | |
ada6814c | 1173 | if (bits == 0) |
ab7f863e | 1174 | break; |
ab7f863e SR |
1175 | |
1176 | bit_idx = __ffs(bits); | |
1177 | ||
1178 | /* Process port. */ | |
1179 | port = (word_idx * BITS_PER_LONG) + bit_idx; | |
1180 | irq = evtchn_to_irq[port]; | |
1181 | ||
3588fe2e JF |
1182 | mask_evtchn(port); |
1183 | clear_evtchn(port); | |
1184 | ||
ca4dbc66 EB |
1185 | if (irq != -1) { |
1186 | desc = irq_to_desc(irq); | |
1187 | if (desc) | |
1188 | generic_handle_irq_desc(irq, desc); | |
1189 | } | |
ab7f863e | 1190 | |
ada6814c KF |
1191 | bit_idx = (bit_idx + 1) % BITS_PER_LONG; |
1192 | ||
1193 | /* Next caller starts at last processed + 1 */ | |
1194 | __this_cpu_write(current_word_idx, | |
1195 | bit_idx ? word_idx : | |
1196 | (word_idx+1) % BITS_PER_LONG); | |
1197 | __this_cpu_write(current_bit_idx, bit_idx); | |
1198 | } while (bit_idx != 0); | |
ab7f863e | 1199 | |
24b51c2f KF |
1200 | /* Scan start_l1i twice; all others once. */ |
1201 | if ((word_idx != start_word_idx) || (i != 0)) | |
ab7f863e | 1202 | pending_words &= ~(1UL << word_idx); |
ada6814c KF |
1203 | |
1204 | word_idx = (word_idx + 1) % BITS_PER_LONG; | |
e46cdb66 | 1205 | } |
e46cdb66 | 1206 | |
229664be JF |
1207 | BUG_ON(!irqs_disabled()); |
1208 | ||
780f36d8 CL |
1209 | count = __this_cpu_read(xed_nesting_count); |
1210 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1211 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1212 | |
1213 | out: | |
38e20b07 SY |
1214 | |
1215 | put_cpu(); | |
1216 | } | |
1217 | ||
1218 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1219 | { | |
1220 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1221 | ||
1222 | exit_idle(); | |
1223 | irq_enter(); | |
1224 | ||
1225 | __xen_evtchn_do_upcall(); | |
1226 | ||
3445a8fd JF |
1227 | irq_exit(); |
1228 | set_irq_regs(old_regs); | |
38e20b07 | 1229 | } |
3445a8fd | 1230 | |
38e20b07 SY |
1231 | void xen_hvm_evtchn_do_upcall(void) |
1232 | { | |
1233 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1234 | } |
183d03cc | 1235 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1236 | |
eb1e305f JF |
1237 | /* Rebind a new event channel to an existing irq. */ |
1238 | void rebind_evtchn_irq(int evtchn, int irq) | |
1239 | { | |
d77bbd4d JF |
1240 | struct irq_info *info = info_for_irq(irq); |
1241 | ||
eb1e305f JF |
1242 | /* Make sure the irq is masked, since the new event channel |
1243 | will also be masked. */ | |
1244 | disable_irq(irq); | |
1245 | ||
1246 | spin_lock(&irq_mapping_update_lock); | |
1247 | ||
1248 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1249 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1250 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1251 | so there should be a proper type */ |
1252 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1253 | |
9158c358 | 1254 | xen_irq_info_evtchn_init(irq, evtchn); |
eb1e305f JF |
1255 | |
1256 | spin_unlock(&irq_mapping_update_lock); | |
1257 | ||
1258 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1259 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1260 | |
1261 | /* Unmask the event channel. */ | |
1262 | enable_irq(irq); | |
1263 | } | |
1264 | ||
e46cdb66 | 1265 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1266 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1267 | { |
1268 | struct evtchn_bind_vcpu bind_vcpu; | |
1269 | int evtchn = evtchn_from_irq(irq); | |
1270 | ||
be49472f IC |
1271 | if (!VALID_EVTCHN(evtchn)) |
1272 | return -1; | |
1273 | ||
1274 | /* | |
1275 | * Events delivered via platform PCI interrupts are always | |
1276 | * routed to vcpu 0 and hence cannot be rebound. | |
1277 | */ | |
1278 | if (xen_hvm_domain() && !xen_have_vector_callback) | |
d5dedd45 | 1279 | return -1; |
e46cdb66 JF |
1280 | |
1281 | /* Send future instances of this interrupt to other vcpu. */ | |
1282 | bind_vcpu.port = evtchn; | |
1283 | bind_vcpu.vcpu = tcpu; | |
1284 | ||
1285 | /* | |
1286 | * If this fails, it usually just indicates that we're dealing with a | |
1287 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1288 | * it, but don't do the xenlinux-level rebind in that case. | |
1289 | */ | |
1290 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1291 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1292 | |
d5dedd45 YL |
1293 | return 0; |
1294 | } | |
e46cdb66 | 1295 | |
c9e265e0 TG |
1296 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1297 | bool force) | |
e46cdb66 | 1298 | { |
0de26520 | 1299 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 | 1300 | |
c9e265e0 | 1301 | return rebind_irq_to_cpu(data->irq, tcpu); |
e46cdb66 JF |
1302 | } |
1303 | ||
642e0c88 IY |
1304 | int resend_irq_on_evtchn(unsigned int irq) |
1305 | { | |
1306 | int masked, evtchn = evtchn_from_irq(irq); | |
1307 | struct shared_info *s = HYPERVISOR_shared_info; | |
1308 | ||
1309 | if (!VALID_EVTCHN(evtchn)) | |
1310 | return 1; | |
1311 | ||
1312 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1313 | sync_set_bit(evtchn, s->evtchn_pending); | |
1314 | if (!masked) | |
1315 | unmask_evtchn(evtchn); | |
1316 | ||
1317 | return 1; | |
1318 | } | |
1319 | ||
c9e265e0 | 1320 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1321 | { |
c9e265e0 | 1322 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1323 | |
1324 | if (VALID_EVTCHN(evtchn)) | |
1325 | unmask_evtchn(evtchn); | |
1326 | } | |
1327 | ||
c9e265e0 | 1328 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1329 | { |
c9e265e0 | 1330 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1331 | |
1332 | if (VALID_EVTCHN(evtchn)) | |
1333 | mask_evtchn(evtchn); | |
1334 | } | |
1335 | ||
c9e265e0 | 1336 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1337 | { |
c9e265e0 | 1338 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1339 | |
a3b975c4 | 1340 | irq_move_masked_irq(data); |
e46cdb66 JF |
1341 | |
1342 | if (VALID_EVTCHN(evtchn)) | |
3588fe2e | 1343 | unmask_evtchn(evtchn); |
e46cdb66 JF |
1344 | } |
1345 | ||
c9e265e0 | 1346 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1347 | { |
c9e265e0 | 1348 | int evtchn = evtchn_from_irq(data->irq); |
ee8fa1c6 | 1349 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1350 | int ret = 0; |
1351 | ||
1352 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1353 | int masked; |
1354 | ||
1355 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1356 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1357 | if (!masked) | |
1358 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1359 | ret = 1; |
1360 | } | |
1361 | ||
1362 | return ret; | |
1363 | } | |
1364 | ||
0a85226f | 1365 | static void restore_pirqs(void) |
9a069c33 SS |
1366 | { |
1367 | int pirq, rc, irq, gsi; | |
1368 | struct physdev_map_pirq map_irq; | |
69c358ce | 1369 | struct irq_info *info; |
9a069c33 | 1370 | |
69c358ce IC |
1371 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1372 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1373 | continue; |
1374 | ||
69c358ce IC |
1375 | pirq = info->u.pirq.pirq; |
1376 | gsi = info->u.pirq.gsi; | |
1377 | irq = info->irq; | |
1378 | ||
9a069c33 SS |
1379 | /* save/restore of PT devices doesn't work, so at this point the |
1380 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1381 | if (!gsi) |
1382 | continue; | |
1383 | ||
1384 | map_irq.domid = DOMID_SELF; | |
1385 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1386 | map_irq.index = gsi; | |
1387 | map_irq.pirq = pirq; | |
1388 | ||
1389 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1390 | if (rc) { | |
1391 | printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", | |
1392 | gsi, irq, pirq, rc); | |
9158c358 | 1393 | xen_free_irq(irq); |
9a069c33 SS |
1394 | continue; |
1395 | } | |
1396 | ||
1397 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1398 | ||
c9e265e0 | 1399 | __startup_pirq(irq); |
9a069c33 SS |
1400 | } |
1401 | } | |
1402 | ||
0e91398f JF |
1403 | static void restore_cpu_virqs(unsigned int cpu) |
1404 | { | |
1405 | struct evtchn_bind_virq bind_virq; | |
1406 | int virq, irq, evtchn; | |
1407 | ||
1408 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1409 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1410 | continue; | |
1411 | ||
ced40d0f | 1412 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1413 | |
1414 | /* Get a new binding from Xen. */ | |
1415 | bind_virq.virq = virq; | |
1416 | bind_virq.vcpu = cpu; | |
1417 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1418 | &bind_virq) != 0) | |
1419 | BUG(); | |
1420 | evtchn = bind_virq.port; | |
1421 | ||
1422 | /* Record the new mapping. */ | |
3d4cfa37 | 1423 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
0e91398f | 1424 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1425 | } |
1426 | } | |
1427 | ||
1428 | static void restore_cpu_ipis(unsigned int cpu) | |
1429 | { | |
1430 | struct evtchn_bind_ipi bind_ipi; | |
1431 | int ipi, irq, evtchn; | |
1432 | ||
1433 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1434 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1435 | continue; | |
1436 | ||
ced40d0f | 1437 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1438 | |
1439 | /* Get a new binding from Xen. */ | |
1440 | bind_ipi.vcpu = cpu; | |
1441 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1442 | &bind_ipi) != 0) | |
1443 | BUG(); | |
1444 | evtchn = bind_ipi.port; | |
1445 | ||
1446 | /* Record the new mapping. */ | |
3d4cfa37 | 1447 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
0e91398f | 1448 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1449 | } |
1450 | } | |
1451 | ||
2d9e1e2f JF |
1452 | /* Clear an irq's pending state, in preparation for polling on it */ |
1453 | void xen_clear_irq_pending(int irq) | |
1454 | { | |
1455 | int evtchn = evtchn_from_irq(irq); | |
1456 | ||
1457 | if (VALID_EVTCHN(evtchn)) | |
1458 | clear_evtchn(evtchn); | |
1459 | } | |
d9a8814f | 1460 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1461 | void xen_set_irq_pending(int irq) |
1462 | { | |
1463 | int evtchn = evtchn_from_irq(irq); | |
1464 | ||
1465 | if (VALID_EVTCHN(evtchn)) | |
1466 | set_evtchn(evtchn); | |
1467 | } | |
1468 | ||
1469 | bool xen_test_irq_pending(int irq) | |
1470 | { | |
1471 | int evtchn = evtchn_from_irq(irq); | |
1472 | bool ret = false; | |
1473 | ||
1474 | if (VALID_EVTCHN(evtchn)) | |
1475 | ret = test_evtchn(evtchn); | |
1476 | ||
1477 | return ret; | |
1478 | } | |
1479 | ||
d9a8814f KRW |
1480 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1481 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1482 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1483 | { |
1484 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1485 | ||
1486 | if (VALID_EVTCHN(evtchn)) { | |
1487 | struct sched_poll poll; | |
1488 | ||
1489 | poll.nr_ports = 1; | |
d9a8814f | 1490 | poll.timeout = timeout; |
ff3c5362 | 1491 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1492 | |
1493 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1494 | BUG(); | |
1495 | } | |
1496 | } | |
d9a8814f KRW |
1497 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1498 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1499 | * irq will be disabled so it won't deliver an interrupt. */ | |
1500 | void xen_poll_irq(int irq) | |
1501 | { | |
1502 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1503 | } | |
2d9e1e2f | 1504 | |
0e91398f JF |
1505 | void xen_irq_resume(void) |
1506 | { | |
6cb6537d IC |
1507 | unsigned int cpu, evtchn; |
1508 | struct irq_info *info; | |
0e91398f JF |
1509 | |
1510 | init_evtchn_cpu_bindings(); | |
1511 | ||
1512 | /* New event-channel space is not 'live' yet. */ | |
1513 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1514 | mask_evtchn(evtchn); | |
1515 | ||
1516 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1517 | list_for_each_entry(info, &xen_irq_list_head, list) |
1518 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f JF |
1519 | |
1520 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1521 | evtchn_to_irq[evtchn] = -1; | |
1522 | ||
1523 | for_each_possible_cpu(cpu) { | |
1524 | restore_cpu_virqs(cpu); | |
1525 | restore_cpu_ipis(cpu); | |
1526 | } | |
6903591f | 1527 | |
0a85226f | 1528 | restore_pirqs(); |
0e91398f JF |
1529 | } |
1530 | ||
e46cdb66 | 1531 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1532 | .name = "xen-dyn", |
54a353a0 | 1533 | |
c9e265e0 TG |
1534 | .irq_disable = disable_dynirq, |
1535 | .irq_mask = disable_dynirq, | |
1536 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1537 | |
c9e265e0 TG |
1538 | .irq_eoi = ack_dynirq, |
1539 | .irq_set_affinity = set_affinity_irq, | |
1540 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1541 | }; |
1542 | ||
d46a78b0 | 1543 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1544 | .name = "xen-pirq", |
d46a78b0 | 1545 | |
c9e265e0 TG |
1546 | .irq_startup = startup_pirq, |
1547 | .irq_shutdown = shutdown_pirq, | |
d46a78b0 | 1548 | |
c9e265e0 TG |
1549 | .irq_enable = enable_pirq, |
1550 | .irq_unmask = enable_pirq, | |
d46a78b0 | 1551 | |
c9e265e0 TG |
1552 | .irq_disable = disable_pirq, |
1553 | .irq_mask = disable_pirq, | |
d46a78b0 | 1554 | |
c9e265e0 | 1555 | .irq_ack = ack_pirq, |
d46a78b0 | 1556 | |
c9e265e0 | 1557 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1558 | |
c9e265e0 | 1559 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1560 | }; |
1561 | ||
aaca4964 | 1562 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1563 | .name = "xen-percpu", |
aaca4964 | 1564 | |
c9e265e0 TG |
1565 | .irq_disable = disable_dynirq, |
1566 | .irq_mask = disable_dynirq, | |
1567 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1568 | |
c9e265e0 | 1569 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1570 | }; |
1571 | ||
38e20b07 SY |
1572 | int xen_set_callback_via(uint64_t via) |
1573 | { | |
1574 | struct xen_hvm_param a; | |
1575 | a.domid = DOMID_SELF; | |
1576 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1577 | a.value = via; | |
1578 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1579 | } | |
1580 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1581 | ||
ca65f9fc | 1582 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1583 | /* Vector callbacks are better than PCI interrupts to receive event |
1584 | * channel notifications because we can receive vector callbacks on any | |
1585 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1586 | void xen_callback_vector(void) | |
1587 | { | |
1588 | int rc; | |
1589 | uint64_t callback_via; | |
1590 | if (xen_have_vector_callback) { | |
1591 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1592 | rc = xen_set_callback_via(callback_via); | |
1593 | if (rc) { | |
1594 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1595 | " failed.\n"); | |
1596 | xen_have_vector_callback = 0; | |
1597 | return; | |
1598 | } | |
1599 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1600 | "enabled\n"); | |
1601 | /* in the restore case the vector has already been allocated */ | |
1602 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1603 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1604 | } | |
1605 | } | |
ca65f9fc SS |
1606 | #else |
1607 | void xen_callback_vector(void) {} | |
1608 | #endif | |
38e20b07 | 1609 | |
e46cdb66 JF |
1610 | void __init xen_init_IRQ(void) |
1611 | { | |
e5fc7345 | 1612 | int i; |
c7a3589e | 1613 | |
b21ddbf5 JF |
1614 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1615 | GFP_KERNEL); | |
1616 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1617 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1618 | |
1619 | init_evtchn_cpu_bindings(); | |
1620 | ||
1621 | /* No event channels are 'live' right now. */ | |
1622 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1623 | mask_evtchn(i); | |
1624 | ||
38e20b07 SY |
1625 | if (xen_hvm_domain()) { |
1626 | xen_callback_vector(); | |
1627 | native_init_IRQ(); | |
3942b740 SS |
1628 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1629 | * __acpi_register_gsi can point at the right function */ | |
1630 | pci_xen_hvm_init(); | |
38e20b07 SY |
1631 | } else { |
1632 | irq_ctx_init(smp_processor_id()); | |
38aa66fc JF |
1633 | if (xen_initial_domain()) |
1634 | xen_setup_pirqs(); | |
38e20b07 | 1635 | } |
e46cdb66 | 1636 | } |