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e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
0ec53ecf 34#ifdef CONFIG_X86
38e20b07 35#include <asm/desc.h>
e46cdb66
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36#include <asm/ptrace.h>
37#include <asm/irq.h>
792dc4f6 38#include <asm/idle.h>
0794bfc7 39#include <asm/io_apic.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
0ec53ecf
SS
42#endif
43#include <asm/sync_bitops.h>
e46cdb66 44#include <asm/xen/hypercall.h>
8d1b8753 45#include <asm/xen/hypervisor.h>
e46cdb66 46
38e20b07
SY
47#include <xen/xen.h>
48#include <xen/hvm.h>
e04d0d07 49#include <xen/xen-ops.h>
e46cdb66
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50#include <xen/events.h>
51#include <xen/interface/xen.h>
52#include <xen/interface/event_channel.h>
38e20b07
SY
53#include <xen/interface/hvm/hvm_op.h>
54#include <xen/interface/hvm/params.h>
0ec53ecf
SS
55#include <xen/interface/physdev.h>
56#include <xen/interface/sched.h>
57#include <asm/hw_irq.h>
e46cdb66 58
e46cdb66
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59/*
60 * This lock protects updates to the following mapping and reference-count
61 * arrays. The lock does not need to be acquired to read the mapping tables.
62 */
77365948 63static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 64
6cb6537d
IC
65static LIST_HEAD(xen_irq_list_head);
66
e46cdb66 67/* IRQ <-> VIRQ mapping. */
204fba4a 68static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 69
f87e4cac 70/* IRQ <-> IPI mapping */
204fba4a 71static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 72
ced40d0f
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73/* Interrupt types. */
74enum xen_irq_type {
d77bbd4d 75 IRQT_UNBOUND = 0,
f87e4cac
JF
76 IRQT_PIRQ,
77 IRQT_VIRQ,
78 IRQT_IPI,
79 IRQT_EVTCHN
80};
e46cdb66 81
ced40d0f
JF
82/*
83 * Packed IRQ information:
84 * type - enum xen_irq_type
85 * event channel - irq->event channel mapping
86 * cpu - cpu this event channel is bound to
87 * index - type-specific information:
42a1de56
SS
88 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
89 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
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90 * VIRQ - virq number
91 * IPI - IPI vector
92 * EVTCHN -
93 */
088c05a8 94struct irq_info {
6cb6537d 95 struct list_head list;
420eb554 96 int refcnt;
ced40d0f 97 enum xen_irq_type type; /* type */
6cb6537d 98 unsigned irq;
ced40d0f
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99 unsigned short evtchn; /* event channel */
100 unsigned short cpu; /* cpu bound */
101
102 union {
103 unsigned short virq;
104 enum ipi_vector ipi;
105 struct {
7a043f11 106 unsigned short pirq;
ced40d0f 107 unsigned short gsi;
d46a78b0
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108 unsigned char vector;
109 unsigned char flags;
beafbdc1 110 uint16_t domid;
ced40d0f
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111 } pirq;
112 } u;
113};
d46a78b0 114#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 115#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 116
b21ddbf5 117static int *evtchn_to_irq;
bf86ad80 118#ifdef CONFIG_X86
9846ff10 119static unsigned long *pirq_eoi_map;
bf86ad80 120#endif
9846ff10 121static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 122
c81611c4
IC
123/*
124 * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
125 * careful to only use bitops which allow for this (e.g
126 * test_bit/find_first_bit and friends but not __ffs) and to pass
127 * BITS_PER_EVTCHN_WORD as the bitmask length.
128 */
129#define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
130/*
131 * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
132 * array. Primarily to avoid long lines (hence the terse name).
133 */
134#define BM(x) (unsigned long *)(x)
135/* Find the first set bit in a evtchn mask */
136#define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
137
138static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
cb60d114 139 cpu_evtchn_mask);
e46cdb66 140
e46cdb66
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141/* Xen will never allocate port zero for any purpose. */
142#define VALID_EVTCHN(chn) ((chn) != 0)
143
e46cdb66 144static struct irq_chip xen_dynamic_chip;
aaca4964 145static struct irq_chip xen_percpu_chip;
d46a78b0 146static struct irq_chip xen_pirq_chip;
7e186bdd
SS
147static void enable_dynirq(struct irq_data *data);
148static void disable_dynirq(struct irq_data *data);
e46cdb66 149
9158c358
IC
150/* Get info for IRQ */
151static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 152{
c442b806 153 return irq_get_handler_data(irq);
ced40d0f
JF
154}
155
9158c358
IC
156/* Constructors for packed IRQ information. */
157static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 158 unsigned irq,
9158c358
IC
159 enum xen_irq_type type,
160 unsigned short evtchn,
161 unsigned short cpu)
ced40d0f 162{
9158c358
IC
163
164 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
165
166 info->type = type;
6cb6537d 167 info->irq = irq;
9158c358
IC
168 info->evtchn = evtchn;
169 info->cpu = cpu;
3d4cfa37
IC
170
171 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
172}
173
9158c358
IC
174static void xen_irq_info_evtchn_init(unsigned irq,
175 unsigned short evtchn)
ced40d0f 176{
9158c358
IC
177 struct irq_info *info = info_for_irq(irq);
178
3d4cfa37 179 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
180}
181
3d4cfa37
IC
182static void xen_irq_info_ipi_init(unsigned cpu,
183 unsigned irq,
9158c358
IC
184 unsigned short evtchn,
185 enum ipi_vector ipi)
e46cdb66 186{
9158c358
IC
187 struct irq_info *info = info_for_irq(irq);
188
3d4cfa37 189 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
190
191 info->u.ipi = ipi;
3d4cfa37
IC
192
193 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
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194}
195
3d4cfa37
IC
196static void xen_irq_info_virq_init(unsigned cpu,
197 unsigned irq,
9158c358
IC
198 unsigned short evtchn,
199 unsigned short virq)
ced40d0f 200{
9158c358
IC
201 struct irq_info *info = info_for_irq(irq);
202
3d4cfa37 203 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
204
205 info->u.virq = virq;
3d4cfa37
IC
206
207 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
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208}
209
9158c358
IC
210static void xen_irq_info_pirq_init(unsigned irq,
211 unsigned short evtchn,
212 unsigned short pirq,
213 unsigned short gsi,
214 unsigned short vector,
beafbdc1 215 uint16_t domid,
9158c358 216 unsigned char flags)
ced40d0f 217{
9158c358
IC
218 struct irq_info *info = info_for_irq(irq);
219
3d4cfa37 220 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
221
222 info->u.pirq.pirq = pirq;
223 info->u.pirq.gsi = gsi;
224 info->u.pirq.vector = vector;
beafbdc1 225 info->u.pirq.domid = domid;
9158c358 226 info->u.pirq.flags = flags;
e46cdb66
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227}
228
229/*
230 * Accessors for packed IRQ information.
231 */
ced40d0f 232static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 233{
110e7c7e
JJ
234 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
235 return 0;
236
ced40d0f 237 return info_for_irq(irq)->evtchn;
e46cdb66
JF
238}
239
d4c04536
IC
240unsigned irq_from_evtchn(unsigned int evtchn)
241{
242 return evtchn_to_irq[evtchn];
243}
244EXPORT_SYMBOL_GPL(irq_from_evtchn);
245
ced40d0f 246static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 247{
ced40d0f
JF
248 struct irq_info *info = info_for_irq(irq);
249
250 BUG_ON(info == NULL);
251 BUG_ON(info->type != IRQT_IPI);
252
253 return info->u.ipi;
254}
255
256static unsigned virq_from_irq(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info == NULL);
261 BUG_ON(info->type != IRQT_VIRQ);
262
263 return info->u.virq;
264}
265
7a043f11
SS
266static unsigned pirq_from_irq(unsigned irq)
267{
268 struct irq_info *info = info_for_irq(irq);
269
270 BUG_ON(info == NULL);
271 BUG_ON(info->type != IRQT_PIRQ);
272
273 return info->u.pirq.pirq;
274}
275
ced40d0f
JF
276static enum xen_irq_type type_from_irq(unsigned irq)
277{
278 return info_for_irq(irq)->type;
279}
280
281static unsigned cpu_from_irq(unsigned irq)
282{
283 return info_for_irq(irq)->cpu;
284}
285
286static unsigned int cpu_from_evtchn(unsigned int evtchn)
287{
288 int irq = evtchn_to_irq[evtchn];
289 unsigned ret = 0;
290
291 if (irq != -1)
292 ret = cpu_from_irq(irq);
293
294 return ret;
e46cdb66
JF
295}
296
bf86ad80 297#ifdef CONFIG_X86
9846ff10 298static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 299{
521394e4 300 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 301}
bf86ad80 302#endif
d46a78b0 303
9846ff10
SS
304static bool pirq_needs_eoi_flag(unsigned irq)
305{
306 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
307 BUG_ON(info->type != IRQT_PIRQ);
308
309 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
310}
311
c81611c4
IC
312static inline xen_ulong_t active_evtchns(unsigned int cpu,
313 struct shared_info *sh,
314 unsigned int idx)
e46cdb66 315{
088c05a8 316 return sh->evtchn_pending[idx] &
cb60d114 317 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 318 ~sh->evtchn_mask[idx];
e46cdb66
JF
319}
320
321static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
322{
323 int irq = evtchn_to_irq[chn];
324
325 BUG_ON(irq == -1);
326#ifdef CONFIG_SMP
c9e265e0 327 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
328#endif
329
c81611c4
IC
330 clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
331 set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
e46cdb66 332
ca62ce8c 333 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
334}
335
336static void init_evtchn_cpu_bindings(void)
337{
1c6969ec 338 int i;
e46cdb66 339#ifdef CONFIG_SMP
6cb6537d 340 struct irq_info *info;
10e58084 341
e46cdb66 342 /* By default all event channels notify CPU#0. */
6cb6537d
IC
343 list_for_each_entry(info, &xen_irq_list_head, list) {
344 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 345 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 346 }
e46cdb66
JF
347#endif
348
1c6969ec 349 for_each_possible_cpu(i)
cb60d114
IC
350 memset(per_cpu(cpu_evtchn_mask, i),
351 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
352}
353
e46cdb66
JF
354static inline void clear_evtchn(int port)
355{
356 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 357 sync_clear_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
358}
359
360static inline void set_evtchn(int port)
361{
362 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 363 sync_set_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
364}
365
168d2f46
JF
366static inline int test_evtchn(int port)
367{
368 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 369 return sync_test_bit(port, BM(&s->evtchn_pending[0]));
168d2f46
JF
370}
371
e46cdb66
JF
372
373/**
374 * notify_remote_via_irq - send event to remote end of event channel via irq
375 * @irq: irq of event channel to send event to
376 *
377 * Unlike notify_remote_via_evtchn(), this is safe to use across
378 * save/restore. Notifications on a broken connection are silently
379 * dropped.
380 */
381void notify_remote_via_irq(int irq)
382{
383 int evtchn = evtchn_from_irq(irq);
384
385 if (VALID_EVTCHN(evtchn))
386 notify_remote_via_evtchn(evtchn);
387}
388EXPORT_SYMBOL_GPL(notify_remote_via_irq);
389
390static void mask_evtchn(int port)
391{
392 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 393 sync_set_bit(port, BM(&s->evtchn_mask[0]));
e46cdb66
JF
394}
395
396static void unmask_evtchn(int port)
397{
398 struct shared_info *s = HYPERVISOR_shared_info;
399 unsigned int cpu = get_cpu();
b5e57923 400 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
JF
401
402 BUG_ON(!irqs_disabled());
403
b5e57923
SS
404 if (unlikely((cpu != cpu_from_evtchn(port))))
405 do_hypercall = 1;
406 else
c81611c4 407 evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
b5e57923
SS
408
409 if (unlikely(evtchn_pending && xen_hvm_domain()))
410 do_hypercall = 1;
411
412 /* Slow path (hypercall) if this is a non-local port or if this is
413 * an hvm domain and an event is pending (hvm domains don't have
414 * their own implementation of irq_enable). */
415 if (do_hypercall) {
e46cdb66
JF
416 struct evtchn_unmask unmask = { .port = port };
417 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
418 } else {
780f36d8 419 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66 420
c81611c4 421 sync_clear_bit(port, BM(&s->evtchn_mask[0]));
e46cdb66
JF
422
423 /*
424 * The following is basically the equivalent of
425 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
426 * the interrupt edge' if the channel is masked.
427 */
b5e57923 428 if (evtchn_pending &&
c81611c4
IC
429 !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
430 BM(&vcpu_info->evtchn_pending_sel)))
e46cdb66
JF
431 vcpu_info->evtchn_upcall_pending = 1;
432 }
433
434 put_cpu();
435}
436
6cb6537d
IC
437static void xen_irq_init(unsigned irq)
438{
439 struct irq_info *info;
b5328cd1 440#ifdef CONFIG_SMP
6cb6537d
IC
441 struct irq_desc *desc = irq_to_desc(irq);
442
443 /* By default all event channels notify CPU#0. */
444 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 445#endif
6cb6537d 446
ca62ce8c
IC
447 info = kzalloc(sizeof(*info), GFP_KERNEL);
448 if (info == NULL)
449 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
450
451 info->type = IRQT_UNBOUND;
420eb554 452 info->refcnt = -1;
6cb6537d 453
c442b806 454 irq_set_handler_data(irq, info);
ca62ce8c 455
6cb6537d
IC
456 list_add_tail(&info->list, &xen_irq_list_head);
457}
458
7bee9768 459static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 460{
89911501
IC
461 int first = 0;
462 int irq;
0794bfc7
KRW
463
464#ifdef CONFIG_X86_IO_APIC
89911501
IC
465 /*
466 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 467 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
468 * e.g. those corresponding to event channels or MSIs
469 * etc. from the range above those "real" GSIs to avoid
470 * collisions.
471 */
472 if (xen_initial_domain() || xen_hvm_domain())
473 first = get_nr_irqs_gsi();
0794bfc7
KRW
474#endif
475
89911501 476 irq = irq_alloc_desc_from(first, -1);
3a69e916 477
e6599225
KRW
478 if (irq >= 0)
479 xen_irq_init(irq);
ced40d0f 480
e46cdb66 481 return irq;
d46a78b0
JF
482}
483
7bee9768 484static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
485{
486 int irq;
487
89911501
IC
488 /*
489 * A PV guest has no concept of a GSI (since it has no ACPI
490 * nor access to/knowledge of the physical APICs). Therefore
491 * all IRQs are dynamically allocated from the entire IRQ
492 * space.
493 */
494 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
495 return xen_allocate_irq_dynamic();
496
497 /* Legacy IRQ descriptors are already allocated by the arch. */
498 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
499 irq = gsi;
500 else
501 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 502
6cb6537d 503 xen_irq_init(irq);
c9df1ce5
IC
504
505 return irq;
506}
507
508static void xen_free_irq(unsigned irq)
509{
c442b806 510 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
511
512 list_del(&info->list);
9158c358 513
c442b806 514 irq_set_handler_data(irq, NULL);
ca62ce8c 515
420eb554
DDG
516 WARN_ON(info->refcnt > 0);
517
ca62ce8c
IC
518 kfree(info);
519
72146104
IC
520 /* Legacy IRQ descriptors are managed by the arch. */
521 if (irq < NR_IRQS_LEGACY)
522 return;
523
c9df1ce5
IC
524 irq_free_desc(irq);
525}
526
d46a78b0
JF
527static void pirq_query_unmask(int irq)
528{
529 struct physdev_irq_status_query irq_status;
530 struct irq_info *info = info_for_irq(irq);
531
532 BUG_ON(info->type != IRQT_PIRQ);
533
7a043f11 534 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
535 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
536 irq_status.flags = 0;
537
538 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
539 if (irq_status.flags & XENIRQSTAT_needs_eoi)
540 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
541}
542
543static bool probing_irq(int irq)
544{
545 struct irq_desc *desc = irq_to_desc(irq);
546
547 return desc && desc->action == NULL;
548}
549
7e186bdd
SS
550static void eoi_pirq(struct irq_data *data)
551{
552 int evtchn = evtchn_from_irq(data->irq);
553 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
554 int rc = 0;
555
556 irq_move_irq(data);
557
558 if (VALID_EVTCHN(evtchn))
559 clear_evtchn(evtchn);
560
561 if (pirq_needs_eoi(data->irq)) {
562 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
563 WARN_ON(rc);
564 }
565}
566
567static void mask_ack_pirq(struct irq_data *data)
568{
569 disable_dynirq(data);
570 eoi_pirq(data);
571}
572
c9e265e0 573static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
574{
575 struct evtchn_bind_pirq bind_pirq;
576 struct irq_info *info = info_for_irq(irq);
577 int evtchn = evtchn_from_irq(irq);
15ebbb82 578 int rc;
d46a78b0
JF
579
580 BUG_ON(info->type != IRQT_PIRQ);
581
582 if (VALID_EVTCHN(evtchn))
583 goto out;
584
7a043f11 585 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 586 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
587 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
588 BIND_PIRQ__WILL_SHARE : 0;
589 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
590 if (rc != 0) {
d46a78b0
JF
591 if (!probing_irq(irq))
592 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
593 irq);
594 return 0;
595 }
596 evtchn = bind_pirq.port;
597
598 pirq_query_unmask(irq);
599
600 evtchn_to_irq[evtchn] = irq;
601 bind_evtchn_to_cpu(evtchn, 0);
602 info->evtchn = evtchn;
603
604out:
605 unmask_evtchn(evtchn);
7e186bdd 606 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
607
608 return 0;
609}
610
c9e265e0
TG
611static unsigned int startup_pirq(struct irq_data *data)
612{
613 return __startup_pirq(data->irq);
614}
615
616static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
617{
618 struct evtchn_close close;
c9e265e0 619 unsigned int irq = data->irq;
d46a78b0
JF
620 struct irq_info *info = info_for_irq(irq);
621 int evtchn = evtchn_from_irq(irq);
622
623 BUG_ON(info->type != IRQT_PIRQ);
624
625 if (!VALID_EVTCHN(evtchn))
626 return;
627
628 mask_evtchn(evtchn);
629
630 close.port = evtchn;
631 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
632 BUG();
633
634 bind_evtchn_to_cpu(evtchn, 0);
635 evtchn_to_irq[evtchn] = -1;
636 info->evtchn = 0;
637}
638
c9e265e0 639static void enable_pirq(struct irq_data *data)
d46a78b0 640{
c9e265e0 641 startup_pirq(data);
d46a78b0
JF
642}
643
c9e265e0 644static void disable_pirq(struct irq_data *data)
d46a78b0 645{
7e186bdd 646 disable_dynirq(data);
d46a78b0
JF
647}
648
68c2c39a 649int xen_irq_from_gsi(unsigned gsi)
d46a78b0 650{
6cb6537d 651 struct irq_info *info;
d46a78b0 652
6cb6537d
IC
653 list_for_each_entry(info, &xen_irq_list_head, list) {
654 if (info->type != IRQT_PIRQ)
d46a78b0
JF
655 continue;
656
6cb6537d
IC
657 if (info->u.pirq.gsi == gsi)
658 return info->irq;
d46a78b0
JF
659 }
660
661 return -1;
662}
68c2c39a 663EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 664
653378ac
IC
665/*
666 * Do not make any assumptions regarding the relationship between the
667 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
668 *
669 * Note: We don't assign an event channel until the irq actually started
670 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
671 *
672 * Shareable implies level triggered, not shareable implies edge
673 * triggered here.
d46a78b0 674 */
f4d0635b
IC
675int xen_bind_pirq_gsi_to_irq(unsigned gsi,
676 unsigned pirq, int shareable, char *name)
d46a78b0 677{
a0e18116 678 int irq = -1;
d46a78b0
JF
679 struct physdev_irq irq_op;
680
77365948 681 mutex_lock(&irq_mapping_update_lock);
d46a78b0 682
68c2c39a 683 irq = xen_irq_from_gsi(gsi);
d46a78b0 684 if (irq != -1) {
7a043f11 685 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 686 irq, gsi);
420eb554 687 goto out;
d46a78b0
JF
688 }
689
c9df1ce5 690 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
691 if (irq < 0)
692 goto out;
d46a78b0 693
d46a78b0 694 irq_op.irq = irq;
b5401a96
AN
695 irq_op.vector = 0;
696
697 /* Only the privileged domain can do this. For non-priv, the pcifront
698 * driver provides a PCI bus that does the call to do exactly
699 * this in the priv domain. */
700 if (xen_initial_domain() &&
701 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 702 xen_free_irq(irq);
d46a78b0
JF
703 irq = -ENOSPC;
704 goto out;
705 }
706
beafbdc1 707 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 708 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 709
7e186bdd
SS
710 pirq_query_unmask(irq);
711 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
712 * type of interrupt: if the interrupt is an edge triggered
713 * interrupt we use handle_edge_irq.
7e186bdd 714 *
e5ac0bda
SS
715 * On the other hand if the interrupt is level triggered we use
716 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 717 * interrupts.
e5ac0bda 718 *
7e186bdd
SS
719 * Depending on the Xen version, pirq_needs_eoi might return true
720 * not only for level triggered interrupts but for edge triggered
721 * interrupts too. In any case Xen always honors the eoi mechanism,
722 * not injecting any more pirqs of the same kind if the first one
723 * hasn't received an eoi yet. Therefore using the fasteoi handler
724 * is the right choice either way.
725 */
e5ac0bda 726 if (shareable)
7e186bdd
SS
727 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
728 handle_fasteoi_irq, name);
729 else
730 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
731 handle_edge_irq, name);
732
d46a78b0 733out:
77365948 734 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
735
736 return irq;
737}
738
f731e3ef 739#ifdef CONFIG_PCI_MSI
bf480d95 740int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 741{
5cad61a6 742 int rc;
cbf6aa89 743 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 744
bf480d95 745 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 746 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 747
5cad61a6
IC
748 WARN_ONCE(rc == -ENOSYS,
749 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
750
751 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
752}
753
bf480d95 754int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
755 int pirq, int vector, const char *name,
756 domid_t domid)
809f9267 757{
bf480d95 758 int irq, ret;
4b41df7f 759
77365948 760 mutex_lock(&irq_mapping_update_lock);
809f9267 761
4b41df7f 762 irq = xen_allocate_irq_dynamic();
e6599225 763 if (irq < 0)
bb5d079a 764 goto out;
809f9267 765
7e186bdd
SS
766 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
767 name);
809f9267 768
beafbdc1 769 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 770 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
771 if (ret < 0)
772 goto error_irq;
809f9267 773out:
77365948 774 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 775 return irq;
bf480d95 776error_irq:
77365948 777 mutex_unlock(&irq_mapping_update_lock);
bf480d95 778 xen_free_irq(irq);
e6599225 779 return ret;
809f9267 780}
f731e3ef
QH
781#endif
782
b5401a96
AN
783int xen_destroy_irq(int irq)
784{
785 struct irq_desc *desc;
38aa66fc
JF
786 struct physdev_unmap_pirq unmap_irq;
787 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
788 int rc = -ENOENT;
789
77365948 790 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
791
792 desc = irq_to_desc(irq);
793 if (!desc)
794 goto out;
795
38aa66fc 796 if (xen_initial_domain()) {
12334715 797 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 798 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 799 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
800 /* If another domain quits without making the pci_disable_msix
801 * call, the Xen hypervisor takes care of freeing the PIRQs
802 * (free_domain_pirqs).
803 */
804 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
805 printk(KERN_INFO "domain %d does not have %d anymore\n",
806 info->u.pirq.domid, info->u.pirq.pirq);
807 else if (rc) {
38aa66fc
JF
808 printk(KERN_WARNING "unmap irq failed %d\n", rc);
809 goto out;
810 }
811 }
b5401a96 812
c9df1ce5 813 xen_free_irq(irq);
b5401a96
AN
814
815out:
77365948 816 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
817 return rc;
818}
819
af42b8d1 820int xen_irq_from_pirq(unsigned pirq)
d46a78b0 821{
69c358ce 822 int irq;
d46a78b0 823
69c358ce 824 struct irq_info *info;
e46cdb66 825
77365948 826 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
827
828 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 829 if (info->type != IRQT_PIRQ)
69c358ce
IC
830 continue;
831 irq = info->irq;
832 if (info->u.pirq.pirq == pirq)
833 goto out;
834 }
835 irq = -1;
836out:
77365948 837 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
838
839 return irq;
af42b8d1
SS
840}
841
e6197acc
KRW
842
843int xen_pirq_from_irq(unsigned irq)
844{
845 return pirq_from_irq(irq);
846}
847EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 848int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
849{
850 int irq;
851
77365948 852 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
853
854 irq = evtchn_to_irq[evtchn];
855
856 if (irq == -1) {
c9df1ce5 857 irq = xen_allocate_irq_dynamic();
68ba45ff 858 if (irq < 0)
7bee9768 859 goto out;
e46cdb66 860
c442b806 861 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 862 handle_edge_irq, "event");
e46cdb66 863
9158c358 864 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
865 } else {
866 struct irq_info *info = info_for_irq(irq);
867 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66 868 }
a8636c0b 869 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
e46cdb66 870
7bee9768 871out:
77365948 872 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
873
874 return irq;
875}
b536b4b9 876EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 877
f87e4cac
JF
878static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
879{
880 struct evtchn_bind_ipi bind_ipi;
881 int evtchn, irq;
882
77365948 883 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
884
885 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 886
f87e4cac 887 if (irq == -1) {
c9df1ce5 888 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
889 if (irq < 0)
890 goto out;
891
c442b806 892 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 893 handle_percpu_irq, "ipi");
f87e4cac
JF
894
895 bind_ipi.vcpu = cpu;
896 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
897 &bind_ipi) != 0)
898 BUG();
899 evtchn = bind_ipi.port;
900
3d4cfa37 901 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
902
903 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
904 } else {
905 struct irq_info *info = info_for_irq(irq);
906 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
907 }
908
f87e4cac 909 out:
77365948 910 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
911 return irq;
912}
913
2e820f58
IC
914static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
915 unsigned int remote_port)
916{
917 struct evtchn_bind_interdomain bind_interdomain;
918 int err;
919
920 bind_interdomain.remote_dom = remote_domain;
921 bind_interdomain.remote_port = remote_port;
922
923 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
924 &bind_interdomain);
925
926 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
927}
928
62cc5fc7
OH
929static int find_virq(unsigned int virq, unsigned int cpu)
930{
931 struct evtchn_status status;
932 int port, rc = -ENOENT;
933
934 memset(&status, 0, sizeof(status));
935 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
936 status.dom = DOMID_SELF;
937 status.port = port;
938 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
939 if (rc < 0)
940 continue;
941 if (status.status != EVTCHNSTAT_virq)
942 continue;
943 if (status.u.virq == virq && status.vcpu == cpu) {
944 rc = port;
945 break;
946 }
947 }
948 return rc;
949}
f87e4cac 950
4fe7d5a7 951int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
952{
953 struct evtchn_bind_virq bind_virq;
62cc5fc7 954 int evtchn, irq, ret;
e46cdb66 955
77365948 956 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
957
958 irq = per_cpu(virq_to_irq, cpu)[virq];
959
960 if (irq == -1) {
c9df1ce5 961 irq = xen_allocate_irq_dynamic();
68ba45ff 962 if (irq < 0)
7bee9768 963 goto out;
a52521f1 964
c442b806 965 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
966 handle_percpu_irq, "virq");
967
e46cdb66
JF
968 bind_virq.virq = virq;
969 bind_virq.vcpu = cpu;
62cc5fc7
OH
970 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
971 &bind_virq);
972 if (ret == 0)
973 evtchn = bind_virq.port;
974 else {
975 if (ret == -EEXIST)
976 ret = find_virq(virq, cpu);
977 BUG_ON(ret < 0);
978 evtchn = ret;
979 }
e46cdb66 980
3d4cfa37 981 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
982
983 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
984 } else {
985 struct irq_info *info = info_for_irq(irq);
986 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
987 }
988
7bee9768 989out:
77365948 990 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
991
992 return irq;
993}
994
995static void unbind_from_irq(unsigned int irq)
996{
997 struct evtchn_close close;
998 int evtchn = evtchn_from_irq(irq);
420eb554 999 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 1000
77365948 1001 mutex_lock(&irq_mapping_update_lock);
e46cdb66 1002
420eb554
DDG
1003 if (info->refcnt > 0) {
1004 info->refcnt--;
1005 if (info->refcnt != 0)
1006 goto done;
1007 }
1008
d77bbd4d 1009 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
1010 close.port = evtchn;
1011 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
1012 BUG();
1013
1014 switch (type_from_irq(irq)) {
1015 case IRQT_VIRQ:
1016 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1017 [virq_from_irq(irq)] = -1;
e46cdb66 1018 break;
d68d82af
AN
1019 case IRQT_IPI:
1020 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1021 [ipi_from_irq(irq)] = -1;
d68d82af 1022 break;
e46cdb66
JF
1023 default:
1024 break;
1025 }
1026
1027 /* Closed ports are implicitly re-bound to VCPU0. */
1028 bind_evtchn_to_cpu(evtchn, 0);
1029
1030 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1031 }
1032
ca62ce8c 1033 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1034
9158c358 1035 xen_free_irq(irq);
e46cdb66 1036
420eb554 1037 done:
77365948 1038 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1039}
1040
1041int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1042 irq_handler_t handler,
e46cdb66
JF
1043 unsigned long irqflags,
1044 const char *devname, void *dev_id)
1045{
361ae8cb 1046 int irq, retval;
e46cdb66
JF
1047
1048 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1049 if (irq < 0)
1050 return irq;
e46cdb66
JF
1051 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1052 if (retval != 0) {
1053 unbind_from_irq(irq);
1054 return retval;
1055 }
1056
1057 return irq;
1058}
1059EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1060
2e820f58
IC
1061int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1062 unsigned int remote_port,
1063 irq_handler_t handler,
1064 unsigned long irqflags,
1065 const char *devname,
1066 void *dev_id)
1067{
1068 int irq, retval;
1069
1070 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1071 if (irq < 0)
1072 return irq;
1073
1074 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1075 if (retval != 0) {
1076 unbind_from_irq(irq);
1077 return retval;
1078 }
1079
1080 return irq;
1081}
1082EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1083
e46cdb66 1084int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1085 irq_handler_t handler,
e46cdb66
JF
1086 unsigned long irqflags, const char *devname, void *dev_id)
1087{
361ae8cb 1088 int irq, retval;
e46cdb66
JF
1089
1090 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1091 if (irq < 0)
1092 return irq;
e46cdb66
JF
1093 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1094 if (retval != 0) {
1095 unbind_from_irq(irq);
1096 return retval;
1097 }
1098
1099 return irq;
1100}
1101EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1102
f87e4cac
JF
1103int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1104 unsigned int cpu,
1105 irq_handler_t handler,
1106 unsigned long irqflags,
1107 const char *devname,
1108 void *dev_id)
1109{
1110 int irq, retval;
1111
1112 irq = bind_ipi_to_irq(ipi, cpu);
1113 if (irq < 0)
1114 return irq;
1115
9bab0b7f 1116 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1117 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1118 if (retval != 0) {
1119 unbind_from_irq(irq);
1120 return retval;
1121 }
1122
1123 return irq;
1124}
1125
e46cdb66
JF
1126void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1127{
1128 free_irq(irq, dev_id);
1129 unbind_from_irq(irq);
1130}
1131EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1132
420eb554
DDG
1133int evtchn_make_refcounted(unsigned int evtchn)
1134{
1135 int irq = evtchn_to_irq[evtchn];
1136 struct irq_info *info;
1137
1138 if (irq == -1)
1139 return -ENOENT;
1140
1141 info = irq_get_handler_data(irq);
1142
1143 if (!info)
1144 return -ENOENT;
1145
1146 WARN_ON(info->refcnt != -1);
1147
1148 info->refcnt = 1;
1149
1150 return 0;
1151}
1152EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1153
1154int evtchn_get(unsigned int evtchn)
1155{
1156 int irq;
1157 struct irq_info *info;
1158 int err = -ENOENT;
1159
c3b3f16d
DDG
1160 if (evtchn >= NR_EVENT_CHANNELS)
1161 return -EINVAL;
1162
420eb554
DDG
1163 mutex_lock(&irq_mapping_update_lock);
1164
1165 irq = evtchn_to_irq[evtchn];
1166 if (irq == -1)
1167 goto done;
1168
1169 info = irq_get_handler_data(irq);
1170
1171 if (!info)
1172 goto done;
1173
1174 err = -EINVAL;
1175 if (info->refcnt <= 0)
1176 goto done;
1177
1178 info->refcnt++;
1179 err = 0;
1180 done:
1181 mutex_unlock(&irq_mapping_update_lock);
1182
1183 return err;
1184}
1185EXPORT_SYMBOL_GPL(evtchn_get);
1186
1187void evtchn_put(unsigned int evtchn)
1188{
1189 int irq = evtchn_to_irq[evtchn];
1190 if (WARN_ON(irq == -1))
1191 return;
1192 unbind_from_irq(irq);
1193}
1194EXPORT_SYMBOL_GPL(evtchn_put);
1195
f87e4cac
JF
1196void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1197{
1198 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1199 BUG_ON(irq < 0);
1200 notify_remote_via_irq(irq);
1201}
1202
ee523ca1
JF
1203irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1204{
1205 struct shared_info *sh = HYPERVISOR_shared_info;
1206 int cpu = smp_processor_id();
c81611c4 1207 xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1208 int i;
1209 unsigned long flags;
1210 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1211 struct vcpu_info *v;
ee523ca1
JF
1212
1213 spin_lock_irqsave(&debug_lock, flags);
1214
cb52e6d9 1215 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1216
1217 for_each_online_cpu(i) {
cb52e6d9
IC
1218 int pending;
1219 v = per_cpu(xen_vcpu, i);
1220 pending = (get_irq_regs() && i == cpu)
1221 ? xen_irqs_disabled(get_irq_regs())
1222 : v->evtchn_upcall_mask;
c81611c4 1223 printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
cb52e6d9
IC
1224 pending, v->evtchn_upcall_pending,
1225 (int)(sizeof(v->evtchn_pending_sel)*2),
1226 v->evtchn_pending_sel);
1227 }
1228 v = per_cpu(xen_vcpu, cpu);
1229
1230 printk("\npending:\n ");
1231 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
c81611c4
IC
1232 printk("%0*"PRI_xen_ulong"%s",
1233 (int)sizeof(sh->evtchn_pending[0])*2,
cb52e6d9
IC
1234 sh->evtchn_pending[i],
1235 i % 8 == 0 ? "\n " : " ");
1236 printk("\nglobal mask:\n ");
1237 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4 1238 printk("%0*"PRI_xen_ulong"%s",
cb52e6d9
IC
1239 (int)(sizeof(sh->evtchn_mask[0])*2),
1240 sh->evtchn_mask[i],
1241 i % 8 == 0 ? "\n " : " ");
1242
1243 printk("\nglobally unmasked:\n ");
1244 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4
IC
1245 printk("%0*"PRI_xen_ulong"%s",
1246 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9
IC
1247 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1248 i % 8 == 0 ? "\n " : " ");
1249
1250 printk("\nlocal cpu%d mask:\n ", cpu);
c81611c4
IC
1251 for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
1252 printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
cb52e6d9
IC
1253 cpu_evtchn[i],
1254 i % 8 == 0 ? "\n " : " ");
1255
1256 printk("\nlocally unmasked:\n ");
1257 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
c81611c4 1258 xen_ulong_t pending = sh->evtchn_pending[i]
cb52e6d9
IC
1259 & ~sh->evtchn_mask[i]
1260 & cpu_evtchn[i];
c81611c4
IC
1261 printk("%0*"PRI_xen_ulong"%s",
1262 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9 1263 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1264 }
ee523ca1
JF
1265
1266 printk("\npending list:\n");
cb52e6d9 1267 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
c81611c4
IC
1268 if (sync_test_bit(i, BM(sh->evtchn_pending))) {
1269 int word_idx = i / BITS_PER_EVTCHN_WORD;
cb52e6d9 1270 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1271 cpu_from_evtchn(i), i,
cb52e6d9 1272 evtchn_to_irq[i],
c81611c4 1273 sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
cb52e6d9 1274 ? "" : " l2-clear",
c81611c4 1275 !sync_test_bit(i, BM(sh->evtchn_mask))
cb52e6d9 1276 ? "" : " globally-masked",
c81611c4 1277 sync_test_bit(i, BM(cpu_evtchn))
cb52e6d9 1278 ? "" : " locally-masked");
ee523ca1
JF
1279 }
1280 }
1281
1282 spin_unlock_irqrestore(&debug_lock, flags);
1283
1284 return IRQ_HANDLED;
1285}
1286
245b2e70 1287static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1288static DEFINE_PER_CPU(unsigned int, current_word_idx);
1289static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1290
ab7f863e
SR
1291/*
1292 * Mask out the i least significant bits of w
1293 */
c81611c4 1294#define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
245b2e70 1295
e46cdb66
JF
1296/*
1297 * Search the CPUs pending events bitmasks. For each one found, map
1298 * the event number to an irq, and feed it into do_IRQ() for
1299 * handling.
1300 *
1301 * Xen uses a two-level bitmap to speed searching. The first level is
1302 * a bitset of words which contain pending event bits. The second
1303 * level is a bitset of pending events themselves.
1304 */
38e20b07 1305static void __xen_evtchn_do_upcall(void)
e46cdb66 1306{
24b51c2f 1307 int start_word_idx, start_bit_idx;
ab7f863e 1308 int word_idx, bit_idx;
24b51c2f 1309 int i;
e46cdb66
JF
1310 int cpu = get_cpu();
1311 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1312 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1313 unsigned count;
e46cdb66 1314
229664be 1315 do {
c81611c4 1316 xen_ulong_t pending_words;
e46cdb66 1317
229664be 1318 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1319
b2e4ae69 1320 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1321 goto out;
e46cdb66 1322
c81611c4
IC
1323 /*
1324 * Master flag must be cleared /before/ clearing
1325 * selector flag. xchg_xen_ulong must contain an
1326 * appropriate barrier.
1327 */
1328 pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1329
24b51c2f
KF
1330 start_word_idx = __this_cpu_read(current_word_idx);
1331 start_bit_idx = __this_cpu_read(current_bit_idx);
1332
1333 word_idx = start_word_idx;
ab7f863e 1334
24b51c2f 1335 for (i = 0; pending_words != 0; i++) {
c81611c4
IC
1336 xen_ulong_t pending_bits;
1337 xen_ulong_t words;
229664be 1338
ab7f863e
SR
1339 words = MASK_LSBS(pending_words, word_idx);
1340
1341 /*
ada6814c 1342 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1343 */
1344 if (words == 0) {
ada6814c
KF
1345 word_idx = 0;
1346 bit_idx = 0;
ab7f863e
SR
1347 continue;
1348 }
c81611c4 1349 word_idx = EVTCHN_FIRST_BIT(words);
229664be 1350
24b51c2f
KF
1351 pending_bits = active_evtchns(cpu, s, word_idx);
1352 bit_idx = 0; /* usually scan entire word from start */
1353 if (word_idx == start_word_idx) {
1354 /* We scan the starting word in two parts */
1355 if (i == 0)
1356 /* 1st time: start in the middle */
1357 bit_idx = start_bit_idx;
1358 else
1359 /* 2nd time: mask bits done already */
1360 bit_idx &= (1UL << start_bit_idx) - 1;
1361 }
1362
ab7f863e 1363 do {
c81611c4 1364 xen_ulong_t bits;
ab7f863e 1365 int port, irq;
ca4dbc66 1366 struct irq_desc *desc;
229664be 1367
ab7f863e
SR
1368 bits = MASK_LSBS(pending_bits, bit_idx);
1369
1370 /* If we masked out all events, move on. */
ada6814c 1371 if (bits == 0)
ab7f863e 1372 break;
ab7f863e 1373
c81611c4 1374 bit_idx = EVTCHN_FIRST_BIT(bits);
ab7f863e
SR
1375
1376 /* Process port. */
c81611c4 1377 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
ab7f863e
SR
1378 irq = evtchn_to_irq[port];
1379
ca4dbc66
EB
1380 if (irq != -1) {
1381 desc = irq_to_desc(irq);
1382 if (desc)
1383 generic_handle_irq_desc(irq, desc);
1384 }
ab7f863e 1385
c81611c4 1386 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
ada6814c
KF
1387
1388 /* Next caller starts at last processed + 1 */
1389 __this_cpu_write(current_word_idx,
1390 bit_idx ? word_idx :
c81611c4 1391 (word_idx+1) % BITS_PER_EVTCHN_WORD);
ada6814c
KF
1392 __this_cpu_write(current_bit_idx, bit_idx);
1393 } while (bit_idx != 0);
ab7f863e 1394
24b51c2f
KF
1395 /* Scan start_l1i twice; all others once. */
1396 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1397 pending_words &= ~(1UL << word_idx);
ada6814c 1398
c81611c4 1399 word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
e46cdb66 1400 }
e46cdb66 1401
229664be
JF
1402 BUG_ON(!irqs_disabled());
1403
780f36d8
CL
1404 count = __this_cpu_read(xed_nesting_count);
1405 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1406 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1407
1408out:
38e20b07
SY
1409
1410 put_cpu();
1411}
1412
1413void xen_evtchn_do_upcall(struct pt_regs *regs)
1414{
1415 struct pt_regs *old_regs = set_irq_regs(regs);
1416
772aebce 1417 irq_enter();
0ec53ecf 1418#ifdef CONFIG_X86
38e20b07 1419 exit_idle();
0ec53ecf 1420#endif
38e20b07
SY
1421
1422 __xen_evtchn_do_upcall();
1423
3445a8fd
JF
1424 irq_exit();
1425 set_irq_regs(old_regs);
38e20b07 1426}
3445a8fd 1427
38e20b07
SY
1428void xen_hvm_evtchn_do_upcall(void)
1429{
1430 __xen_evtchn_do_upcall();
e46cdb66 1431}
183d03cc 1432EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1433
eb1e305f
JF
1434/* Rebind a new event channel to an existing irq. */
1435void rebind_evtchn_irq(int evtchn, int irq)
1436{
d77bbd4d
JF
1437 struct irq_info *info = info_for_irq(irq);
1438
eb1e305f
JF
1439 /* Make sure the irq is masked, since the new event channel
1440 will also be masked. */
1441 disable_irq(irq);
1442
77365948 1443 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1444
1445 /* After resume the irq<->evtchn mappings are all cleared out */
1446 BUG_ON(evtchn_to_irq[evtchn] != -1);
1447 /* Expect irq to have been bound before,
d77bbd4d
JF
1448 so there should be a proper type */
1449 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1450
9158c358 1451 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1452
77365948 1453 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1454
1455 /* new event channels are always bound to cpu 0 */
0de26520 1456 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1457
1458 /* Unmask the event channel. */
1459 enable_irq(irq);
1460}
1461
e46cdb66 1462/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1463static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1464{
1465 struct evtchn_bind_vcpu bind_vcpu;
1466 int evtchn = evtchn_from_irq(irq);
1467
be49472f
IC
1468 if (!VALID_EVTCHN(evtchn))
1469 return -1;
1470
1471 /*
1472 * Events delivered via platform PCI interrupts are always
1473 * routed to vcpu 0 and hence cannot be rebound.
1474 */
1475 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1476 return -1;
e46cdb66
JF
1477
1478 /* Send future instances of this interrupt to other vcpu. */
1479 bind_vcpu.port = evtchn;
1480 bind_vcpu.vcpu = tcpu;
1481
1482 /*
1483 * If this fails, it usually just indicates that we're dealing with a
1484 * virq or IPI channel, which don't actually need to be rebound. Ignore
1485 * it, but don't do the xenlinux-level rebind in that case.
1486 */
1487 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1488 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1489
d5dedd45
YL
1490 return 0;
1491}
e46cdb66 1492
c9e265e0
TG
1493static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1494 bool force)
e46cdb66 1495{
0de26520 1496 unsigned tcpu = cpumask_first(dest);
d5dedd45 1497
c9e265e0 1498 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1499}
1500
642e0c88
IY
1501int resend_irq_on_evtchn(unsigned int irq)
1502{
1503 int masked, evtchn = evtchn_from_irq(irq);
1504 struct shared_info *s = HYPERVISOR_shared_info;
1505
1506 if (!VALID_EVTCHN(evtchn))
1507 return 1;
1508
c81611c4
IC
1509 masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
1510 sync_set_bit(evtchn, BM(s->evtchn_pending));
642e0c88
IY
1511 if (!masked)
1512 unmask_evtchn(evtchn);
1513
1514 return 1;
1515}
1516
c9e265e0 1517static void enable_dynirq(struct irq_data *data)
e46cdb66 1518{
c9e265e0 1519 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1520
1521 if (VALID_EVTCHN(evtchn))
1522 unmask_evtchn(evtchn);
1523}
1524
c9e265e0 1525static void disable_dynirq(struct irq_data *data)
e46cdb66 1526{
c9e265e0 1527 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1528
1529 if (VALID_EVTCHN(evtchn))
1530 mask_evtchn(evtchn);
1531}
1532
c9e265e0 1533static void ack_dynirq(struct irq_data *data)
e46cdb66 1534{
c9e265e0 1535 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1536
7e186bdd 1537 irq_move_irq(data);
e46cdb66
JF
1538
1539 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1540 clear_evtchn(evtchn);
1541}
1542
1543static void mask_ack_dynirq(struct irq_data *data)
1544{
1545 disable_dynirq(data);
1546 ack_dynirq(data);
e46cdb66
JF
1547}
1548
c9e265e0 1549static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1550{
c9e265e0 1551 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1552 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1553 int ret = 0;
1554
1555 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1556 int masked;
1557
c81611c4
IC
1558 masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
1559 sync_set_bit(evtchn, BM(sh->evtchn_pending));
ee8fa1c6
JF
1560 if (!masked)
1561 unmask_evtchn(evtchn);
e46cdb66
JF
1562 ret = 1;
1563 }
1564
1565 return ret;
1566}
1567
0a85226f 1568static void restore_pirqs(void)
9a069c33
SS
1569{
1570 int pirq, rc, irq, gsi;
1571 struct physdev_map_pirq map_irq;
69c358ce 1572 struct irq_info *info;
9a069c33 1573
69c358ce
IC
1574 list_for_each_entry(info, &xen_irq_list_head, list) {
1575 if (info->type != IRQT_PIRQ)
9a069c33
SS
1576 continue;
1577
69c358ce
IC
1578 pirq = info->u.pirq.pirq;
1579 gsi = info->u.pirq.gsi;
1580 irq = info->irq;
1581
9a069c33
SS
1582 /* save/restore of PT devices doesn't work, so at this point the
1583 * only devices present are GSI based emulated devices */
9a069c33
SS
1584 if (!gsi)
1585 continue;
1586
1587 map_irq.domid = DOMID_SELF;
1588 map_irq.type = MAP_PIRQ_TYPE_GSI;
1589 map_irq.index = gsi;
1590 map_irq.pirq = pirq;
1591
1592 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1593 if (rc) {
1594 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1595 gsi, irq, pirq, rc);
9158c358 1596 xen_free_irq(irq);
9a069c33
SS
1597 continue;
1598 }
1599
1600 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1601
c9e265e0 1602 __startup_pirq(irq);
9a069c33
SS
1603 }
1604}
1605
0e91398f
JF
1606static void restore_cpu_virqs(unsigned int cpu)
1607{
1608 struct evtchn_bind_virq bind_virq;
1609 int virq, irq, evtchn;
1610
1611 for (virq = 0; virq < NR_VIRQS; virq++) {
1612 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1613 continue;
1614
ced40d0f 1615 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1616
1617 /* Get a new binding from Xen. */
1618 bind_virq.virq = virq;
1619 bind_virq.vcpu = cpu;
1620 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1621 &bind_virq) != 0)
1622 BUG();
1623 evtchn = bind_virq.port;
1624
1625 /* Record the new mapping. */
3d4cfa37 1626 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1627 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1628 }
1629}
1630
1631static void restore_cpu_ipis(unsigned int cpu)
1632{
1633 struct evtchn_bind_ipi bind_ipi;
1634 int ipi, irq, evtchn;
1635
1636 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1637 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1638 continue;
1639
ced40d0f 1640 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1641
1642 /* Get a new binding from Xen. */
1643 bind_ipi.vcpu = cpu;
1644 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1645 &bind_ipi) != 0)
1646 BUG();
1647 evtchn = bind_ipi.port;
1648
1649 /* Record the new mapping. */
3d4cfa37 1650 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1651 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1652 }
1653}
1654
2d9e1e2f
JF
1655/* Clear an irq's pending state, in preparation for polling on it */
1656void xen_clear_irq_pending(int irq)
1657{
1658 int evtchn = evtchn_from_irq(irq);
1659
1660 if (VALID_EVTCHN(evtchn))
1661 clear_evtchn(evtchn);
1662}
d9a8814f 1663EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1664void xen_set_irq_pending(int irq)
1665{
1666 int evtchn = evtchn_from_irq(irq);
1667
1668 if (VALID_EVTCHN(evtchn))
1669 set_evtchn(evtchn);
1670}
1671
1672bool xen_test_irq_pending(int irq)
1673{
1674 int evtchn = evtchn_from_irq(irq);
1675 bool ret = false;
1676
1677 if (VALID_EVTCHN(evtchn))
1678 ret = test_evtchn(evtchn);
1679
1680 return ret;
1681}
1682
d9a8814f
KRW
1683/* Poll waiting for an irq to become pending with timeout. In the usual case,
1684 * the irq will be disabled so it won't deliver an interrupt. */
1685void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1686{
1687 evtchn_port_t evtchn = evtchn_from_irq(irq);
1688
1689 if (VALID_EVTCHN(evtchn)) {
1690 struct sched_poll poll;
1691
1692 poll.nr_ports = 1;
d9a8814f 1693 poll.timeout = timeout;
ff3c5362 1694 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1695
1696 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1697 BUG();
1698 }
1699}
d9a8814f
KRW
1700EXPORT_SYMBOL(xen_poll_irq_timeout);
1701/* Poll waiting for an irq to become pending. In the usual case, the
1702 * irq will be disabled so it won't deliver an interrupt. */
1703void xen_poll_irq(int irq)
1704{
1705 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1706}
2d9e1e2f 1707
c7c2c3a2
KRW
1708/* Check whether the IRQ line is shared with other guests. */
1709int xen_test_irq_shared(int irq)
1710{
1711 struct irq_info *info = info_for_irq(irq);
1712 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1713
1714 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1715 return 0;
1716 return !(irq_status.flags & XENIRQSTAT_shared);
1717}
1718EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1719
0e91398f
JF
1720void xen_irq_resume(void)
1721{
6cb6537d
IC
1722 unsigned int cpu, evtchn;
1723 struct irq_info *info;
0e91398f
JF
1724
1725 init_evtchn_cpu_bindings();
1726
1727 /* New event-channel space is not 'live' yet. */
1728 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1729 mask_evtchn(evtchn);
1730
1731 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1732 list_for_each_entry(info, &xen_irq_list_head, list)
1733 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1734
1735 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1736 evtchn_to_irq[evtchn] = -1;
1737
1738 for_each_possible_cpu(cpu) {
1739 restore_cpu_virqs(cpu);
1740 restore_cpu_ipis(cpu);
1741 }
6903591f 1742
0a85226f 1743 restore_pirqs();
0e91398f
JF
1744}
1745
e46cdb66 1746static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1747 .name = "xen-dyn",
54a353a0 1748
c9e265e0
TG
1749 .irq_disable = disable_dynirq,
1750 .irq_mask = disable_dynirq,
1751 .irq_unmask = enable_dynirq,
54a353a0 1752
7e186bdd
SS
1753 .irq_ack = ack_dynirq,
1754 .irq_mask_ack = mask_ack_dynirq,
1755
c9e265e0
TG
1756 .irq_set_affinity = set_affinity_irq,
1757 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1758};
1759
d46a78b0 1760static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1761 .name = "xen-pirq",
d46a78b0 1762
c9e265e0
TG
1763 .irq_startup = startup_pirq,
1764 .irq_shutdown = shutdown_pirq,
c9e265e0 1765 .irq_enable = enable_pirq,
c9e265e0 1766 .irq_disable = disable_pirq,
d46a78b0 1767
7e186bdd
SS
1768 .irq_mask = disable_dynirq,
1769 .irq_unmask = enable_dynirq,
1770
1771 .irq_ack = eoi_pirq,
1772 .irq_eoi = eoi_pirq,
1773 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1774
c9e265e0 1775 .irq_set_affinity = set_affinity_irq,
d46a78b0 1776
c9e265e0 1777 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1778};
1779
aaca4964 1780static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1781 .name = "xen-percpu",
aaca4964 1782
c9e265e0
TG
1783 .irq_disable = disable_dynirq,
1784 .irq_mask = disable_dynirq,
1785 .irq_unmask = enable_dynirq,
aaca4964 1786
c9e265e0 1787 .irq_ack = ack_dynirq,
aaca4964
JF
1788};
1789
38e20b07
SY
1790int xen_set_callback_via(uint64_t via)
1791{
1792 struct xen_hvm_param a;
1793 a.domid = DOMID_SELF;
1794 a.index = HVM_PARAM_CALLBACK_IRQ;
1795 a.value = via;
1796 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1797}
1798EXPORT_SYMBOL_GPL(xen_set_callback_via);
1799
ca65f9fc 1800#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1801/* Vector callbacks are better than PCI interrupts to receive event
1802 * channel notifications because we can receive vector callbacks on any
1803 * vcpu and we don't need PCI support or APIC interactions. */
1804void xen_callback_vector(void)
1805{
1806 int rc;
1807 uint64_t callback_via;
1808 if (xen_have_vector_callback) {
bc2b0331 1809 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1810 rc = xen_set_callback_via(callback_via);
1811 if (rc) {
1812 printk(KERN_ERR "Request for Xen HVM callback vector"
1813 " failed.\n");
1814 xen_have_vector_callback = 0;
1815 return;
1816 }
1817 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1818 "enabled\n");
1819 /* in the restore case the vector has already been allocated */
bc2b0331
S
1820 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1821 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1822 xen_hvm_callback_vector);
38e20b07
SY
1823 }
1824}
ca65f9fc
SS
1825#else
1826void xen_callback_vector(void) {}
1827#endif
38e20b07 1828
2e3d8860 1829void __init xen_init_IRQ(void)
e46cdb66 1830{
0ec53ecf 1831 int i;
c7a3589e 1832
b21ddbf5
JF
1833 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1834 GFP_KERNEL);
9d093e29 1835 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1836 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1837 evtchn_to_irq[i] = -1;
e46cdb66
JF
1838
1839 init_evtchn_cpu_bindings();
1840
1841 /* No event channels are 'live' right now. */
1842 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1843 mask_evtchn(i);
1844
9846ff10
SS
1845 pirq_needs_eoi = pirq_needs_eoi_flag;
1846
0ec53ecf 1847#ifdef CONFIG_X86
38e20b07
SY
1848 if (xen_hvm_domain()) {
1849 xen_callback_vector();
1850 native_init_IRQ();
3942b740
SS
1851 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1852 * __acpi_register_gsi can point at the right function */
1853 pci_xen_hvm_init();
38e20b07 1854 } else {
0ec53ecf 1855 int rc;
9846ff10
SS
1856 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1857
38e20b07 1858 irq_ctx_init(smp_processor_id());
38aa66fc 1859 if (xen_initial_domain())
a0ee0567 1860 pci_xen_initial_domain();
9846ff10
SS
1861
1862 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1863 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1864 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1865 if (rc != 0) {
1866 free_page((unsigned long) pirq_eoi_map);
1867 pirq_eoi_map = NULL;
1868 } else
1869 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1870 }
0ec53ecf 1871#endif
e46cdb66 1872}