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Merge tag 'v3.2-rc2' into staging/for_v3.3
[mirror_ubuntu-artful-kernel.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
77365948 57static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 58
6cb6537d
IC
59static LIST_HEAD(xen_irq_list_head);
60
e46cdb66 61/* IRQ <-> VIRQ mapping. */
204fba4a 62static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 63
f87e4cac 64/* IRQ <-> IPI mapping */
204fba4a 65static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 66
ced40d0f
JF
67/* Interrupt types. */
68enum xen_irq_type {
d77bbd4d 69 IRQT_UNBOUND = 0,
f87e4cac
JF
70 IRQT_PIRQ,
71 IRQT_VIRQ,
72 IRQT_IPI,
73 IRQT_EVTCHN
74};
e46cdb66 75
ced40d0f
JF
76/*
77 * Packed IRQ information:
78 * type - enum xen_irq_type
79 * event channel - irq->event channel mapping
80 * cpu - cpu this event channel is bound to
81 * index - type-specific information:
42a1de56
SS
82 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
83 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
84 * VIRQ - virq number
85 * IPI - IPI vector
86 * EVTCHN -
87 */
088c05a8 88struct irq_info {
6cb6537d 89 struct list_head list;
ced40d0f 90 enum xen_irq_type type; /* type */
6cb6537d 91 unsigned irq;
ced40d0f
JF
92 unsigned short evtchn; /* event channel */
93 unsigned short cpu; /* cpu bound */
94
95 union {
96 unsigned short virq;
97 enum ipi_vector ipi;
98 struct {
7a043f11 99 unsigned short pirq;
ced40d0f 100 unsigned short gsi;
d46a78b0
JF
101 unsigned char vector;
102 unsigned char flags;
beafbdc1 103 uint16_t domid;
ced40d0f
JF
104 } pirq;
105 } u;
106};
d46a78b0 107#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 108#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 109
b21ddbf5 110static int *evtchn_to_irq;
3b32f574 111
cb60d114
IC
112static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
113 cpu_evtchn_mask);
e46cdb66 114
e46cdb66
JF
115/* Xen will never allocate port zero for any purpose. */
116#define VALID_EVTCHN(chn) ((chn) != 0)
117
e46cdb66 118static struct irq_chip xen_dynamic_chip;
aaca4964 119static struct irq_chip xen_percpu_chip;
d46a78b0 120static struct irq_chip xen_pirq_chip;
7e186bdd
SS
121static void enable_dynirq(struct irq_data *data);
122static void disable_dynirq(struct irq_data *data);
e46cdb66 123
9158c358
IC
124/* Get info for IRQ */
125static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 126{
c442b806 127 return irq_get_handler_data(irq);
ced40d0f
JF
128}
129
9158c358
IC
130/* Constructors for packed IRQ information. */
131static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 132 unsigned irq,
9158c358
IC
133 enum xen_irq_type type,
134 unsigned short evtchn,
135 unsigned short cpu)
ced40d0f 136{
9158c358
IC
137
138 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
139
140 info->type = type;
6cb6537d 141 info->irq = irq;
9158c358
IC
142 info->evtchn = evtchn;
143 info->cpu = cpu;
3d4cfa37
IC
144
145 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
146}
147
9158c358
IC
148static void xen_irq_info_evtchn_init(unsigned irq,
149 unsigned short evtchn)
ced40d0f 150{
9158c358
IC
151 struct irq_info *info = info_for_irq(irq);
152
3d4cfa37 153 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
154}
155
3d4cfa37
IC
156static void xen_irq_info_ipi_init(unsigned cpu,
157 unsigned irq,
9158c358
IC
158 unsigned short evtchn,
159 enum ipi_vector ipi)
e46cdb66 160{
9158c358
IC
161 struct irq_info *info = info_for_irq(irq);
162
3d4cfa37 163 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
164
165 info->u.ipi = ipi;
3d4cfa37
IC
166
167 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
168}
169
3d4cfa37
IC
170static void xen_irq_info_virq_init(unsigned cpu,
171 unsigned irq,
9158c358
IC
172 unsigned short evtchn,
173 unsigned short virq)
ced40d0f 174{
9158c358
IC
175 struct irq_info *info = info_for_irq(irq);
176
3d4cfa37 177 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
178
179 info->u.virq = virq;
3d4cfa37
IC
180
181 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
182}
183
9158c358
IC
184static void xen_irq_info_pirq_init(unsigned irq,
185 unsigned short evtchn,
186 unsigned short pirq,
187 unsigned short gsi,
188 unsigned short vector,
beafbdc1 189 uint16_t domid,
9158c358 190 unsigned char flags)
ced40d0f 191{
9158c358
IC
192 struct irq_info *info = info_for_irq(irq);
193
3d4cfa37 194 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
195
196 info->u.pirq.pirq = pirq;
197 info->u.pirq.gsi = gsi;
198 info->u.pirq.vector = vector;
beafbdc1 199 info->u.pirq.domid = domid;
9158c358 200 info->u.pirq.flags = flags;
e46cdb66
JF
201}
202
203/*
204 * Accessors for packed IRQ information.
205 */
ced40d0f 206static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 207{
110e7c7e
JJ
208 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
209 return 0;
210
ced40d0f 211 return info_for_irq(irq)->evtchn;
e46cdb66
JF
212}
213
d4c04536
IC
214unsigned irq_from_evtchn(unsigned int evtchn)
215{
216 return evtchn_to_irq[evtchn];
217}
218EXPORT_SYMBOL_GPL(irq_from_evtchn);
219
ced40d0f 220static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 221{
ced40d0f
JF
222 struct irq_info *info = info_for_irq(irq);
223
224 BUG_ON(info == NULL);
225 BUG_ON(info->type != IRQT_IPI);
226
227 return info->u.ipi;
228}
229
230static unsigned virq_from_irq(unsigned irq)
231{
232 struct irq_info *info = info_for_irq(irq);
233
234 BUG_ON(info == NULL);
235 BUG_ON(info->type != IRQT_VIRQ);
236
237 return info->u.virq;
238}
239
7a043f11
SS
240static unsigned pirq_from_irq(unsigned irq)
241{
242 struct irq_info *info = info_for_irq(irq);
243
244 BUG_ON(info == NULL);
245 BUG_ON(info->type != IRQT_PIRQ);
246
247 return info->u.pirq.pirq;
248}
249
ced40d0f
JF
250static enum xen_irq_type type_from_irq(unsigned irq)
251{
252 return info_for_irq(irq)->type;
253}
254
255static unsigned cpu_from_irq(unsigned irq)
256{
257 return info_for_irq(irq)->cpu;
258}
259
260static unsigned int cpu_from_evtchn(unsigned int evtchn)
261{
262 int irq = evtchn_to_irq[evtchn];
263 unsigned ret = 0;
264
265 if (irq != -1)
266 ret = cpu_from_irq(irq);
267
268 return ret;
e46cdb66
JF
269}
270
d46a78b0
JF
271static bool pirq_needs_eoi(unsigned irq)
272{
273 struct irq_info *info = info_for_irq(irq);
274
275 BUG_ON(info->type != IRQT_PIRQ);
276
277 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
278}
279
e46cdb66
JF
280static inline unsigned long active_evtchns(unsigned int cpu,
281 struct shared_info *sh,
282 unsigned int idx)
283{
088c05a8 284 return sh->evtchn_pending[idx] &
cb60d114 285 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 286 ~sh->evtchn_mask[idx];
e46cdb66
JF
287}
288
289static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
290{
291 int irq = evtchn_to_irq[chn];
292
293 BUG_ON(irq == -1);
294#ifdef CONFIG_SMP
c9e265e0 295 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
296#endif
297
cb60d114
IC
298 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
299 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 300
ca62ce8c 301 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
302}
303
304static void init_evtchn_cpu_bindings(void)
305{
1c6969ec 306 int i;
e46cdb66 307#ifdef CONFIG_SMP
6cb6537d 308 struct irq_info *info;
10e58084 309
e46cdb66 310 /* By default all event channels notify CPU#0. */
6cb6537d
IC
311 list_for_each_entry(info, &xen_irq_list_head, list) {
312 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 313 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 314 }
e46cdb66
JF
315#endif
316
1c6969ec 317 for_each_possible_cpu(i)
cb60d114
IC
318 memset(per_cpu(cpu_evtchn_mask, i),
319 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
320}
321
e46cdb66
JF
322static inline void clear_evtchn(int port)
323{
324 struct shared_info *s = HYPERVISOR_shared_info;
325 sync_clear_bit(port, &s->evtchn_pending[0]);
326}
327
328static inline void set_evtchn(int port)
329{
330 struct shared_info *s = HYPERVISOR_shared_info;
331 sync_set_bit(port, &s->evtchn_pending[0]);
332}
333
168d2f46
JF
334static inline int test_evtchn(int port)
335{
336 struct shared_info *s = HYPERVISOR_shared_info;
337 return sync_test_bit(port, &s->evtchn_pending[0]);
338}
339
e46cdb66
JF
340
341/**
342 * notify_remote_via_irq - send event to remote end of event channel via irq
343 * @irq: irq of event channel to send event to
344 *
345 * Unlike notify_remote_via_evtchn(), this is safe to use across
346 * save/restore. Notifications on a broken connection are silently
347 * dropped.
348 */
349void notify_remote_via_irq(int irq)
350{
351 int evtchn = evtchn_from_irq(irq);
352
353 if (VALID_EVTCHN(evtchn))
354 notify_remote_via_evtchn(evtchn);
355}
356EXPORT_SYMBOL_GPL(notify_remote_via_irq);
357
358static void mask_evtchn(int port)
359{
360 struct shared_info *s = HYPERVISOR_shared_info;
361 sync_set_bit(port, &s->evtchn_mask[0]);
362}
363
364static void unmask_evtchn(int port)
365{
366 struct shared_info *s = HYPERVISOR_shared_info;
367 unsigned int cpu = get_cpu();
368
369 BUG_ON(!irqs_disabled());
370
371 /* Slow path (hypercall) if this is a non-local port. */
372 if (unlikely(cpu != cpu_from_evtchn(port))) {
373 struct evtchn_unmask unmask = { .port = port };
374 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
375 } else {
780f36d8 376 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
377
378 sync_clear_bit(port, &s->evtchn_mask[0]);
379
380 /*
381 * The following is basically the equivalent of
382 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
383 * the interrupt edge' if the channel is masked.
384 */
385 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
386 !sync_test_and_set_bit(port / BITS_PER_LONG,
387 &vcpu_info->evtchn_pending_sel))
388 vcpu_info->evtchn_upcall_pending = 1;
389 }
390
391 put_cpu();
392}
393
6cb6537d
IC
394static void xen_irq_init(unsigned irq)
395{
396 struct irq_info *info;
b5328cd1 397#ifdef CONFIG_SMP
6cb6537d
IC
398 struct irq_desc *desc = irq_to_desc(irq);
399
400 /* By default all event channels notify CPU#0. */
401 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 402#endif
6cb6537d 403
ca62ce8c
IC
404 info = kzalloc(sizeof(*info), GFP_KERNEL);
405 if (info == NULL)
406 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
407
408 info->type = IRQT_UNBOUND;
409
c442b806 410 irq_set_handler_data(irq, info);
ca62ce8c 411
6cb6537d
IC
412 list_add_tail(&info->list, &xen_irq_list_head);
413}
414
7bee9768 415static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 416{
89911501
IC
417 int first = 0;
418 int irq;
0794bfc7
KRW
419
420#ifdef CONFIG_X86_IO_APIC
89911501
IC
421 /*
422 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 423 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
424 * e.g. those corresponding to event channels or MSIs
425 * etc. from the range above those "real" GSIs to avoid
426 * collisions.
427 */
428 if (xen_initial_domain() || xen_hvm_domain())
429 first = get_nr_irqs_gsi();
0794bfc7
KRW
430#endif
431
89911501 432 irq = irq_alloc_desc_from(first, -1);
3a69e916 433
e6599225
KRW
434 if (irq >= 0)
435 xen_irq_init(irq);
ced40d0f 436
e46cdb66 437 return irq;
d46a78b0
JF
438}
439
7bee9768 440static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
441{
442 int irq;
443
89911501
IC
444 /*
445 * A PV guest has no concept of a GSI (since it has no ACPI
446 * nor access to/knowledge of the physical APICs). Therefore
447 * all IRQs are dynamically allocated from the entire IRQ
448 * space.
449 */
450 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
451 return xen_allocate_irq_dynamic();
452
453 /* Legacy IRQ descriptors are already allocated by the arch. */
454 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
455 irq = gsi;
456 else
457 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 458
6cb6537d 459 xen_irq_init(irq);
c9df1ce5
IC
460
461 return irq;
462}
463
464static void xen_free_irq(unsigned irq)
465{
c442b806 466 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
467
468 list_del(&info->list);
9158c358 469
c442b806 470 irq_set_handler_data(irq, NULL);
ca62ce8c
IC
471
472 kfree(info);
473
72146104
IC
474 /* Legacy IRQ descriptors are managed by the arch. */
475 if (irq < NR_IRQS_LEGACY)
476 return;
477
c9df1ce5
IC
478 irq_free_desc(irq);
479}
480
d46a78b0
JF
481static void pirq_query_unmask(int irq)
482{
483 struct physdev_irq_status_query irq_status;
484 struct irq_info *info = info_for_irq(irq);
485
486 BUG_ON(info->type != IRQT_PIRQ);
487
7a043f11 488 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
489 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
490 irq_status.flags = 0;
491
492 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
493 if (irq_status.flags & XENIRQSTAT_needs_eoi)
494 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
495}
496
497static bool probing_irq(int irq)
498{
499 struct irq_desc *desc = irq_to_desc(irq);
500
501 return desc && desc->action == NULL;
502}
503
7e186bdd
SS
504static void eoi_pirq(struct irq_data *data)
505{
506 int evtchn = evtchn_from_irq(data->irq);
507 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
508 int rc = 0;
509
510 irq_move_irq(data);
511
512 if (VALID_EVTCHN(evtchn))
513 clear_evtchn(evtchn);
514
515 if (pirq_needs_eoi(data->irq)) {
516 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
517 WARN_ON(rc);
518 }
519}
520
521static void mask_ack_pirq(struct irq_data *data)
522{
523 disable_dynirq(data);
524 eoi_pirq(data);
525}
526
c9e265e0 527static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
528{
529 struct evtchn_bind_pirq bind_pirq;
530 struct irq_info *info = info_for_irq(irq);
531 int evtchn = evtchn_from_irq(irq);
15ebbb82 532 int rc;
d46a78b0
JF
533
534 BUG_ON(info->type != IRQT_PIRQ);
535
536 if (VALID_EVTCHN(evtchn))
537 goto out;
538
7a043f11 539 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 540 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
541 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
542 BIND_PIRQ__WILL_SHARE : 0;
543 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
544 if (rc != 0) {
d46a78b0
JF
545 if (!probing_irq(irq))
546 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
547 irq);
548 return 0;
549 }
550 evtchn = bind_pirq.port;
551
552 pirq_query_unmask(irq);
553
554 evtchn_to_irq[evtchn] = irq;
555 bind_evtchn_to_cpu(evtchn, 0);
556 info->evtchn = evtchn;
557
558out:
559 unmask_evtchn(evtchn);
7e186bdd 560 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
561
562 return 0;
563}
564
c9e265e0
TG
565static unsigned int startup_pirq(struct irq_data *data)
566{
567 return __startup_pirq(data->irq);
568}
569
570static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
571{
572 struct evtchn_close close;
c9e265e0 573 unsigned int irq = data->irq;
d46a78b0
JF
574 struct irq_info *info = info_for_irq(irq);
575 int evtchn = evtchn_from_irq(irq);
576
577 BUG_ON(info->type != IRQT_PIRQ);
578
579 if (!VALID_EVTCHN(evtchn))
580 return;
581
582 mask_evtchn(evtchn);
583
584 close.port = evtchn;
585 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
586 BUG();
587
588 bind_evtchn_to_cpu(evtchn, 0);
589 evtchn_to_irq[evtchn] = -1;
590 info->evtchn = 0;
591}
592
c9e265e0 593static void enable_pirq(struct irq_data *data)
d46a78b0 594{
c9e265e0 595 startup_pirq(data);
d46a78b0
JF
596}
597
c9e265e0 598static void disable_pirq(struct irq_data *data)
d46a78b0 599{
7e186bdd 600 disable_dynirq(data);
d46a78b0
JF
601}
602
d46a78b0
JF
603static int find_irq_by_gsi(unsigned gsi)
604{
6cb6537d 605 struct irq_info *info;
d46a78b0 606
6cb6537d
IC
607 list_for_each_entry(info, &xen_irq_list_head, list) {
608 if (info->type != IRQT_PIRQ)
d46a78b0
JF
609 continue;
610
6cb6537d
IC
611 if (info->u.pirq.gsi == gsi)
612 return info->irq;
d46a78b0
JF
613 }
614
615 return -1;
616}
617
653378ac
IC
618/*
619 * Do not make any assumptions regarding the relationship between the
620 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
621 *
622 * Note: We don't assign an event channel until the irq actually started
623 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
624 *
625 * Shareable implies level triggered, not shareable implies edge
626 * triggered here.
d46a78b0 627 */
f4d0635b
IC
628int xen_bind_pirq_gsi_to_irq(unsigned gsi,
629 unsigned pirq, int shareable, char *name)
d46a78b0 630{
a0e18116 631 int irq = -1;
d46a78b0
JF
632 struct physdev_irq irq_op;
633
77365948 634 mutex_lock(&irq_mapping_update_lock);
d46a78b0
JF
635
636 irq = find_irq_by_gsi(gsi);
637 if (irq != -1) {
7a043f11 638 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
639 irq, gsi);
640 goto out; /* XXX need refcount? */
641 }
642
c9df1ce5 643 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
644 if (irq < 0)
645 goto out;
d46a78b0 646
d46a78b0 647 irq_op.irq = irq;
b5401a96
AN
648 irq_op.vector = 0;
649
650 /* Only the privileged domain can do this. For non-priv, the pcifront
651 * driver provides a PCI bus that does the call to do exactly
652 * this in the priv domain. */
653 if (xen_initial_domain() &&
654 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 655 xen_free_irq(irq);
d46a78b0
JF
656 irq = -ENOSPC;
657 goto out;
658 }
659
beafbdc1 660 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 661 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 662
7e186bdd
SS
663 pirq_query_unmask(irq);
664 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
665 * type of interrupt: if the interrupt is an edge triggered
666 * interrupt we use handle_edge_irq.
7e186bdd 667 *
e5ac0bda
SS
668 * On the other hand if the interrupt is level triggered we use
669 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 670 * interrupts.
e5ac0bda 671 *
7e186bdd
SS
672 * Depending on the Xen version, pirq_needs_eoi might return true
673 * not only for level triggered interrupts but for edge triggered
674 * interrupts too. In any case Xen always honors the eoi mechanism,
675 * not injecting any more pirqs of the same kind if the first one
676 * hasn't received an eoi yet. Therefore using the fasteoi handler
677 * is the right choice either way.
678 */
e5ac0bda 679 if (shareable)
7e186bdd
SS
680 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
681 handle_fasteoi_irq, name);
682 else
683 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
684 handle_edge_irq, name);
685
d46a78b0 686out:
77365948 687 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
688
689 return irq;
690}
691
f731e3ef 692#ifdef CONFIG_PCI_MSI
bf480d95 693int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 694{
5cad61a6 695 int rc;
cbf6aa89 696 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 697
bf480d95 698 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 699 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 700
5cad61a6
IC
701 WARN_ONCE(rc == -ENOSYS,
702 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
703
704 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
705}
706
bf480d95 707int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
708 int pirq, int vector, const char *name,
709 domid_t domid)
809f9267 710{
bf480d95 711 int irq, ret;
4b41df7f 712
77365948 713 mutex_lock(&irq_mapping_update_lock);
809f9267 714
4b41df7f 715 irq = xen_allocate_irq_dynamic();
e6599225 716 if (irq < 0)
bb5d079a 717 goto out;
809f9267 718
7e186bdd
SS
719 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
720 name);
809f9267 721
beafbdc1 722 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 723 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
724 if (ret < 0)
725 goto error_irq;
809f9267 726out:
77365948 727 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 728 return irq;
bf480d95 729error_irq:
77365948 730 mutex_unlock(&irq_mapping_update_lock);
bf480d95 731 xen_free_irq(irq);
e6599225 732 return ret;
809f9267 733}
f731e3ef
QH
734#endif
735
b5401a96
AN
736int xen_destroy_irq(int irq)
737{
738 struct irq_desc *desc;
38aa66fc
JF
739 struct physdev_unmap_pirq unmap_irq;
740 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
741 int rc = -ENOENT;
742
77365948 743 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
744
745 desc = irq_to_desc(irq);
746 if (!desc)
747 goto out;
748
38aa66fc 749 if (xen_initial_domain()) {
12334715 750 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 751 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 752 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
753 /* If another domain quits without making the pci_disable_msix
754 * call, the Xen hypervisor takes care of freeing the PIRQs
755 * (free_domain_pirqs).
756 */
757 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
758 printk(KERN_INFO "domain %d does not have %d anymore\n",
759 info->u.pirq.domid, info->u.pirq.pirq);
760 else if (rc) {
38aa66fc
JF
761 printk(KERN_WARNING "unmap irq failed %d\n", rc);
762 goto out;
763 }
764 }
b5401a96 765
c9df1ce5 766 xen_free_irq(irq);
b5401a96
AN
767
768out:
77365948 769 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
770 return rc;
771}
772
af42b8d1 773int xen_irq_from_pirq(unsigned pirq)
d46a78b0 774{
69c358ce 775 int irq;
d46a78b0 776
69c358ce 777 struct irq_info *info;
e46cdb66 778
77365948 779 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
780
781 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 782 if (info->type != IRQT_PIRQ)
69c358ce
IC
783 continue;
784 irq = info->irq;
785 if (info->u.pirq.pirq == pirq)
786 goto out;
787 }
788 irq = -1;
789out:
77365948 790 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
791
792 return irq;
af42b8d1
SS
793}
794
e6197acc
KRW
795
796int xen_pirq_from_irq(unsigned irq)
797{
798 return pirq_from_irq(irq);
799}
800EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 801int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
802{
803 int irq;
804
77365948 805 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
806
807 irq = evtchn_to_irq[evtchn];
808
809 if (irq == -1) {
c9df1ce5 810 irq = xen_allocate_irq_dynamic();
7bee9768
IC
811 if (irq == -1)
812 goto out;
e46cdb66 813
c442b806 814 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 815 handle_edge_irq, "event");
e46cdb66 816
9158c358 817 xen_irq_info_evtchn_init(irq, evtchn);
e46cdb66
JF
818 }
819
7bee9768 820out:
77365948 821 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
822
823 return irq;
824}
b536b4b9 825EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 826
f87e4cac
JF
827static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
828{
829 struct evtchn_bind_ipi bind_ipi;
830 int evtchn, irq;
831
77365948 832 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
833
834 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 835
f87e4cac 836 if (irq == -1) {
c9df1ce5 837 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
838 if (irq < 0)
839 goto out;
840
c442b806 841 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 842 handle_percpu_irq, "ipi");
f87e4cac
JF
843
844 bind_ipi.vcpu = cpu;
845 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
846 &bind_ipi) != 0)
847 BUG();
848 evtchn = bind_ipi.port;
849
3d4cfa37 850 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
851
852 bind_evtchn_to_cpu(evtchn, cpu);
853 }
854
f87e4cac 855 out:
77365948 856 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
857 return irq;
858}
859
2e820f58
IC
860static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
861 unsigned int remote_port)
862{
863 struct evtchn_bind_interdomain bind_interdomain;
864 int err;
865
866 bind_interdomain.remote_dom = remote_domain;
867 bind_interdomain.remote_port = remote_port;
868
869 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
870 &bind_interdomain);
871
872 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
873}
874
62cc5fc7
OH
875static int find_virq(unsigned int virq, unsigned int cpu)
876{
877 struct evtchn_status status;
878 int port, rc = -ENOENT;
879
880 memset(&status, 0, sizeof(status));
881 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
882 status.dom = DOMID_SELF;
883 status.port = port;
884 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
885 if (rc < 0)
886 continue;
887 if (status.status != EVTCHNSTAT_virq)
888 continue;
889 if (status.u.virq == virq && status.vcpu == cpu) {
890 rc = port;
891 break;
892 }
893 }
894 return rc;
895}
f87e4cac 896
4fe7d5a7 897int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
898{
899 struct evtchn_bind_virq bind_virq;
62cc5fc7 900 int evtchn, irq, ret;
e46cdb66 901
77365948 902 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
903
904 irq = per_cpu(virq_to_irq, cpu)[virq];
905
906 if (irq == -1) {
c9df1ce5 907 irq = xen_allocate_irq_dynamic();
7bee9768
IC
908 if (irq == -1)
909 goto out;
a52521f1 910
c442b806 911 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
912 handle_percpu_irq, "virq");
913
e46cdb66
JF
914 bind_virq.virq = virq;
915 bind_virq.vcpu = cpu;
62cc5fc7
OH
916 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
917 &bind_virq);
918 if (ret == 0)
919 evtchn = bind_virq.port;
920 else {
921 if (ret == -EEXIST)
922 ret = find_virq(virq, cpu);
923 BUG_ON(ret < 0);
924 evtchn = ret;
925 }
e46cdb66 926
3d4cfa37 927 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
928
929 bind_evtchn_to_cpu(evtchn, cpu);
930 }
931
7bee9768 932out:
77365948 933 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
934
935 return irq;
936}
937
938static void unbind_from_irq(unsigned int irq)
939{
940 struct evtchn_close close;
941 int evtchn = evtchn_from_irq(irq);
942
77365948 943 mutex_lock(&irq_mapping_update_lock);
e46cdb66 944
d77bbd4d 945 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
946 close.port = evtchn;
947 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
948 BUG();
949
950 switch (type_from_irq(irq)) {
951 case IRQT_VIRQ:
952 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 953 [virq_from_irq(irq)] = -1;
e46cdb66 954 break;
d68d82af
AN
955 case IRQT_IPI:
956 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 957 [ipi_from_irq(irq)] = -1;
d68d82af 958 break;
e46cdb66
JF
959 default:
960 break;
961 }
962
963 /* Closed ports are implicitly re-bound to VCPU0. */
964 bind_evtchn_to_cpu(evtchn, 0);
965
966 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
967 }
968
ca62ce8c 969 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 970
9158c358 971 xen_free_irq(irq);
e46cdb66 972
77365948 973 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
974}
975
976int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 977 irq_handler_t handler,
e46cdb66
JF
978 unsigned long irqflags,
979 const char *devname, void *dev_id)
980{
361ae8cb 981 int irq, retval;
e46cdb66
JF
982
983 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
984 if (irq < 0)
985 return irq;
e46cdb66
JF
986 retval = request_irq(irq, handler, irqflags, devname, dev_id);
987 if (retval != 0) {
988 unbind_from_irq(irq);
989 return retval;
990 }
991
992 return irq;
993}
994EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
995
2e820f58
IC
996int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
997 unsigned int remote_port,
998 irq_handler_t handler,
999 unsigned long irqflags,
1000 const char *devname,
1001 void *dev_id)
1002{
1003 int irq, retval;
1004
1005 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1006 if (irq < 0)
1007 return irq;
1008
1009 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1010 if (retval != 0) {
1011 unbind_from_irq(irq);
1012 return retval;
1013 }
1014
1015 return irq;
1016}
1017EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1018
e46cdb66 1019int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1020 irq_handler_t handler,
e46cdb66
JF
1021 unsigned long irqflags, const char *devname, void *dev_id)
1022{
361ae8cb 1023 int irq, retval;
e46cdb66
JF
1024
1025 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1026 if (irq < 0)
1027 return irq;
e46cdb66
JF
1028 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1029 if (retval != 0) {
1030 unbind_from_irq(irq);
1031 return retval;
1032 }
1033
1034 return irq;
1035}
1036EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1037
f87e4cac
JF
1038int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1039 unsigned int cpu,
1040 irq_handler_t handler,
1041 unsigned long irqflags,
1042 const char *devname,
1043 void *dev_id)
1044{
1045 int irq, retval;
1046
1047 irq = bind_ipi_to_irq(ipi, cpu);
1048 if (irq < 0)
1049 return irq;
1050
9bab0b7f 1051 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1052 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1053 if (retval != 0) {
1054 unbind_from_irq(irq);
1055 return retval;
1056 }
1057
1058 return irq;
1059}
1060
e46cdb66
JF
1061void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1062{
1063 free_irq(irq, dev_id);
1064 unbind_from_irq(irq);
1065}
1066EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1067
f87e4cac
JF
1068void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1069{
1070 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1071 BUG_ON(irq < 0);
1072 notify_remote_via_irq(irq);
1073}
1074
ee523ca1
JF
1075irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1076{
1077 struct shared_info *sh = HYPERVISOR_shared_info;
1078 int cpu = smp_processor_id();
cb60d114 1079 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1080 int i;
1081 unsigned long flags;
1082 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1083 struct vcpu_info *v;
ee523ca1
JF
1084
1085 spin_lock_irqsave(&debug_lock, flags);
1086
cb52e6d9 1087 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1088
1089 for_each_online_cpu(i) {
cb52e6d9
IC
1090 int pending;
1091 v = per_cpu(xen_vcpu, i);
1092 pending = (get_irq_regs() && i == cpu)
1093 ? xen_irqs_disabled(get_irq_regs())
1094 : v->evtchn_upcall_mask;
1095 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1096 pending, v->evtchn_upcall_pending,
1097 (int)(sizeof(v->evtchn_pending_sel)*2),
1098 v->evtchn_pending_sel);
1099 }
1100 v = per_cpu(xen_vcpu, cpu);
1101
1102 printk("\npending:\n ");
1103 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1104 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1105 sh->evtchn_pending[i],
1106 i % 8 == 0 ? "\n " : " ");
1107 printk("\nglobal mask:\n ");
1108 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1109 printk("%0*lx%s",
1110 (int)(sizeof(sh->evtchn_mask[0])*2),
1111 sh->evtchn_mask[i],
1112 i % 8 == 0 ? "\n " : " ");
1113
1114 printk("\nglobally unmasked:\n ");
1115 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1116 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1117 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1118 i % 8 == 0 ? "\n " : " ");
1119
1120 printk("\nlocal cpu%d mask:\n ", cpu);
1121 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1122 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1123 cpu_evtchn[i],
1124 i % 8 == 0 ? "\n " : " ");
1125
1126 printk("\nlocally unmasked:\n ");
1127 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1128 unsigned long pending = sh->evtchn_pending[i]
1129 & ~sh->evtchn_mask[i]
1130 & cpu_evtchn[i];
1131 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1132 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1133 }
ee523ca1
JF
1134
1135 printk("\npending list:\n");
cb52e6d9 1136 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1137 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1138 int word_idx = i / BITS_PER_LONG;
1139 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1140 cpu_from_evtchn(i), i,
cb52e6d9
IC
1141 evtchn_to_irq[i],
1142 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1143 ? "" : " l2-clear",
1144 !sync_test_bit(i, sh->evtchn_mask)
1145 ? "" : " globally-masked",
1146 sync_test_bit(i, cpu_evtchn)
1147 ? "" : " locally-masked");
ee523ca1
JF
1148 }
1149 }
1150
1151 spin_unlock_irqrestore(&debug_lock, flags);
1152
1153 return IRQ_HANDLED;
1154}
1155
245b2e70 1156static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1157static DEFINE_PER_CPU(unsigned int, current_word_idx);
1158static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1159
ab7f863e
SR
1160/*
1161 * Mask out the i least significant bits of w
1162 */
1163#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1164
e46cdb66
JF
1165/*
1166 * Search the CPUs pending events bitmasks. For each one found, map
1167 * the event number to an irq, and feed it into do_IRQ() for
1168 * handling.
1169 *
1170 * Xen uses a two-level bitmap to speed searching. The first level is
1171 * a bitset of words which contain pending event bits. The second
1172 * level is a bitset of pending events themselves.
1173 */
38e20b07 1174static void __xen_evtchn_do_upcall(void)
e46cdb66 1175{
24b51c2f 1176 int start_word_idx, start_bit_idx;
ab7f863e 1177 int word_idx, bit_idx;
24b51c2f 1178 int i;
e46cdb66
JF
1179 int cpu = get_cpu();
1180 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1181 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1182 unsigned count;
e46cdb66 1183
229664be
JF
1184 do {
1185 unsigned long pending_words;
e46cdb66 1186
229664be 1187 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1188
b2e4ae69 1189 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1190 goto out;
e46cdb66 1191
e849c3e9
IY
1192#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1193 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1194 wmb();
e849c3e9 1195#endif
229664be 1196 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1197
24b51c2f
KF
1198 start_word_idx = __this_cpu_read(current_word_idx);
1199 start_bit_idx = __this_cpu_read(current_bit_idx);
1200
1201 word_idx = start_word_idx;
ab7f863e 1202
24b51c2f 1203 for (i = 0; pending_words != 0; i++) {
229664be 1204 unsigned long pending_bits;
ab7f863e 1205 unsigned long words;
229664be 1206
ab7f863e
SR
1207 words = MASK_LSBS(pending_words, word_idx);
1208
1209 /*
ada6814c 1210 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1211 */
1212 if (words == 0) {
ada6814c
KF
1213 word_idx = 0;
1214 bit_idx = 0;
ab7f863e
SR
1215 continue;
1216 }
1217 word_idx = __ffs(words);
229664be 1218
24b51c2f
KF
1219 pending_bits = active_evtchns(cpu, s, word_idx);
1220 bit_idx = 0; /* usually scan entire word from start */
1221 if (word_idx == start_word_idx) {
1222 /* We scan the starting word in two parts */
1223 if (i == 0)
1224 /* 1st time: start in the middle */
1225 bit_idx = start_bit_idx;
1226 else
1227 /* 2nd time: mask bits done already */
1228 bit_idx &= (1UL << start_bit_idx) - 1;
1229 }
1230
ab7f863e
SR
1231 do {
1232 unsigned long bits;
1233 int port, irq;
ca4dbc66 1234 struct irq_desc *desc;
229664be 1235
ab7f863e
SR
1236 bits = MASK_LSBS(pending_bits, bit_idx);
1237
1238 /* If we masked out all events, move on. */
ada6814c 1239 if (bits == 0)
ab7f863e 1240 break;
ab7f863e
SR
1241
1242 bit_idx = __ffs(bits);
1243
1244 /* Process port. */
1245 port = (word_idx * BITS_PER_LONG) + bit_idx;
1246 irq = evtchn_to_irq[port];
1247
ca4dbc66
EB
1248 if (irq != -1) {
1249 desc = irq_to_desc(irq);
1250 if (desc)
1251 generic_handle_irq_desc(irq, desc);
1252 }
ab7f863e 1253
ada6814c
KF
1254 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1255
1256 /* Next caller starts at last processed + 1 */
1257 __this_cpu_write(current_word_idx,
1258 bit_idx ? word_idx :
1259 (word_idx+1) % BITS_PER_LONG);
1260 __this_cpu_write(current_bit_idx, bit_idx);
1261 } while (bit_idx != 0);
ab7f863e 1262
24b51c2f
KF
1263 /* Scan start_l1i twice; all others once. */
1264 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1265 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1266
1267 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1268 }
e46cdb66 1269
229664be
JF
1270 BUG_ON(!irqs_disabled());
1271
780f36d8
CL
1272 count = __this_cpu_read(xed_nesting_count);
1273 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1274 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1275
1276out:
38e20b07
SY
1277
1278 put_cpu();
1279}
1280
1281void xen_evtchn_do_upcall(struct pt_regs *regs)
1282{
1283 struct pt_regs *old_regs = set_irq_regs(regs);
1284
1285 exit_idle();
1286 irq_enter();
1287
1288 __xen_evtchn_do_upcall();
1289
3445a8fd
JF
1290 irq_exit();
1291 set_irq_regs(old_regs);
38e20b07 1292}
3445a8fd 1293
38e20b07
SY
1294void xen_hvm_evtchn_do_upcall(void)
1295{
1296 __xen_evtchn_do_upcall();
e46cdb66 1297}
183d03cc 1298EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1299
eb1e305f
JF
1300/* Rebind a new event channel to an existing irq. */
1301void rebind_evtchn_irq(int evtchn, int irq)
1302{
d77bbd4d
JF
1303 struct irq_info *info = info_for_irq(irq);
1304
eb1e305f
JF
1305 /* Make sure the irq is masked, since the new event channel
1306 will also be masked. */
1307 disable_irq(irq);
1308
77365948 1309 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1310
1311 /* After resume the irq<->evtchn mappings are all cleared out */
1312 BUG_ON(evtchn_to_irq[evtchn] != -1);
1313 /* Expect irq to have been bound before,
d77bbd4d
JF
1314 so there should be a proper type */
1315 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1316
9158c358 1317 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1318
77365948 1319 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1320
1321 /* new event channels are always bound to cpu 0 */
0de26520 1322 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1323
1324 /* Unmask the event channel. */
1325 enable_irq(irq);
1326}
1327
e46cdb66 1328/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1329static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1330{
1331 struct evtchn_bind_vcpu bind_vcpu;
1332 int evtchn = evtchn_from_irq(irq);
1333
be49472f
IC
1334 if (!VALID_EVTCHN(evtchn))
1335 return -1;
1336
1337 /*
1338 * Events delivered via platform PCI interrupts are always
1339 * routed to vcpu 0 and hence cannot be rebound.
1340 */
1341 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1342 return -1;
e46cdb66
JF
1343
1344 /* Send future instances of this interrupt to other vcpu. */
1345 bind_vcpu.port = evtchn;
1346 bind_vcpu.vcpu = tcpu;
1347
1348 /*
1349 * If this fails, it usually just indicates that we're dealing with a
1350 * virq or IPI channel, which don't actually need to be rebound. Ignore
1351 * it, but don't do the xenlinux-level rebind in that case.
1352 */
1353 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1354 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1355
d5dedd45
YL
1356 return 0;
1357}
e46cdb66 1358
c9e265e0
TG
1359static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1360 bool force)
e46cdb66 1361{
0de26520 1362 unsigned tcpu = cpumask_first(dest);
d5dedd45 1363
c9e265e0 1364 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1365}
1366
642e0c88
IY
1367int resend_irq_on_evtchn(unsigned int irq)
1368{
1369 int masked, evtchn = evtchn_from_irq(irq);
1370 struct shared_info *s = HYPERVISOR_shared_info;
1371
1372 if (!VALID_EVTCHN(evtchn))
1373 return 1;
1374
1375 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1376 sync_set_bit(evtchn, s->evtchn_pending);
1377 if (!masked)
1378 unmask_evtchn(evtchn);
1379
1380 return 1;
1381}
1382
c9e265e0 1383static void enable_dynirq(struct irq_data *data)
e46cdb66 1384{
c9e265e0 1385 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1386
1387 if (VALID_EVTCHN(evtchn))
1388 unmask_evtchn(evtchn);
1389}
1390
c9e265e0 1391static void disable_dynirq(struct irq_data *data)
e46cdb66 1392{
c9e265e0 1393 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1394
1395 if (VALID_EVTCHN(evtchn))
1396 mask_evtchn(evtchn);
1397}
1398
c9e265e0 1399static void ack_dynirq(struct irq_data *data)
e46cdb66 1400{
c9e265e0 1401 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1402
7e186bdd 1403 irq_move_irq(data);
e46cdb66
JF
1404
1405 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1406 clear_evtchn(evtchn);
1407}
1408
1409static void mask_ack_dynirq(struct irq_data *data)
1410{
1411 disable_dynirq(data);
1412 ack_dynirq(data);
e46cdb66
JF
1413}
1414
c9e265e0 1415static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1416{
c9e265e0 1417 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1418 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1419 int ret = 0;
1420
1421 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1422 int masked;
1423
1424 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1425 sync_set_bit(evtchn, sh->evtchn_pending);
1426 if (!masked)
1427 unmask_evtchn(evtchn);
e46cdb66
JF
1428 ret = 1;
1429 }
1430
1431 return ret;
1432}
1433
0a85226f 1434static void restore_pirqs(void)
9a069c33
SS
1435{
1436 int pirq, rc, irq, gsi;
1437 struct physdev_map_pirq map_irq;
69c358ce 1438 struct irq_info *info;
9a069c33 1439
69c358ce
IC
1440 list_for_each_entry(info, &xen_irq_list_head, list) {
1441 if (info->type != IRQT_PIRQ)
9a069c33
SS
1442 continue;
1443
69c358ce
IC
1444 pirq = info->u.pirq.pirq;
1445 gsi = info->u.pirq.gsi;
1446 irq = info->irq;
1447
9a069c33
SS
1448 /* save/restore of PT devices doesn't work, so at this point the
1449 * only devices present are GSI based emulated devices */
9a069c33
SS
1450 if (!gsi)
1451 continue;
1452
1453 map_irq.domid = DOMID_SELF;
1454 map_irq.type = MAP_PIRQ_TYPE_GSI;
1455 map_irq.index = gsi;
1456 map_irq.pirq = pirq;
1457
1458 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1459 if (rc) {
1460 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1461 gsi, irq, pirq, rc);
9158c358 1462 xen_free_irq(irq);
9a069c33
SS
1463 continue;
1464 }
1465
1466 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1467
c9e265e0 1468 __startup_pirq(irq);
9a069c33
SS
1469 }
1470}
1471
0e91398f
JF
1472static void restore_cpu_virqs(unsigned int cpu)
1473{
1474 struct evtchn_bind_virq bind_virq;
1475 int virq, irq, evtchn;
1476
1477 for (virq = 0; virq < NR_VIRQS; virq++) {
1478 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1479 continue;
1480
ced40d0f 1481 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1482
1483 /* Get a new binding from Xen. */
1484 bind_virq.virq = virq;
1485 bind_virq.vcpu = cpu;
1486 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1487 &bind_virq) != 0)
1488 BUG();
1489 evtchn = bind_virq.port;
1490
1491 /* Record the new mapping. */
3d4cfa37 1492 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1493 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1494 }
1495}
1496
1497static void restore_cpu_ipis(unsigned int cpu)
1498{
1499 struct evtchn_bind_ipi bind_ipi;
1500 int ipi, irq, evtchn;
1501
1502 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1503 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1504 continue;
1505
ced40d0f 1506 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1507
1508 /* Get a new binding from Xen. */
1509 bind_ipi.vcpu = cpu;
1510 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1511 &bind_ipi) != 0)
1512 BUG();
1513 evtchn = bind_ipi.port;
1514
1515 /* Record the new mapping. */
3d4cfa37 1516 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1517 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1518 }
1519}
1520
2d9e1e2f
JF
1521/* Clear an irq's pending state, in preparation for polling on it */
1522void xen_clear_irq_pending(int irq)
1523{
1524 int evtchn = evtchn_from_irq(irq);
1525
1526 if (VALID_EVTCHN(evtchn))
1527 clear_evtchn(evtchn);
1528}
d9a8814f 1529EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1530void xen_set_irq_pending(int irq)
1531{
1532 int evtchn = evtchn_from_irq(irq);
1533
1534 if (VALID_EVTCHN(evtchn))
1535 set_evtchn(evtchn);
1536}
1537
1538bool xen_test_irq_pending(int irq)
1539{
1540 int evtchn = evtchn_from_irq(irq);
1541 bool ret = false;
1542
1543 if (VALID_EVTCHN(evtchn))
1544 ret = test_evtchn(evtchn);
1545
1546 return ret;
1547}
1548
d9a8814f
KRW
1549/* Poll waiting for an irq to become pending with timeout. In the usual case,
1550 * the irq will be disabled so it won't deliver an interrupt. */
1551void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1552{
1553 evtchn_port_t evtchn = evtchn_from_irq(irq);
1554
1555 if (VALID_EVTCHN(evtchn)) {
1556 struct sched_poll poll;
1557
1558 poll.nr_ports = 1;
d9a8814f 1559 poll.timeout = timeout;
ff3c5362 1560 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1561
1562 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1563 BUG();
1564 }
1565}
d9a8814f
KRW
1566EXPORT_SYMBOL(xen_poll_irq_timeout);
1567/* Poll waiting for an irq to become pending. In the usual case, the
1568 * irq will be disabled so it won't deliver an interrupt. */
1569void xen_poll_irq(int irq)
1570{
1571 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1572}
2d9e1e2f 1573
c7c2c3a2
KRW
1574/* Check whether the IRQ line is shared with other guests. */
1575int xen_test_irq_shared(int irq)
1576{
1577 struct irq_info *info = info_for_irq(irq);
1578 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1579
1580 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1581 return 0;
1582 return !(irq_status.flags & XENIRQSTAT_shared);
1583}
1584EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1585
0e91398f
JF
1586void xen_irq_resume(void)
1587{
6cb6537d
IC
1588 unsigned int cpu, evtchn;
1589 struct irq_info *info;
0e91398f
JF
1590
1591 init_evtchn_cpu_bindings();
1592
1593 /* New event-channel space is not 'live' yet. */
1594 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1595 mask_evtchn(evtchn);
1596
1597 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1598 list_for_each_entry(info, &xen_irq_list_head, list)
1599 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1600
1601 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1602 evtchn_to_irq[evtchn] = -1;
1603
1604 for_each_possible_cpu(cpu) {
1605 restore_cpu_virqs(cpu);
1606 restore_cpu_ipis(cpu);
1607 }
6903591f 1608
0a85226f 1609 restore_pirqs();
0e91398f
JF
1610}
1611
e46cdb66 1612static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1613 .name = "xen-dyn",
54a353a0 1614
c9e265e0
TG
1615 .irq_disable = disable_dynirq,
1616 .irq_mask = disable_dynirq,
1617 .irq_unmask = enable_dynirq,
54a353a0 1618
7e186bdd
SS
1619 .irq_ack = ack_dynirq,
1620 .irq_mask_ack = mask_ack_dynirq,
1621
c9e265e0
TG
1622 .irq_set_affinity = set_affinity_irq,
1623 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1624};
1625
d46a78b0 1626static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1627 .name = "xen-pirq",
d46a78b0 1628
c9e265e0
TG
1629 .irq_startup = startup_pirq,
1630 .irq_shutdown = shutdown_pirq,
c9e265e0 1631 .irq_enable = enable_pirq,
c9e265e0 1632 .irq_disable = disable_pirq,
d46a78b0 1633
7e186bdd
SS
1634 .irq_mask = disable_dynirq,
1635 .irq_unmask = enable_dynirq,
1636
1637 .irq_ack = eoi_pirq,
1638 .irq_eoi = eoi_pirq,
1639 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1640
c9e265e0 1641 .irq_set_affinity = set_affinity_irq,
d46a78b0 1642
c9e265e0 1643 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1644};
1645
aaca4964 1646static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1647 .name = "xen-percpu",
aaca4964 1648
c9e265e0
TG
1649 .irq_disable = disable_dynirq,
1650 .irq_mask = disable_dynirq,
1651 .irq_unmask = enable_dynirq,
aaca4964 1652
c9e265e0 1653 .irq_ack = ack_dynirq,
aaca4964
JF
1654};
1655
38e20b07
SY
1656int xen_set_callback_via(uint64_t via)
1657{
1658 struct xen_hvm_param a;
1659 a.domid = DOMID_SELF;
1660 a.index = HVM_PARAM_CALLBACK_IRQ;
1661 a.value = via;
1662 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1663}
1664EXPORT_SYMBOL_GPL(xen_set_callback_via);
1665
ca65f9fc 1666#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1667/* Vector callbacks are better than PCI interrupts to receive event
1668 * channel notifications because we can receive vector callbacks on any
1669 * vcpu and we don't need PCI support or APIC interactions. */
1670void xen_callback_vector(void)
1671{
1672 int rc;
1673 uint64_t callback_via;
1674 if (xen_have_vector_callback) {
1675 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1676 rc = xen_set_callback_via(callback_via);
1677 if (rc) {
1678 printk(KERN_ERR "Request for Xen HVM callback vector"
1679 " failed.\n");
1680 xen_have_vector_callback = 0;
1681 return;
1682 }
1683 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1684 "enabled\n");
1685 /* in the restore case the vector has already been allocated */
1686 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1687 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1688 }
1689}
ca65f9fc
SS
1690#else
1691void xen_callback_vector(void) {}
1692#endif
38e20b07 1693
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1694void __init xen_init_IRQ(void)
1695{
e5fc7345 1696 int i;
c7a3589e 1697
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1698 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1699 GFP_KERNEL);
9d093e29 1700 BUG_ON(!evtchn_to_irq);
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1701 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1702 evtchn_to_irq[i] = -1;
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1703
1704 init_evtchn_cpu_bindings();
1705
1706 /* No event channels are 'live' right now. */
1707 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1708 mask_evtchn(i);
1709
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1710 if (xen_hvm_domain()) {
1711 xen_callback_vector();
1712 native_init_IRQ();
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SS
1713 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1714 * __acpi_register_gsi can point at the right function */
1715 pci_xen_hvm_init();
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SY
1716 } else {
1717 irq_ctx_init(smp_processor_id());
38aa66fc 1718 if (xen_initial_domain())
a0ee0567 1719 pci_xen_initial_domain();
38e20b07 1720 }
e46cdb66 1721}