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xen: Remove stale irq_chip.end
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CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
110e7c7e
JJ
173 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
174 return 0;
175
ced40d0f 176 return info_for_irq(irq)->evtchn;
e46cdb66
JF
177}
178
d4c04536
IC
179unsigned irq_from_evtchn(unsigned int evtchn)
180{
181 return evtchn_to_irq[evtchn];
182}
183EXPORT_SYMBOL_GPL(irq_from_evtchn);
184
ced40d0f 185static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 186{
ced40d0f
JF
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_IPI);
191
192 return info->u.ipi;
193}
194
195static unsigned virq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_VIRQ);
201
202 return info->u.virq;
203}
204
7a043f11
SS
205static unsigned pirq_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.pirq;
213}
214
ced40d0f
JF
215static unsigned gsi_from_irq(unsigned irq)
216{
217 struct irq_info *info = info_for_irq(irq);
218
219 BUG_ON(info == NULL);
220 BUG_ON(info->type != IRQT_PIRQ);
221
222 return info->u.pirq.gsi;
223}
224
225static unsigned vector_from_irq(unsigned irq)
226{
227 struct irq_info *info = info_for_irq(irq);
228
229 BUG_ON(info == NULL);
230 BUG_ON(info->type != IRQT_PIRQ);
231
232 return info->u.pirq.vector;
233}
234
235static enum xen_irq_type type_from_irq(unsigned irq)
236{
237 return info_for_irq(irq)->type;
238}
239
240static unsigned cpu_from_irq(unsigned irq)
241{
242 return info_for_irq(irq)->cpu;
243}
244
245static unsigned int cpu_from_evtchn(unsigned int evtchn)
246{
247 int irq = evtchn_to_irq[evtchn];
248 unsigned ret = 0;
249
250 if (irq != -1)
251 ret = cpu_from_irq(irq);
252
253 return ret;
e46cdb66
JF
254}
255
d46a78b0
JF
256static bool pirq_needs_eoi(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info->type != IRQT_PIRQ);
261
262 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
263}
264
e46cdb66
JF
265static inline unsigned long active_evtchns(unsigned int cpu,
266 struct shared_info *sh,
267 unsigned int idx)
268{
269 return (sh->evtchn_pending[idx] &
c7a3589e 270 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
271 ~sh->evtchn_mask[idx]);
272}
273
274static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
275{
276 int irq = evtchn_to_irq[chn];
277
278 BUG_ON(irq == -1);
279#ifdef CONFIG_SMP
7f7ace0c 280 cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
e46cdb66
JF
281#endif
282
e0419564
JF
283 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
284 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 285
ced40d0f 286 irq_info[irq].cpu = cpu;
e46cdb66
JF
287}
288
289static void init_evtchn_cpu_bindings(void)
290{
1c6969ec 291 int i;
e46cdb66 292#ifdef CONFIG_SMP
10e58084 293 struct irq_desc *desc;
10e58084 294
e46cdb66 295 /* By default all event channels notify CPU#0. */
0b8f1efa 296 for_each_irq_desc(i, desc) {
7f7ace0c 297 cpumask_copy(desc->affinity, cpumask_of(0));
0b8f1efa 298 }
e46cdb66
JF
299#endif
300
1c6969ec
JB
301 for_each_possible_cpu(i)
302 memset(cpu_evtchn_mask(i),
303 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
304
e46cdb66
JF
305}
306
e46cdb66
JF
307static inline void clear_evtchn(int port)
308{
309 struct shared_info *s = HYPERVISOR_shared_info;
310 sync_clear_bit(port, &s->evtchn_pending[0]);
311}
312
313static inline void set_evtchn(int port)
314{
315 struct shared_info *s = HYPERVISOR_shared_info;
316 sync_set_bit(port, &s->evtchn_pending[0]);
317}
318
168d2f46
JF
319static inline int test_evtchn(int port)
320{
321 struct shared_info *s = HYPERVISOR_shared_info;
322 return sync_test_bit(port, &s->evtchn_pending[0]);
323}
324
e46cdb66
JF
325
326/**
327 * notify_remote_via_irq - send event to remote end of event channel via irq
328 * @irq: irq of event channel to send event to
329 *
330 * Unlike notify_remote_via_evtchn(), this is safe to use across
331 * save/restore. Notifications on a broken connection are silently
332 * dropped.
333 */
334void notify_remote_via_irq(int irq)
335{
336 int evtchn = evtchn_from_irq(irq);
337
338 if (VALID_EVTCHN(evtchn))
339 notify_remote_via_evtchn(evtchn);
340}
341EXPORT_SYMBOL_GPL(notify_remote_via_irq);
342
343static void mask_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
346 sync_set_bit(port, &s->evtchn_mask[0]);
347}
348
349static void unmask_evtchn(int port)
350{
351 struct shared_info *s = HYPERVISOR_shared_info;
352 unsigned int cpu = get_cpu();
353
354 BUG_ON(!irqs_disabled());
355
356 /* Slow path (hypercall) if this is a non-local port. */
357 if (unlikely(cpu != cpu_from_evtchn(port))) {
358 struct evtchn_unmask unmask = { .port = port };
359 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
360 } else {
780f36d8 361 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
362
363 sync_clear_bit(port, &s->evtchn_mask[0]);
364
365 /*
366 * The following is basically the equivalent of
367 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
368 * the interrupt edge' if the channel is masked.
369 */
370 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
371 !sync_test_and_set_bit(port / BITS_PER_LONG,
372 &vcpu_info->evtchn_pending_sel))
373 vcpu_info->evtchn_upcall_pending = 1;
374 }
375
376 put_cpu();
377}
378
89911501 379static int xen_allocate_irq_dynamic(void)
0794bfc7 380{
89911501
IC
381 int first = 0;
382 int irq;
0794bfc7
KRW
383
384#ifdef CONFIG_X86_IO_APIC
89911501
IC
385 /*
386 * For an HVM guest or domain 0 which see "real" (emulated or
387 * actual repectively) GSIs we allocate dynamic IRQs
388 * e.g. those corresponding to event channels or MSIs
389 * etc. from the range above those "real" GSIs to avoid
390 * collisions.
391 */
392 if (xen_initial_domain() || xen_hvm_domain())
393 first = get_nr_irqs_gsi();
0794bfc7
KRW
394#endif
395
89911501
IC
396retry:
397 irq = irq_alloc_desc_from(first, -1);
3a69e916 398
89911501
IC
399 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
400 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
401 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
402 goto retry;
99ad198c 403 }
e46cdb66 404
89911501
IC
405 if (irq < 0)
406 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 407
e46cdb66 408 return irq;
d46a78b0
JF
409}
410
c9df1ce5
IC
411static int xen_allocate_irq_gsi(unsigned gsi)
412{
413 int irq;
414
89911501
IC
415 /*
416 * A PV guest has no concept of a GSI (since it has no ACPI
417 * nor access to/knowledge of the physical APICs). Therefore
418 * all IRQs are dynamically allocated from the entire IRQ
419 * space.
420 */
421 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
422 return xen_allocate_irq_dynamic();
423
424 /* Legacy IRQ descriptors are already allocated by the arch. */
425 if (gsi < NR_IRQS_LEGACY)
426 return gsi;
427
428 irq = irq_alloc_desc_at(gsi, -1);
429 if (irq < 0)
430 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
431
432 return irq;
433}
434
435static void xen_free_irq(unsigned irq)
436{
72146104
IC
437 /* Legacy IRQ descriptors are managed by the arch. */
438 if (irq < NR_IRQS_LEGACY)
439 return;
440
c9df1ce5
IC
441 irq_free_desc(irq);
442}
443
d46a78b0
JF
444static void pirq_unmask_notify(int irq)
445{
7a043f11 446 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
447
448 if (unlikely(pirq_needs_eoi(irq))) {
449 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
450 WARN_ON(rc);
451 }
452}
453
454static void pirq_query_unmask(int irq)
455{
456 struct physdev_irq_status_query irq_status;
457 struct irq_info *info = info_for_irq(irq);
458
459 BUG_ON(info->type != IRQT_PIRQ);
460
7a043f11 461 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
462 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
463 irq_status.flags = 0;
464
465 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
466 if (irq_status.flags & XENIRQSTAT_needs_eoi)
467 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
468}
469
470static bool probing_irq(int irq)
471{
472 struct irq_desc *desc = irq_to_desc(irq);
473
474 return desc && desc->action == NULL;
475}
476
477static unsigned int startup_pirq(unsigned int irq)
478{
479 struct evtchn_bind_pirq bind_pirq;
480 struct irq_info *info = info_for_irq(irq);
481 int evtchn = evtchn_from_irq(irq);
15ebbb82 482 int rc;
d46a78b0
JF
483
484 BUG_ON(info->type != IRQT_PIRQ);
485
486 if (VALID_EVTCHN(evtchn))
487 goto out;
488
7a043f11 489 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 490 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
491 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
492 BIND_PIRQ__WILL_SHARE : 0;
493 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
494 if (rc != 0) {
d46a78b0
JF
495 if (!probing_irq(irq))
496 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
497 irq);
498 return 0;
499 }
500 evtchn = bind_pirq.port;
501
502 pirq_query_unmask(irq);
503
504 evtchn_to_irq[evtchn] = irq;
505 bind_evtchn_to_cpu(evtchn, 0);
506 info->evtchn = evtchn;
507
508out:
509 unmask_evtchn(evtchn);
510 pirq_unmask_notify(irq);
511
512 return 0;
513}
514
515static void shutdown_pirq(unsigned int irq)
516{
517 struct evtchn_close close;
518 struct irq_info *info = info_for_irq(irq);
519 int evtchn = evtchn_from_irq(irq);
520
521 BUG_ON(info->type != IRQT_PIRQ);
522
523 if (!VALID_EVTCHN(evtchn))
524 return;
525
526 mask_evtchn(evtchn);
527
528 close.port = evtchn;
529 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
530 BUG();
531
532 bind_evtchn_to_cpu(evtchn, 0);
533 evtchn_to_irq[evtchn] = -1;
534 info->evtchn = 0;
535}
536
537static void enable_pirq(unsigned int irq)
538{
539 startup_pirq(irq);
540}
541
542static void disable_pirq(unsigned int irq)
543{
544}
545
546static void ack_pirq(unsigned int irq)
547{
548 int evtchn = evtchn_from_irq(irq);
549
550 move_native_irq(irq);
551
552 if (VALID_EVTCHN(evtchn)) {
553 mask_evtchn(evtchn);
554 clear_evtchn(evtchn);
555 }
556}
557
d46a78b0
JF
558static int find_irq_by_gsi(unsigned gsi)
559{
560 int irq;
561
b21ddbf5 562 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
563 struct irq_info *info = info_for_irq(irq);
564
565 if (info == NULL || info->type != IRQT_PIRQ)
566 continue;
567
568 if (gsi_from_irq(irq) == gsi)
569 return irq;
570 }
571
572 return -1;
573}
574
7a043f11
SS
575int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
576{
577 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
578}
579
580/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
581 * consequence don't assume that the irq number returned has a low value
582 * or can be used as a pirq number unless you know otherwise.
583 *
7a043f11 584 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 585 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
586 * matches the gsi number passed as second argument.
587 *
588 * Note: We don't assign an event channel until the irq actually started
589 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 590 */
7a043f11 591int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 592{
7a043f11 593 int irq = 0;
d46a78b0
JF
594 struct physdev_irq irq_op;
595
596 spin_lock(&irq_mapping_update_lock);
597
e5fc7345 598 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 599 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
600 pirq > nr_irqs ? "pirq" :"",
601 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
602 goto out;
603 }
604
d46a78b0
JF
605 irq = find_irq_by_gsi(gsi);
606 if (irq != -1) {
7a043f11 607 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
608 irq, gsi);
609 goto out; /* XXX need refcount? */
610 }
611
c9df1ce5 612 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
613
614 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 615 handle_level_irq, name);
d46a78b0
JF
616
617 irq_op.irq = irq;
b5401a96
AN
618 irq_op.vector = 0;
619
620 /* Only the privileged domain can do this. For non-priv, the pcifront
621 * driver provides a PCI bus that does the call to do exactly
622 * this in the priv domain. */
623 if (xen_initial_domain() &&
624 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 625 xen_free_irq(irq);
d46a78b0
JF
626 irq = -ENOSPC;
627 goto out;
628 }
629
7a043f11 630 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 631 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 632 pirq_to_irq[pirq] = irq;
d46a78b0
JF
633
634out:
635 spin_unlock(&irq_mapping_update_lock);
636
637 return irq;
638}
639
f731e3ef
QH
640#ifdef CONFIG_PCI_MSI
641#include <linux/msi.h>
642#include "../pci/msi.h"
643
cbf6aa89
IC
644static int find_unbound_pirq(int type)
645{
646 int rc, i;
647 struct physdev_get_free_pirq op_get_free_pirq;
648 op_get_free_pirq.type = type;
649
650 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
651 if (!rc)
652 return op_get_free_pirq.pirq;
653
654 for (i = 0; i < nr_irqs; i++) {
655 if (pirq_to_irq[i] < 0)
656 return i;
657 }
658 return -1;
659}
660
af42b8d1 661void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc)
809f9267
SS
662{
663 spin_lock(&irq_mapping_update_lock);
664
af42b8d1 665 if (alloc & XEN_ALLOC_IRQ) {
c9df1ce5 666 *irq = xen_allocate_irq_dynamic();
af42b8d1
SS
667 if (*irq == -1)
668 goto out;
669 }
809f9267 670
af42b8d1
SS
671 if (alloc & XEN_ALLOC_PIRQ) {
672 *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
673 if (*pirq == -1)
674 goto out;
675 }
809f9267
SS
676
677 set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
678 handle_level_irq, name);
679
680 irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
681 pirq_to_irq[*pirq] = *irq;
682
683out:
684 spin_unlock(&irq_mapping_update_lock);
685}
686
f731e3ef
QH
687int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
688{
689 int irq = -1;
690 struct physdev_map_pirq map_irq;
691 int rc;
692 int pos;
693 u32 table_offset, bir;
694
695 memset(&map_irq, 0, sizeof(map_irq));
696 map_irq.domid = DOMID_SELF;
697 map_irq.type = MAP_PIRQ_TYPE_MSI;
698 map_irq.index = -1;
699 map_irq.pirq = -1;
700 map_irq.bus = dev->bus->number;
701 map_irq.devfn = dev->devfn;
702
703 if (type == PCI_CAP_ID_MSIX) {
704 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
705
706 pci_read_config_dword(dev, msix_table_offset_reg(pos),
707 &table_offset);
708 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
709
710 map_irq.table_base = pci_resource_start(dev, bir);
711 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
712 }
713
714 spin_lock(&irq_mapping_update_lock);
715
c9df1ce5 716 irq = xen_allocate_irq_dynamic();
f731e3ef
QH
717
718 if (irq == -1)
719 goto out;
720
721 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
722 if (rc) {
723 printk(KERN_WARNING "xen map irq failed %d\n", rc);
724
c9df1ce5 725 xen_free_irq(irq);
f731e3ef
QH
726
727 irq = -1;
728 goto out;
729 }
730 irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
731
732 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
733 handle_level_irq,
734 (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
735
736out:
737 spin_unlock(&irq_mapping_update_lock);
738 return irq;
739}
740#endif
741
b5401a96
AN
742int xen_destroy_irq(int irq)
743{
744 struct irq_desc *desc;
38aa66fc
JF
745 struct physdev_unmap_pirq unmap_irq;
746 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
747 int rc = -ENOENT;
748
749 spin_lock(&irq_mapping_update_lock);
750
751 desc = irq_to_desc(irq);
752 if (!desc)
753 goto out;
754
38aa66fc 755 if (xen_initial_domain()) {
12334715 756 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
757 unmap_irq.domid = DOMID_SELF;
758 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
759 if (rc) {
760 printk(KERN_WARNING "unmap irq failed %d\n", rc);
761 goto out;
762 }
af42b8d1 763 pirq_to_irq[info->u.pirq.pirq] = -1;
38aa66fc 764 }
b5401a96
AN
765 irq_info[irq] = mk_unbound_info();
766
c9df1ce5 767 xen_free_irq(irq);
b5401a96
AN
768
769out:
770 spin_unlock(&irq_mapping_update_lock);
771 return rc;
772}
773
d46a78b0
JF
774int xen_vector_from_irq(unsigned irq)
775{
776 return vector_from_irq(irq);
777}
778
779int xen_gsi_from_irq(unsigned irq)
780{
781 return gsi_from_irq(irq);
e46cdb66
JF
782}
783
af42b8d1
SS
784int xen_irq_from_pirq(unsigned pirq)
785{
786 return pirq_to_irq[pirq];
787}
788
b536b4b9 789int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
790{
791 int irq;
792
793 spin_lock(&irq_mapping_update_lock);
794
795 irq = evtchn_to_irq[evtchn];
796
797 if (irq == -1) {
c9df1ce5 798 irq = xen_allocate_irq_dynamic();
e46cdb66 799
e46cdb66 800 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 801 handle_fasteoi_irq, "event");
e46cdb66
JF
802
803 evtchn_to_irq[evtchn] = irq;
ced40d0f 804 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
805 }
806
e46cdb66
JF
807 spin_unlock(&irq_mapping_update_lock);
808
809 return irq;
810}
b536b4b9 811EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 812
f87e4cac
JF
813static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
814{
815 struct evtchn_bind_ipi bind_ipi;
816 int evtchn, irq;
817
818 spin_lock(&irq_mapping_update_lock);
819
820 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 821
f87e4cac 822 if (irq == -1) {
c9df1ce5 823 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
824 if (irq < 0)
825 goto out;
826
aaca4964
JF
827 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
828 handle_percpu_irq, "ipi");
f87e4cac
JF
829
830 bind_ipi.vcpu = cpu;
831 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
832 &bind_ipi) != 0)
833 BUG();
834 evtchn = bind_ipi.port;
835
836 evtchn_to_irq[evtchn] = irq;
ced40d0f 837 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
838 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
839
840 bind_evtchn_to_cpu(evtchn, cpu);
841 }
842
f87e4cac
JF
843 out:
844 spin_unlock(&irq_mapping_update_lock);
845 return irq;
846}
847
848
4fe7d5a7 849int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
850{
851 struct evtchn_bind_virq bind_virq;
852 int evtchn, irq;
853
854 spin_lock(&irq_mapping_update_lock);
855
856 irq = per_cpu(virq_to_irq, cpu)[virq];
857
858 if (irq == -1) {
c9df1ce5 859 irq = xen_allocate_irq_dynamic();
a52521f1
JF
860
861 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
862 handle_percpu_irq, "virq");
863
e46cdb66
JF
864 bind_virq.virq = virq;
865 bind_virq.vcpu = cpu;
866 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
867 &bind_virq) != 0)
868 BUG();
869 evtchn = bind_virq.port;
870
e46cdb66 871 evtchn_to_irq[evtchn] = irq;
ced40d0f 872 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
873
874 per_cpu(virq_to_irq, cpu)[virq] = irq;
875
876 bind_evtchn_to_cpu(evtchn, cpu);
877 }
878
e46cdb66
JF
879 spin_unlock(&irq_mapping_update_lock);
880
881 return irq;
882}
883
884static void unbind_from_irq(unsigned int irq)
885{
886 struct evtchn_close close;
887 int evtchn = evtchn_from_irq(irq);
888
889 spin_lock(&irq_mapping_update_lock);
890
d77bbd4d 891 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
892 close.port = evtchn;
893 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
894 BUG();
895
896 switch (type_from_irq(irq)) {
897 case IRQT_VIRQ:
898 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 899 [virq_from_irq(irq)] = -1;
e46cdb66 900 break;
d68d82af
AN
901 case IRQT_IPI:
902 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 903 [ipi_from_irq(irq)] = -1;
d68d82af 904 break;
e46cdb66
JF
905 default:
906 break;
907 }
908
909 /* Closed ports are implicitly re-bound to VCPU0. */
910 bind_evtchn_to_cpu(evtchn, 0);
911
912 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
913 }
914
915 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 916 irq_info[irq] = mk_unbound_info();
e46cdb66 917
c9df1ce5 918 xen_free_irq(irq);
e46cdb66
JF
919 }
920
921 spin_unlock(&irq_mapping_update_lock);
922}
923
924int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 925 irq_handler_t handler,
e46cdb66
JF
926 unsigned long irqflags,
927 const char *devname, void *dev_id)
928{
929 unsigned int irq;
930 int retval;
931
932 irq = bind_evtchn_to_irq(evtchn);
933 retval = request_irq(irq, handler, irqflags, devname, dev_id);
934 if (retval != 0) {
935 unbind_from_irq(irq);
936 return retval;
937 }
938
939 return irq;
940}
941EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
942
943int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 944 irq_handler_t handler,
e46cdb66
JF
945 unsigned long irqflags, const char *devname, void *dev_id)
946{
947 unsigned int irq;
948 int retval;
949
950 irq = bind_virq_to_irq(virq, cpu);
951 retval = request_irq(irq, handler, irqflags, devname, dev_id);
952 if (retval != 0) {
953 unbind_from_irq(irq);
954 return retval;
955 }
956
957 return irq;
958}
959EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
960
f87e4cac
JF
961int bind_ipi_to_irqhandler(enum ipi_vector ipi,
962 unsigned int cpu,
963 irq_handler_t handler,
964 unsigned long irqflags,
965 const char *devname,
966 void *dev_id)
967{
968 int irq, retval;
969
970 irq = bind_ipi_to_irq(ipi, cpu);
971 if (irq < 0)
972 return irq;
973
4877c737 974 irqflags |= IRQF_NO_SUSPEND;
f87e4cac
JF
975 retval = request_irq(irq, handler, irqflags, devname, dev_id);
976 if (retval != 0) {
977 unbind_from_irq(irq);
978 return retval;
979 }
980
981 return irq;
982}
983
e46cdb66
JF
984void unbind_from_irqhandler(unsigned int irq, void *dev_id)
985{
986 free_irq(irq, dev_id);
987 unbind_from_irq(irq);
988}
989EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
990
f87e4cac
JF
991void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
992{
993 int irq = per_cpu(ipi_to_irq, cpu)[vector];
994 BUG_ON(irq < 0);
995 notify_remote_via_irq(irq);
996}
997
ee523ca1
JF
998irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
999{
1000 struct shared_info *sh = HYPERVISOR_shared_info;
1001 int cpu = smp_processor_id();
cb52e6d9 1002 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
1003 int i;
1004 unsigned long flags;
1005 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1006 struct vcpu_info *v;
ee523ca1
JF
1007
1008 spin_lock_irqsave(&debug_lock, flags);
1009
cb52e6d9 1010 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1011
1012 for_each_online_cpu(i) {
cb52e6d9
IC
1013 int pending;
1014 v = per_cpu(xen_vcpu, i);
1015 pending = (get_irq_regs() && i == cpu)
1016 ? xen_irqs_disabled(get_irq_regs())
1017 : v->evtchn_upcall_mask;
1018 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1019 pending, v->evtchn_upcall_pending,
1020 (int)(sizeof(v->evtchn_pending_sel)*2),
1021 v->evtchn_pending_sel);
1022 }
1023 v = per_cpu(xen_vcpu, cpu);
1024
1025 printk("\npending:\n ");
1026 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1027 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1028 sh->evtchn_pending[i],
1029 i % 8 == 0 ? "\n " : " ");
1030 printk("\nglobal mask:\n ");
1031 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1032 printk("%0*lx%s",
1033 (int)(sizeof(sh->evtchn_mask[0])*2),
1034 sh->evtchn_mask[i],
1035 i % 8 == 0 ? "\n " : " ");
1036
1037 printk("\nglobally unmasked:\n ");
1038 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1039 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1040 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1041 i % 8 == 0 ? "\n " : " ");
1042
1043 printk("\nlocal cpu%d mask:\n ", cpu);
1044 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1045 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1046 cpu_evtchn[i],
1047 i % 8 == 0 ? "\n " : " ");
1048
1049 printk("\nlocally unmasked:\n ");
1050 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1051 unsigned long pending = sh->evtchn_pending[i]
1052 & ~sh->evtchn_mask[i]
1053 & cpu_evtchn[i];
1054 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1055 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1056 }
ee523ca1
JF
1057
1058 printk("\npending list:\n");
cb52e6d9 1059 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1060 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1061 int word_idx = i / BITS_PER_LONG;
1062 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1063 cpu_from_evtchn(i), i,
cb52e6d9
IC
1064 evtchn_to_irq[i],
1065 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1066 ? "" : " l2-clear",
1067 !sync_test_bit(i, sh->evtchn_mask)
1068 ? "" : " globally-masked",
1069 sync_test_bit(i, cpu_evtchn)
1070 ? "" : " locally-masked");
ee523ca1
JF
1071 }
1072 }
1073
1074 spin_unlock_irqrestore(&debug_lock, flags);
1075
1076 return IRQ_HANDLED;
1077}
1078
245b2e70
TH
1079static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1080
e46cdb66
JF
1081/*
1082 * Search the CPUs pending events bitmasks. For each one found, map
1083 * the event number to an irq, and feed it into do_IRQ() for
1084 * handling.
1085 *
1086 * Xen uses a two-level bitmap to speed searching. The first level is
1087 * a bitset of words which contain pending event bits. The second
1088 * level is a bitset of pending events themselves.
1089 */
38e20b07 1090static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1091{
1092 int cpu = get_cpu();
1093 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1094 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1095 unsigned count;
e46cdb66 1096
229664be
JF
1097 do {
1098 unsigned long pending_words;
e46cdb66 1099
229664be 1100 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1101
b2e4ae69 1102 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1103 goto out;
e46cdb66 1104
e849c3e9
IY
1105#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1106 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1107 wmb();
e849c3e9 1108#endif
229664be
JF
1109 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1110 while (pending_words != 0) {
1111 unsigned long pending_bits;
1112 int word_idx = __ffs(pending_words);
1113 pending_words &= ~(1UL << word_idx);
1114
1115 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1116 int bit_idx = __ffs(pending_bits);
1117 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1118 int irq = evtchn_to_irq[port];
ca4dbc66 1119 struct irq_desc *desc;
229664be 1120
3588fe2e
JF
1121 mask_evtchn(port);
1122 clear_evtchn(port);
1123
ca4dbc66
EB
1124 if (irq != -1) {
1125 desc = irq_to_desc(irq);
1126 if (desc)
1127 generic_handle_irq_desc(irq, desc);
1128 }
e46cdb66
JF
1129 }
1130 }
e46cdb66 1131
229664be
JF
1132 BUG_ON(!irqs_disabled());
1133
780f36d8
CL
1134 count = __this_cpu_read(xed_nesting_count);
1135 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1136 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1137
1138out:
38e20b07
SY
1139
1140 put_cpu();
1141}
1142
1143void xen_evtchn_do_upcall(struct pt_regs *regs)
1144{
1145 struct pt_regs *old_regs = set_irq_regs(regs);
1146
1147 exit_idle();
1148 irq_enter();
1149
1150 __xen_evtchn_do_upcall();
1151
3445a8fd
JF
1152 irq_exit();
1153 set_irq_regs(old_regs);
38e20b07 1154}
3445a8fd 1155
38e20b07
SY
1156void xen_hvm_evtchn_do_upcall(void)
1157{
1158 __xen_evtchn_do_upcall();
e46cdb66 1159}
183d03cc 1160EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1161
eb1e305f
JF
1162/* Rebind a new event channel to an existing irq. */
1163void rebind_evtchn_irq(int evtchn, int irq)
1164{
d77bbd4d
JF
1165 struct irq_info *info = info_for_irq(irq);
1166
eb1e305f
JF
1167 /* Make sure the irq is masked, since the new event channel
1168 will also be masked. */
1169 disable_irq(irq);
1170
1171 spin_lock(&irq_mapping_update_lock);
1172
1173 /* After resume the irq<->evtchn mappings are all cleared out */
1174 BUG_ON(evtchn_to_irq[evtchn] != -1);
1175 /* Expect irq to have been bound before,
d77bbd4d
JF
1176 so there should be a proper type */
1177 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1178
1179 evtchn_to_irq[evtchn] = irq;
ced40d0f 1180 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1181
1182 spin_unlock(&irq_mapping_update_lock);
1183
1184 /* new event channels are always bound to cpu 0 */
0de26520 1185 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1186
1187 /* Unmask the event channel. */
1188 enable_irq(irq);
1189}
1190
e46cdb66 1191/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1192static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1193{
1194 struct evtchn_bind_vcpu bind_vcpu;
1195 int evtchn = evtchn_from_irq(irq);
1196
183d03cc
SS
1197 /* events delivered via platform PCI interrupts are always
1198 * routed to vcpu 0 */
1199 if (!VALID_EVTCHN(evtchn) ||
1200 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1201 return -1;
e46cdb66
JF
1202
1203 /* Send future instances of this interrupt to other vcpu. */
1204 bind_vcpu.port = evtchn;
1205 bind_vcpu.vcpu = tcpu;
1206
1207 /*
1208 * If this fails, it usually just indicates that we're dealing with a
1209 * virq or IPI channel, which don't actually need to be rebound. Ignore
1210 * it, but don't do the xenlinux-level rebind in that case.
1211 */
1212 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1213 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1214
d5dedd45
YL
1215 return 0;
1216}
e46cdb66 1217
d5dedd45 1218static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
e46cdb66 1219{
0de26520 1220 unsigned tcpu = cpumask_first(dest);
d5dedd45
YL
1221
1222 return rebind_irq_to_cpu(irq, tcpu);
e46cdb66
JF
1223}
1224
642e0c88
IY
1225int resend_irq_on_evtchn(unsigned int irq)
1226{
1227 int masked, evtchn = evtchn_from_irq(irq);
1228 struct shared_info *s = HYPERVISOR_shared_info;
1229
1230 if (!VALID_EVTCHN(evtchn))
1231 return 1;
1232
1233 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1234 sync_set_bit(evtchn, s->evtchn_pending);
1235 if (!masked)
1236 unmask_evtchn(evtchn);
1237
1238 return 1;
1239}
1240
e46cdb66
JF
1241static void enable_dynirq(unsigned int irq)
1242{
1243 int evtchn = evtchn_from_irq(irq);
1244
1245 if (VALID_EVTCHN(evtchn))
1246 unmask_evtchn(evtchn);
1247}
1248
1249static void disable_dynirq(unsigned int irq)
1250{
1251 int evtchn = evtchn_from_irq(irq);
1252
1253 if (VALID_EVTCHN(evtchn))
1254 mask_evtchn(evtchn);
1255}
1256
1257static void ack_dynirq(unsigned int irq)
1258{
1259 int evtchn = evtchn_from_irq(irq);
1260
3588fe2e 1261 move_masked_irq(irq);
e46cdb66
JF
1262
1263 if (VALID_EVTCHN(evtchn))
3588fe2e 1264 unmask_evtchn(evtchn);
e46cdb66
JF
1265}
1266
1267static int retrigger_dynirq(unsigned int irq)
1268{
1269 int evtchn = evtchn_from_irq(irq);
ee8fa1c6 1270 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1271 int ret = 0;
1272
1273 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1274 int masked;
1275
1276 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1277 sync_set_bit(evtchn, sh->evtchn_pending);
1278 if (!masked)
1279 unmask_evtchn(evtchn);
e46cdb66
JF
1280 ret = 1;
1281 }
1282
1283 return ret;
1284}
1285
9a069c33
SS
1286static void restore_cpu_pirqs(void)
1287{
1288 int pirq, rc, irq, gsi;
1289 struct physdev_map_pirq map_irq;
1290
1291 for (pirq = 0; pirq < nr_irqs; pirq++) {
1292 irq = pirq_to_irq[pirq];
1293 if (irq == -1)
1294 continue;
1295
1296 /* save/restore of PT devices doesn't work, so at this point the
1297 * only devices present are GSI based emulated devices */
1298 gsi = gsi_from_irq(irq);
1299 if (!gsi)
1300 continue;
1301
1302 map_irq.domid = DOMID_SELF;
1303 map_irq.type = MAP_PIRQ_TYPE_GSI;
1304 map_irq.index = gsi;
1305 map_irq.pirq = pirq;
1306
1307 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1308 if (rc) {
1309 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1310 gsi, irq, pirq, rc);
1311 irq_info[irq] = mk_unbound_info();
1312 pirq_to_irq[pirq] = -1;
1313 continue;
1314 }
1315
1316 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1317
1318 startup_pirq(irq);
1319 }
1320}
1321
0e91398f
JF
1322static void restore_cpu_virqs(unsigned int cpu)
1323{
1324 struct evtchn_bind_virq bind_virq;
1325 int virq, irq, evtchn;
1326
1327 for (virq = 0; virq < NR_VIRQS; virq++) {
1328 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1329 continue;
1330
ced40d0f 1331 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1332
1333 /* Get a new binding from Xen. */
1334 bind_virq.virq = virq;
1335 bind_virq.vcpu = cpu;
1336 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1337 &bind_virq) != 0)
1338 BUG();
1339 evtchn = bind_virq.port;
1340
1341 /* Record the new mapping. */
1342 evtchn_to_irq[evtchn] = irq;
ced40d0f 1343 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1344 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1345 }
1346}
1347
1348static void restore_cpu_ipis(unsigned int cpu)
1349{
1350 struct evtchn_bind_ipi bind_ipi;
1351 int ipi, irq, evtchn;
1352
1353 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1354 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1355 continue;
1356
ced40d0f 1357 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1358
1359 /* Get a new binding from Xen. */
1360 bind_ipi.vcpu = cpu;
1361 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1362 &bind_ipi) != 0)
1363 BUG();
1364 evtchn = bind_ipi.port;
1365
1366 /* Record the new mapping. */
1367 evtchn_to_irq[evtchn] = irq;
ced40d0f 1368 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1369 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1370 }
1371}
1372
2d9e1e2f
JF
1373/* Clear an irq's pending state, in preparation for polling on it */
1374void xen_clear_irq_pending(int irq)
1375{
1376 int evtchn = evtchn_from_irq(irq);
1377
1378 if (VALID_EVTCHN(evtchn))
1379 clear_evtchn(evtchn);
1380}
d9a8814f 1381EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1382void xen_set_irq_pending(int irq)
1383{
1384 int evtchn = evtchn_from_irq(irq);
1385
1386 if (VALID_EVTCHN(evtchn))
1387 set_evtchn(evtchn);
1388}
1389
1390bool xen_test_irq_pending(int irq)
1391{
1392 int evtchn = evtchn_from_irq(irq);
1393 bool ret = false;
1394
1395 if (VALID_EVTCHN(evtchn))
1396 ret = test_evtchn(evtchn);
1397
1398 return ret;
1399}
1400
d9a8814f
KRW
1401/* Poll waiting for an irq to become pending with timeout. In the usual case,
1402 * the irq will be disabled so it won't deliver an interrupt. */
1403void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1404{
1405 evtchn_port_t evtchn = evtchn_from_irq(irq);
1406
1407 if (VALID_EVTCHN(evtchn)) {
1408 struct sched_poll poll;
1409
1410 poll.nr_ports = 1;
d9a8814f 1411 poll.timeout = timeout;
ff3c5362 1412 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1413
1414 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1415 BUG();
1416 }
1417}
d9a8814f
KRW
1418EXPORT_SYMBOL(xen_poll_irq_timeout);
1419/* Poll waiting for an irq to become pending. In the usual case, the
1420 * irq will be disabled so it won't deliver an interrupt. */
1421void xen_poll_irq(int irq)
1422{
1423 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1424}
2d9e1e2f 1425
0e91398f
JF
1426void xen_irq_resume(void)
1427{
1428 unsigned int cpu, irq, evtchn;
6903591f 1429 struct irq_desc *desc;
0e91398f
JF
1430
1431 init_evtchn_cpu_bindings();
1432
1433 /* New event-channel space is not 'live' yet. */
1434 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1435 mask_evtchn(evtchn);
1436
1437 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1438 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1439 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1440
1441 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1442 evtchn_to_irq[evtchn] = -1;
1443
1444 for_each_possible_cpu(cpu) {
1445 restore_cpu_virqs(cpu);
1446 restore_cpu_ipis(cpu);
1447 }
6903591f
IC
1448
1449 /*
1450 * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
1451 * are not handled by the IRQ core.
1452 */
1453 for_each_irq_desc(irq, desc) {
1454 if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
1455 continue;
1456 if (desc->status & IRQ_DISABLED)
1457 continue;
1458
1459 evtchn = evtchn_from_irq(irq);
1460 if (evtchn == -1)
1461 continue;
1462
1463 unmask_evtchn(evtchn);
1464 }
9a069c33
SS
1465
1466 restore_cpu_pirqs();
0e91398f
JF
1467}
1468
e46cdb66
JF
1469static struct irq_chip xen_dynamic_chip __read_mostly = {
1470 .name = "xen-dyn",
54a353a0
JF
1471
1472 .disable = disable_dynirq,
e46cdb66
JF
1473 .mask = disable_dynirq,
1474 .unmask = enable_dynirq,
54a353a0 1475
3588fe2e 1476 .eoi = ack_dynirq,
e46cdb66
JF
1477 .set_affinity = set_affinity_irq,
1478 .retrigger = retrigger_dynirq,
1479};
1480
d46a78b0
JF
1481static struct irq_chip xen_pirq_chip __read_mostly = {
1482 .name = "xen-pirq",
1483
1484 .startup = startup_pirq,
1485 .shutdown = shutdown_pirq,
1486
1487 .enable = enable_pirq,
1488 .unmask = enable_pirq,
1489
1490 .disable = disable_pirq,
1491 .mask = disable_pirq,
1492
1493 .ack = ack_pirq,
d46a78b0
JF
1494
1495 .set_affinity = set_affinity_irq,
1496
1497 .retrigger = retrigger_dynirq,
1498};
1499
aaca4964
JF
1500static struct irq_chip xen_percpu_chip __read_mostly = {
1501 .name = "xen-percpu",
1502
1503 .disable = disable_dynirq,
1504 .mask = disable_dynirq,
1505 .unmask = enable_dynirq,
1506
1507 .ack = ack_dynirq,
1508};
1509
38e20b07
SY
1510int xen_set_callback_via(uint64_t via)
1511{
1512 struct xen_hvm_param a;
1513 a.domid = DOMID_SELF;
1514 a.index = HVM_PARAM_CALLBACK_IRQ;
1515 a.value = via;
1516 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1517}
1518EXPORT_SYMBOL_GPL(xen_set_callback_via);
1519
ca65f9fc 1520#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1521/* Vector callbacks are better than PCI interrupts to receive event
1522 * channel notifications because we can receive vector callbacks on any
1523 * vcpu and we don't need PCI support or APIC interactions. */
1524void xen_callback_vector(void)
1525{
1526 int rc;
1527 uint64_t callback_via;
1528 if (xen_have_vector_callback) {
1529 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1530 rc = xen_set_callback_via(callback_via);
1531 if (rc) {
1532 printk(KERN_ERR "Request for Xen HVM callback vector"
1533 " failed.\n");
1534 xen_have_vector_callback = 0;
1535 return;
1536 }
1537 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1538 "enabled\n");
1539 /* in the restore case the vector has already been allocated */
1540 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1541 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1542 }
1543}
ca65f9fc
SS
1544#else
1545void xen_callback_vector(void) {}
1546#endif
38e20b07 1547
e46cdb66
JF
1548void __init xen_init_IRQ(void)
1549{
e5fc7345 1550 int i;
c7a3589e 1551
a70c352a
PE
1552 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1553 GFP_KERNEL);
b21ddbf5
JF
1554 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1555
e5fc7345
SS
1556 /* We are using nr_irqs as the maximum number of pirq available but
1557 * that number is actually chosen by Xen and we don't know exactly
1558 * what it is. Be careful choosing high pirq numbers. */
1559 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1560 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1561 pirq_to_irq[i] = -1;
1562
b21ddbf5
JF
1563 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1564 GFP_KERNEL);
1565 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1566 evtchn_to_irq[i] = -1;
e46cdb66
JF
1567
1568 init_evtchn_cpu_bindings();
1569
1570 /* No event channels are 'live' right now. */
1571 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1572 mask_evtchn(i);
1573
38e20b07
SY
1574 if (xen_hvm_domain()) {
1575 xen_callback_vector();
1576 native_init_IRQ();
3942b740
SS
1577 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1578 * __acpi_register_gsi can point at the right function */
1579 pci_xen_hvm_init();
38e20b07
SY
1580 } else {
1581 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1582 if (xen_initial_domain())
1583 xen_setup_pirqs();
38e20b07 1584 }
e46cdb66 1585}