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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
e46cdb66 | 32 | |
38e20b07 | 33 | #include <asm/desc.h> |
e46cdb66 JF |
34 | #include <asm/ptrace.h> |
35 | #include <asm/irq.h> | |
792dc4f6 | 36 | #include <asm/idle.h> |
0794bfc7 | 37 | #include <asm/io_apic.h> |
e46cdb66 JF |
38 | #include <asm/sync_bitops.h> |
39 | #include <asm/xen/hypercall.h> | |
8d1b8753 | 40 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 41 | |
38e20b07 SY |
42 | #include <xen/xen.h> |
43 | #include <xen/hvm.h> | |
e04d0d07 | 44 | #include <xen/xen-ops.h> |
e46cdb66 JF |
45 | #include <xen/events.h> |
46 | #include <xen/interface/xen.h> | |
47 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
48 | #include <xen/interface/hvm/hvm_op.h> |
49 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 50 | |
e46cdb66 JF |
51 | /* |
52 | * This lock protects updates to the following mapping and reference-count | |
53 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
54 | */ | |
55 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
56 | ||
57 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 58 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 59 | |
f87e4cac | 60 | /* IRQ <-> IPI mapping */ |
204fba4a | 61 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 62 | |
ced40d0f JF |
63 | /* Interrupt types. */ |
64 | enum xen_irq_type { | |
d77bbd4d | 65 | IRQT_UNBOUND = 0, |
f87e4cac JF |
66 | IRQT_PIRQ, |
67 | IRQT_VIRQ, | |
68 | IRQT_IPI, | |
69 | IRQT_EVTCHN | |
70 | }; | |
e46cdb66 | 71 | |
ced40d0f JF |
72 | /* |
73 | * Packed IRQ information: | |
74 | * type - enum xen_irq_type | |
75 | * event channel - irq->event channel mapping | |
76 | * cpu - cpu this event channel is bound to | |
77 | * index - type-specific information: | |
78 | * PIRQ - vector, with MSB being "needs EIO" | |
79 | * VIRQ - virq number | |
80 | * IPI - IPI vector | |
81 | * EVTCHN - | |
82 | */ | |
83 | struct irq_info | |
84 | { | |
85 | enum xen_irq_type type; /* type */ | |
86 | unsigned short evtchn; /* event channel */ | |
87 | unsigned short cpu; /* cpu bound */ | |
88 | ||
89 | union { | |
90 | unsigned short virq; | |
91 | enum ipi_vector ipi; | |
92 | struct { | |
93 | unsigned short gsi; | |
d46a78b0 JF |
94 | unsigned char vector; |
95 | unsigned char flags; | |
ced40d0f JF |
96 | } pirq; |
97 | } u; | |
98 | }; | |
d46a78b0 | 99 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 100 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 101 | |
b21ddbf5 | 102 | static struct irq_info *irq_info; |
e46cdb66 | 103 | |
b21ddbf5 | 104 | static int *evtchn_to_irq; |
c7a3589e MT |
105 | struct cpu_evtchn_s { |
106 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
107 | }; | |
3b32f574 JF |
108 | |
109 | static __initdata struct cpu_evtchn_s init_evtchn_mask = { | |
110 | .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul, | |
111 | }; | |
112 | static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask; | |
113 | ||
c7a3589e MT |
114 | static inline unsigned long *cpu_evtchn_mask(int cpu) |
115 | { | |
116 | return cpu_evtchn_mask_p[cpu].bits; | |
117 | } | |
e46cdb66 | 118 | |
e46cdb66 JF |
119 | /* Xen will never allocate port zero for any purpose. */ |
120 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
121 | ||
e46cdb66 | 122 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 123 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 124 | static struct irq_chip xen_pirq_chip; |
e46cdb66 JF |
125 | |
126 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
127 | static struct irq_info mk_unbound_info(void) |
128 | { | |
129 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
130 | } | |
131 | ||
132 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
133 | { | |
90af9514 IC |
134 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn, |
135 | .cpu = 0 }; | |
ced40d0f JF |
136 | } |
137 | ||
138 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 139 | { |
ced40d0f | 140 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
90af9514 | 141 | .cpu = 0, .u.ipi = ipi }; |
ced40d0f JF |
142 | } |
143 | ||
144 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
145 | { | |
146 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
90af9514 | 147 | .cpu = 0, .u.virq = virq }; |
ced40d0f JF |
148 | } |
149 | ||
150 | static struct irq_info mk_pirq_info(unsigned short evtchn, | |
151 | unsigned short gsi, unsigned short vector) | |
152 | { | |
153 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
90af9514 | 154 | .cpu = 0, .u.pirq = { .gsi = gsi, .vector = vector } }; |
e46cdb66 JF |
155 | } |
156 | ||
157 | /* | |
158 | * Accessors for packed IRQ information. | |
159 | */ | |
ced40d0f | 160 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 161 | { |
ced40d0f | 162 | return &irq_info[irq]; |
e46cdb66 JF |
163 | } |
164 | ||
ced40d0f | 165 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 166 | { |
ced40d0f | 167 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
168 | } |
169 | ||
d4c04536 IC |
170 | unsigned irq_from_evtchn(unsigned int evtchn) |
171 | { | |
172 | return evtchn_to_irq[evtchn]; | |
173 | } | |
174 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
175 | ||
ced40d0f | 176 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 177 | { |
ced40d0f JF |
178 | struct irq_info *info = info_for_irq(irq); |
179 | ||
180 | BUG_ON(info == NULL); | |
181 | BUG_ON(info->type != IRQT_IPI); | |
182 | ||
183 | return info->u.ipi; | |
184 | } | |
185 | ||
186 | static unsigned virq_from_irq(unsigned irq) | |
187 | { | |
188 | struct irq_info *info = info_for_irq(irq); | |
189 | ||
190 | BUG_ON(info == NULL); | |
191 | BUG_ON(info->type != IRQT_VIRQ); | |
192 | ||
193 | return info->u.virq; | |
194 | } | |
195 | ||
196 | static unsigned gsi_from_irq(unsigned irq) | |
197 | { | |
198 | struct irq_info *info = info_for_irq(irq); | |
199 | ||
200 | BUG_ON(info == NULL); | |
201 | BUG_ON(info->type != IRQT_PIRQ); | |
202 | ||
203 | return info->u.pirq.gsi; | |
204 | } | |
205 | ||
206 | static unsigned vector_from_irq(unsigned irq) | |
207 | { | |
208 | struct irq_info *info = info_for_irq(irq); | |
209 | ||
210 | BUG_ON(info == NULL); | |
211 | BUG_ON(info->type != IRQT_PIRQ); | |
212 | ||
213 | return info->u.pirq.vector; | |
214 | } | |
215 | ||
216 | static enum xen_irq_type type_from_irq(unsigned irq) | |
217 | { | |
218 | return info_for_irq(irq)->type; | |
219 | } | |
220 | ||
221 | static unsigned cpu_from_irq(unsigned irq) | |
222 | { | |
223 | return info_for_irq(irq)->cpu; | |
224 | } | |
225 | ||
226 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
227 | { | |
228 | int irq = evtchn_to_irq[evtchn]; | |
229 | unsigned ret = 0; | |
230 | ||
231 | if (irq != -1) | |
232 | ret = cpu_from_irq(irq); | |
233 | ||
234 | return ret; | |
e46cdb66 JF |
235 | } |
236 | ||
d46a78b0 JF |
237 | static bool pirq_needs_eoi(unsigned irq) |
238 | { | |
239 | struct irq_info *info = info_for_irq(irq); | |
240 | ||
241 | BUG_ON(info->type != IRQT_PIRQ); | |
242 | ||
243 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
244 | } | |
245 | ||
e46cdb66 JF |
246 | static inline unsigned long active_evtchns(unsigned int cpu, |
247 | struct shared_info *sh, | |
248 | unsigned int idx) | |
249 | { | |
250 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 251 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
252 | ~sh->evtchn_mask[idx]); |
253 | } | |
254 | ||
255 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
256 | { | |
257 | int irq = evtchn_to_irq[chn]; | |
258 | ||
259 | BUG_ON(irq == -1); | |
260 | #ifdef CONFIG_SMP | |
7f7ace0c | 261 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
262 | #endif |
263 | ||
ced40d0f | 264 | __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
c7a3589e | 265 | __set_bit(chn, cpu_evtchn_mask(cpu)); |
e46cdb66 | 266 | |
ced40d0f | 267 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
268 | } |
269 | ||
270 | static void init_evtchn_cpu_bindings(void) | |
271 | { | |
272 | #ifdef CONFIG_SMP | |
10e58084 | 273 | struct irq_desc *desc; |
e46cdb66 | 274 | int i; |
10e58084 | 275 | |
e46cdb66 | 276 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 277 | for_each_irq_desc(i, desc) { |
7f7ace0c | 278 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 279 | } |
e46cdb66 JF |
280 | #endif |
281 | ||
c7a3589e | 282 | memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0))); |
e46cdb66 JF |
283 | } |
284 | ||
e46cdb66 JF |
285 | static inline void clear_evtchn(int port) |
286 | { | |
287 | struct shared_info *s = HYPERVISOR_shared_info; | |
288 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
289 | } | |
290 | ||
291 | static inline void set_evtchn(int port) | |
292 | { | |
293 | struct shared_info *s = HYPERVISOR_shared_info; | |
294 | sync_set_bit(port, &s->evtchn_pending[0]); | |
295 | } | |
296 | ||
168d2f46 JF |
297 | static inline int test_evtchn(int port) |
298 | { | |
299 | struct shared_info *s = HYPERVISOR_shared_info; | |
300 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
301 | } | |
302 | ||
e46cdb66 JF |
303 | |
304 | /** | |
305 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
306 | * @irq: irq of event channel to send event to | |
307 | * | |
308 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
309 | * save/restore. Notifications on a broken connection are silently | |
310 | * dropped. | |
311 | */ | |
312 | void notify_remote_via_irq(int irq) | |
313 | { | |
314 | int evtchn = evtchn_from_irq(irq); | |
315 | ||
316 | if (VALID_EVTCHN(evtchn)) | |
317 | notify_remote_via_evtchn(evtchn); | |
318 | } | |
319 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
320 | ||
321 | static void mask_evtchn(int port) | |
322 | { | |
323 | struct shared_info *s = HYPERVISOR_shared_info; | |
324 | sync_set_bit(port, &s->evtchn_mask[0]); | |
325 | } | |
326 | ||
327 | static void unmask_evtchn(int port) | |
328 | { | |
329 | struct shared_info *s = HYPERVISOR_shared_info; | |
330 | unsigned int cpu = get_cpu(); | |
331 | ||
332 | BUG_ON(!irqs_disabled()); | |
333 | ||
334 | /* Slow path (hypercall) if this is a non-local port. */ | |
335 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
336 | struct evtchn_unmask unmask = { .port = port }; | |
337 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
338 | } else { | |
339 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
340 | ||
341 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
342 | ||
343 | /* | |
344 | * The following is basically the equivalent of | |
345 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
346 | * the interrupt edge' if the channel is masked. | |
347 | */ | |
348 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
349 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
350 | &vcpu_info->evtchn_pending_sel)) | |
351 | vcpu_info->evtchn_upcall_pending = 1; | |
352 | } | |
353 | ||
354 | put_cpu(); | |
355 | } | |
356 | ||
0794bfc7 KRW |
357 | static int get_nr_hw_irqs(void) |
358 | { | |
359 | int ret = 1; | |
360 | ||
361 | #ifdef CONFIG_X86_IO_APIC | |
362 | ret = get_nr_irqs_gsi(); | |
363 | #endif | |
364 | ||
365 | return ret; | |
366 | } | |
367 | ||
e46cdb66 JF |
368 | static int find_unbound_irq(void) |
369 | { | |
77dff1c7 TG |
370 | struct irq_data *data; |
371 | int irq, res; | |
3a69e916 | 372 | int start = get_nr_hw_irqs(); |
e46cdb66 | 373 | |
3a69e916 KRW |
374 | if (start == nr_irqs) |
375 | goto no_irqs; | |
376 | ||
377 | /* nr_irqs is a magic value. Must not use it.*/ | |
378 | for (irq = nr_irqs-1; irq > start; irq--) { | |
77dff1c7 | 379 | data = irq_get_irq_data(irq); |
99ad198c | 380 | /* only 0->15 have init'd desc; handle irq > 16 */ |
77dff1c7 | 381 | if (!data) |
99ad198c | 382 | break; |
77dff1c7 | 383 | if (data->chip == &no_irq_chip) |
99ad198c | 384 | break; |
77dff1c7 | 385 | if (data->chip != &xen_dynamic_chip) |
99ad198c | 386 | continue; |
d77bbd4d | 387 | if (irq_info[irq].type == IRQT_UNBOUND) |
77dff1c7 | 388 | return irq; |
99ad198c | 389 | } |
e46cdb66 | 390 | |
3a69e916 KRW |
391 | if (irq == start) |
392 | goto no_irqs; | |
e46cdb66 | 393 | |
77dff1c7 | 394 | res = irq_alloc_desc_at(irq, 0); |
6f8a0ed4 | 395 | |
77dff1c7 TG |
396 | if (WARN_ON(res != irq)) |
397 | return -1; | |
ced40d0f | 398 | |
e46cdb66 | 399 | return irq; |
3a69e916 KRW |
400 | |
401 | no_irqs: | |
402 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 JF |
403 | } |
404 | ||
d46a78b0 JF |
405 | static bool identity_mapped_irq(unsigned irq) |
406 | { | |
0794bfc7 KRW |
407 | /* identity map all the hardware irqs */ |
408 | return irq < get_nr_hw_irqs(); | |
d46a78b0 JF |
409 | } |
410 | ||
411 | static void pirq_unmask_notify(int irq) | |
412 | { | |
413 | struct physdev_eoi eoi = { .irq = irq }; | |
414 | ||
415 | if (unlikely(pirq_needs_eoi(irq))) { | |
416 | int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
417 | WARN_ON(rc); | |
418 | } | |
419 | } | |
420 | ||
421 | static void pirq_query_unmask(int irq) | |
422 | { | |
423 | struct physdev_irq_status_query irq_status; | |
424 | struct irq_info *info = info_for_irq(irq); | |
425 | ||
426 | BUG_ON(info->type != IRQT_PIRQ); | |
427 | ||
428 | irq_status.irq = irq; | |
429 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) | |
430 | irq_status.flags = 0; | |
431 | ||
432 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
433 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
434 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
435 | } | |
436 | ||
437 | static bool probing_irq(int irq) | |
438 | { | |
439 | struct irq_desc *desc = irq_to_desc(irq); | |
440 | ||
441 | return desc && desc->action == NULL; | |
442 | } | |
443 | ||
444 | static unsigned int startup_pirq(unsigned int irq) | |
445 | { | |
446 | struct evtchn_bind_pirq bind_pirq; | |
447 | struct irq_info *info = info_for_irq(irq); | |
448 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 449 | int rc; |
d46a78b0 JF |
450 | |
451 | BUG_ON(info->type != IRQT_PIRQ); | |
452 | ||
453 | if (VALID_EVTCHN(evtchn)) | |
454 | goto out; | |
455 | ||
456 | bind_pirq.pirq = irq; | |
457 | /* NB. We are happy to share unless we are probing. */ | |
15ebbb82 KRW |
458 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
459 | BIND_PIRQ__WILL_SHARE : 0; | |
460 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
461 | if (rc != 0) { | |
d46a78b0 JF |
462 | if (!probing_irq(irq)) |
463 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
464 | irq); | |
465 | return 0; | |
466 | } | |
467 | evtchn = bind_pirq.port; | |
468 | ||
469 | pirq_query_unmask(irq); | |
470 | ||
471 | evtchn_to_irq[evtchn] = irq; | |
472 | bind_evtchn_to_cpu(evtchn, 0); | |
473 | info->evtchn = evtchn; | |
474 | ||
475 | out: | |
476 | unmask_evtchn(evtchn); | |
477 | pirq_unmask_notify(irq); | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
482 | static void shutdown_pirq(unsigned int irq) | |
483 | { | |
484 | struct evtchn_close close; | |
485 | struct irq_info *info = info_for_irq(irq); | |
486 | int evtchn = evtchn_from_irq(irq); | |
487 | ||
488 | BUG_ON(info->type != IRQT_PIRQ); | |
489 | ||
490 | if (!VALID_EVTCHN(evtchn)) | |
491 | return; | |
492 | ||
493 | mask_evtchn(evtchn); | |
494 | ||
495 | close.port = evtchn; | |
496 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
497 | BUG(); | |
498 | ||
499 | bind_evtchn_to_cpu(evtchn, 0); | |
500 | evtchn_to_irq[evtchn] = -1; | |
501 | info->evtchn = 0; | |
502 | } | |
503 | ||
504 | static void enable_pirq(unsigned int irq) | |
505 | { | |
506 | startup_pirq(irq); | |
507 | } | |
508 | ||
509 | static void disable_pirq(unsigned int irq) | |
510 | { | |
511 | } | |
512 | ||
513 | static void ack_pirq(unsigned int irq) | |
514 | { | |
515 | int evtchn = evtchn_from_irq(irq); | |
516 | ||
517 | move_native_irq(irq); | |
518 | ||
519 | if (VALID_EVTCHN(evtchn)) { | |
520 | mask_evtchn(evtchn); | |
521 | clear_evtchn(evtchn); | |
522 | } | |
523 | } | |
524 | ||
525 | static void end_pirq(unsigned int irq) | |
526 | { | |
527 | int evtchn = evtchn_from_irq(irq); | |
528 | struct irq_desc *desc = irq_to_desc(irq); | |
529 | ||
530 | if (WARN_ON(!desc)) | |
531 | return; | |
532 | ||
533 | if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) == | |
534 | (IRQ_DISABLED|IRQ_PENDING)) { | |
535 | shutdown_pirq(irq); | |
536 | } else if (VALID_EVTCHN(evtchn)) { | |
537 | unmask_evtchn(evtchn); | |
538 | pirq_unmask_notify(irq); | |
539 | } | |
540 | } | |
541 | ||
542 | static int find_irq_by_gsi(unsigned gsi) | |
543 | { | |
544 | int irq; | |
545 | ||
b21ddbf5 | 546 | for (irq = 0; irq < nr_irqs; irq++) { |
d46a78b0 JF |
547 | struct irq_info *info = info_for_irq(irq); |
548 | ||
549 | if (info == NULL || info->type != IRQT_PIRQ) | |
550 | continue; | |
551 | ||
552 | if (gsi_from_irq(irq) == gsi) | |
553 | return irq; | |
554 | } | |
555 | ||
556 | return -1; | |
557 | } | |
558 | ||
3a69e916 KRW |
559 | /* xen_allocate_irq might allocate irqs from the top down, as a |
560 | * consequence don't assume that the irq number returned has a low value | |
561 | * or can be used as a pirq number unless you know otherwise. | |
562 | * | |
563 | * One notable exception is when xen_allocate_irq is called passing an | |
564 | * hardware gsi as argument, in that case the irq number returned | |
565 | * matches the gsi number passed as first argument. | |
566 | ||
567 | * Note: We don't assign an | |
d46a78b0 JF |
568 | * event channel until the irq actually started up. Return an |
569 | * existing irq if we've already got one for the gsi. | |
570 | */ | |
15ebbb82 | 571 | int xen_allocate_pirq(unsigned gsi, int shareable, char *name) |
d46a78b0 JF |
572 | { |
573 | int irq; | |
574 | struct physdev_irq irq_op; | |
575 | ||
576 | spin_lock(&irq_mapping_update_lock); | |
577 | ||
578 | irq = find_irq_by_gsi(gsi); | |
579 | if (irq != -1) { | |
580 | printk(KERN_INFO "xen_allocate_pirq: returning irq %d for gsi %u\n", | |
581 | irq, gsi); | |
582 | goto out; /* XXX need refcount? */ | |
583 | } | |
584 | ||
585 | if (identity_mapped_irq(gsi)) { | |
586 | irq = gsi; | |
0794bfc7 | 587 | irq_to_desc_alloc_node(irq, 0); |
d46a78b0 JF |
588 | dynamic_irq_init(irq); |
589 | } else | |
590 | irq = find_unbound_irq(); | |
591 | ||
592 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
1a60d05f | 593 | handle_level_irq, name); |
d46a78b0 JF |
594 | |
595 | irq_op.irq = irq; | |
596 | if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
597 | dynamic_irq_cleanup(irq); | |
598 | irq = -ENOSPC; | |
599 | goto out; | |
600 | } | |
601 | ||
602 | irq_info[irq] = mk_pirq_info(0, gsi, irq_op.vector); | |
15ebbb82 | 603 | irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0; |
d46a78b0 JF |
604 | |
605 | out: | |
606 | spin_unlock(&irq_mapping_update_lock); | |
607 | ||
608 | return irq; | |
609 | } | |
610 | ||
611 | int xen_vector_from_irq(unsigned irq) | |
612 | { | |
613 | return vector_from_irq(irq); | |
614 | } | |
615 | ||
616 | int xen_gsi_from_irq(unsigned irq) | |
617 | { | |
618 | return gsi_from_irq(irq); | |
619 | } | |
620 | ||
b536b4b9 | 621 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
622 | { |
623 | int irq; | |
624 | ||
625 | spin_lock(&irq_mapping_update_lock); | |
626 | ||
627 | irq = evtchn_to_irq[evtchn]; | |
628 | ||
629 | if (irq == -1) { | |
630 | irq = find_unbound_irq(); | |
631 | ||
e46cdb66 | 632 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
dffe2e1e | 633 | handle_edge_irq, "event"); |
e46cdb66 JF |
634 | |
635 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 636 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
637 | } |
638 | ||
e46cdb66 JF |
639 | spin_unlock(&irq_mapping_update_lock); |
640 | ||
641 | return irq; | |
642 | } | |
b536b4b9 | 643 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 644 | |
f87e4cac JF |
645 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
646 | { | |
647 | struct evtchn_bind_ipi bind_ipi; | |
648 | int evtchn, irq; | |
649 | ||
650 | spin_lock(&irq_mapping_update_lock); | |
651 | ||
652 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 653 | |
f87e4cac JF |
654 | if (irq == -1) { |
655 | irq = find_unbound_irq(); | |
656 | if (irq < 0) | |
657 | goto out; | |
658 | ||
aaca4964 JF |
659 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
660 | handle_percpu_irq, "ipi"); | |
f87e4cac JF |
661 | |
662 | bind_ipi.vcpu = cpu; | |
663 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
664 | &bind_ipi) != 0) | |
665 | BUG(); | |
666 | evtchn = bind_ipi.port; | |
667 | ||
668 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 669 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
670 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
671 | ||
672 | bind_evtchn_to_cpu(evtchn, cpu); | |
673 | } | |
674 | ||
f87e4cac JF |
675 | out: |
676 | spin_unlock(&irq_mapping_update_lock); | |
677 | return irq; | |
678 | } | |
679 | ||
680 | ||
e46cdb66 JF |
681 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
682 | { | |
683 | struct evtchn_bind_virq bind_virq; | |
684 | int evtchn, irq; | |
685 | ||
686 | spin_lock(&irq_mapping_update_lock); | |
687 | ||
688 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
689 | ||
690 | if (irq == -1) { | |
691 | bind_virq.virq = virq; | |
692 | bind_virq.vcpu = cpu; | |
693 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
694 | &bind_virq) != 0) | |
695 | BUG(); | |
696 | evtchn = bind_virq.port; | |
697 | ||
698 | irq = find_unbound_irq(); | |
699 | ||
aaca4964 JF |
700 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
701 | handle_percpu_irq, "virq"); | |
e46cdb66 JF |
702 | |
703 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 704 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
705 | |
706 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
707 | ||
708 | bind_evtchn_to_cpu(evtchn, cpu); | |
709 | } | |
710 | ||
e46cdb66 JF |
711 | spin_unlock(&irq_mapping_update_lock); |
712 | ||
713 | return irq; | |
714 | } | |
715 | ||
716 | static void unbind_from_irq(unsigned int irq) | |
717 | { | |
718 | struct evtchn_close close; | |
719 | int evtchn = evtchn_from_irq(irq); | |
720 | ||
721 | spin_lock(&irq_mapping_update_lock); | |
722 | ||
d77bbd4d | 723 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
724 | close.port = evtchn; |
725 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
726 | BUG(); | |
727 | ||
728 | switch (type_from_irq(irq)) { | |
729 | case IRQT_VIRQ: | |
730 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 731 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 732 | break; |
d68d82af AN |
733 | case IRQT_IPI: |
734 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 735 | [ipi_from_irq(irq)] = -1; |
d68d82af | 736 | break; |
e46cdb66 JF |
737 | default: |
738 | break; | |
739 | } | |
740 | ||
741 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
742 | bind_evtchn_to_cpu(evtchn, 0); | |
743 | ||
744 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
745 | } |
746 | ||
747 | if (irq_info[irq].type != IRQT_UNBOUND) { | |
ced40d0f | 748 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 749 | |
77dff1c7 | 750 | irq_free_desc(irq); |
e46cdb66 JF |
751 | } |
752 | ||
753 | spin_unlock(&irq_mapping_update_lock); | |
754 | } | |
755 | ||
756 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 757 | irq_handler_t handler, |
e46cdb66 JF |
758 | unsigned long irqflags, |
759 | const char *devname, void *dev_id) | |
760 | { | |
761 | unsigned int irq; | |
762 | int retval; | |
763 | ||
764 | irq = bind_evtchn_to_irq(evtchn); | |
765 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
766 | if (retval != 0) { | |
767 | unbind_from_irq(irq); | |
768 | return retval; | |
769 | } | |
770 | ||
771 | return irq; | |
772 | } | |
773 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
774 | ||
775 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 776 | irq_handler_t handler, |
e46cdb66 JF |
777 | unsigned long irqflags, const char *devname, void *dev_id) |
778 | { | |
779 | unsigned int irq; | |
780 | int retval; | |
781 | ||
782 | irq = bind_virq_to_irq(virq, cpu); | |
783 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
784 | if (retval != 0) { | |
785 | unbind_from_irq(irq); | |
786 | return retval; | |
787 | } | |
788 | ||
789 | return irq; | |
790 | } | |
791 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
792 | ||
f87e4cac JF |
793 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
794 | unsigned int cpu, | |
795 | irq_handler_t handler, | |
796 | unsigned long irqflags, | |
797 | const char *devname, | |
798 | void *dev_id) | |
799 | { | |
800 | int irq, retval; | |
801 | ||
802 | irq = bind_ipi_to_irq(ipi, cpu); | |
803 | if (irq < 0) | |
804 | return irq; | |
805 | ||
4877c737 | 806 | irqflags |= IRQF_NO_SUSPEND; |
f87e4cac JF |
807 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
808 | if (retval != 0) { | |
809 | unbind_from_irq(irq); | |
810 | return retval; | |
811 | } | |
812 | ||
813 | return irq; | |
814 | } | |
815 | ||
e46cdb66 JF |
816 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
817 | { | |
818 | free_irq(irq, dev_id); | |
819 | unbind_from_irq(irq); | |
820 | } | |
821 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
822 | ||
f87e4cac JF |
823 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
824 | { | |
825 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
826 | BUG_ON(irq < 0); | |
827 | notify_remote_via_irq(irq); | |
828 | } | |
829 | ||
ee523ca1 JF |
830 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
831 | { | |
832 | struct shared_info *sh = HYPERVISOR_shared_info; | |
833 | int cpu = smp_processor_id(); | |
834 | int i; | |
835 | unsigned long flags; | |
836 | static DEFINE_SPINLOCK(debug_lock); | |
837 | ||
838 | spin_lock_irqsave(&debug_lock, flags); | |
839 | ||
840 | printk("vcpu %d\n ", cpu); | |
841 | ||
842 | for_each_online_cpu(i) { | |
843 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
844 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 845 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
846 | v->evtchn_upcall_pending, |
847 | v->evtchn_pending_sel); | |
848 | } | |
849 | printk("pending:\n "); | |
850 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
851 | printk("%08lx%s", sh->evtchn_pending[i], | |
852 | i % 8 == 0 ? "\n " : " "); | |
853 | printk("\nmasks:\n "); | |
854 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
855 | printk("%08lx%s", sh->evtchn_mask[i], | |
856 | i % 8 == 0 ? "\n " : " "); | |
857 | ||
858 | printk("\nunmasked:\n "); | |
859 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
860 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
861 | i % 8 == 0 ? "\n " : " "); | |
862 | ||
863 | printk("\npending list:\n"); | |
864 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
865 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
866 | printk(" %d: event %d -> irq %d\n", | |
ced40d0f JF |
867 | cpu_from_evtchn(i), i, |
868 | evtchn_to_irq[i]); | |
ee523ca1 JF |
869 | } |
870 | } | |
871 | ||
872 | spin_unlock_irqrestore(&debug_lock, flags); | |
873 | ||
874 | return IRQ_HANDLED; | |
875 | } | |
876 | ||
245b2e70 TH |
877 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
878 | ||
e46cdb66 JF |
879 | /* |
880 | * Search the CPUs pending events bitmasks. For each one found, map | |
881 | * the event number to an irq, and feed it into do_IRQ() for | |
882 | * handling. | |
883 | * | |
884 | * Xen uses a two-level bitmap to speed searching. The first level is | |
885 | * a bitset of words which contain pending event bits. The second | |
886 | * level is a bitset of pending events themselves. | |
887 | */ | |
38e20b07 | 888 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
889 | { |
890 | int cpu = get_cpu(); | |
891 | struct shared_info *s = HYPERVISOR_shared_info; | |
892 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be | 893 | unsigned count; |
e46cdb66 | 894 | |
229664be JF |
895 | do { |
896 | unsigned long pending_words; | |
e46cdb66 | 897 | |
229664be | 898 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 899 | |
245b2e70 | 900 | if (__get_cpu_var(xed_nesting_count)++) |
229664be | 901 | goto out; |
e46cdb66 | 902 | |
e849c3e9 IY |
903 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
904 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 905 | wmb(); |
e849c3e9 | 906 | #endif |
229664be JF |
907 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
908 | while (pending_words != 0) { | |
909 | unsigned long pending_bits; | |
910 | int word_idx = __ffs(pending_words); | |
911 | pending_words &= ~(1UL << word_idx); | |
912 | ||
913 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
914 | int bit_idx = __ffs(pending_bits); | |
915 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
916 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 917 | struct irq_desc *desc; |
229664be | 918 | |
ca4dbc66 EB |
919 | if (irq != -1) { |
920 | desc = irq_to_desc(irq); | |
921 | if (desc) | |
922 | generic_handle_irq_desc(irq, desc); | |
923 | } | |
e46cdb66 JF |
924 | } |
925 | } | |
e46cdb66 | 926 | |
229664be JF |
927 | BUG_ON(!irqs_disabled()); |
928 | ||
245b2e70 TH |
929 | count = __get_cpu_var(xed_nesting_count); |
930 | __get_cpu_var(xed_nesting_count) = 0; | |
183d03cc | 931 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
932 | |
933 | out: | |
38e20b07 SY |
934 | |
935 | put_cpu(); | |
936 | } | |
937 | ||
938 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
939 | { | |
940 | struct pt_regs *old_regs = set_irq_regs(regs); | |
941 | ||
942 | exit_idle(); | |
943 | irq_enter(); | |
944 | ||
945 | __xen_evtchn_do_upcall(); | |
946 | ||
3445a8fd JF |
947 | irq_exit(); |
948 | set_irq_regs(old_regs); | |
38e20b07 | 949 | } |
3445a8fd | 950 | |
38e20b07 SY |
951 | void xen_hvm_evtchn_do_upcall(void) |
952 | { | |
953 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 954 | } |
183d03cc | 955 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 956 | |
eb1e305f JF |
957 | /* Rebind a new event channel to an existing irq. */ |
958 | void rebind_evtchn_irq(int evtchn, int irq) | |
959 | { | |
d77bbd4d JF |
960 | struct irq_info *info = info_for_irq(irq); |
961 | ||
eb1e305f JF |
962 | /* Make sure the irq is masked, since the new event channel |
963 | will also be masked. */ | |
964 | disable_irq(irq); | |
965 | ||
966 | spin_lock(&irq_mapping_update_lock); | |
967 | ||
968 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
969 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
970 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
971 | so there should be a proper type */ |
972 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
973 | |
974 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 975 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
976 | |
977 | spin_unlock(&irq_mapping_update_lock); | |
978 | ||
979 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 980 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
981 | |
982 | /* Unmask the event channel. */ | |
983 | enable_irq(irq); | |
984 | } | |
985 | ||
e46cdb66 | 986 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 987 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
988 | { |
989 | struct evtchn_bind_vcpu bind_vcpu; | |
990 | int evtchn = evtchn_from_irq(irq); | |
991 | ||
183d03cc SS |
992 | /* events delivered via platform PCI interrupts are always |
993 | * routed to vcpu 0 */ | |
994 | if (!VALID_EVTCHN(evtchn) || | |
995 | (xen_hvm_domain() && !xen_have_vector_callback)) | |
d5dedd45 | 996 | return -1; |
e46cdb66 JF |
997 | |
998 | /* Send future instances of this interrupt to other vcpu. */ | |
999 | bind_vcpu.port = evtchn; | |
1000 | bind_vcpu.vcpu = tcpu; | |
1001 | ||
1002 | /* | |
1003 | * If this fails, it usually just indicates that we're dealing with a | |
1004 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1005 | * it, but don't do the xenlinux-level rebind in that case. | |
1006 | */ | |
1007 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1008 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1009 | |
d5dedd45 YL |
1010 | return 0; |
1011 | } | |
e46cdb66 | 1012 | |
d5dedd45 | 1013 | static int set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 1014 | { |
0de26520 | 1015 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 YL |
1016 | |
1017 | return rebind_irq_to_cpu(irq, tcpu); | |
e46cdb66 JF |
1018 | } |
1019 | ||
642e0c88 IY |
1020 | int resend_irq_on_evtchn(unsigned int irq) |
1021 | { | |
1022 | int masked, evtchn = evtchn_from_irq(irq); | |
1023 | struct shared_info *s = HYPERVISOR_shared_info; | |
1024 | ||
1025 | if (!VALID_EVTCHN(evtchn)) | |
1026 | return 1; | |
1027 | ||
1028 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1029 | sync_set_bit(evtchn, s->evtchn_pending); | |
1030 | if (!masked) | |
1031 | unmask_evtchn(evtchn); | |
1032 | ||
1033 | return 1; | |
1034 | } | |
1035 | ||
e46cdb66 JF |
1036 | static void enable_dynirq(unsigned int irq) |
1037 | { | |
1038 | int evtchn = evtchn_from_irq(irq); | |
1039 | ||
1040 | if (VALID_EVTCHN(evtchn)) | |
1041 | unmask_evtchn(evtchn); | |
1042 | } | |
1043 | ||
1044 | static void disable_dynirq(unsigned int irq) | |
1045 | { | |
1046 | int evtchn = evtchn_from_irq(irq); | |
1047 | ||
1048 | if (VALID_EVTCHN(evtchn)) | |
1049 | mask_evtchn(evtchn); | |
1050 | } | |
1051 | ||
1052 | static void ack_dynirq(unsigned int irq) | |
1053 | { | |
1054 | int evtchn = evtchn_from_irq(irq); | |
1055 | ||
1056 | move_native_irq(irq); | |
1057 | ||
1058 | if (VALID_EVTCHN(evtchn)) | |
1059 | clear_evtchn(evtchn); | |
1060 | } | |
1061 | ||
1062 | static int retrigger_dynirq(unsigned int irq) | |
1063 | { | |
1064 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 1065 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1066 | int ret = 0; |
1067 | ||
1068 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1069 | int masked; |
1070 | ||
1071 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1072 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1073 | if (!masked) | |
1074 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1075 | ret = 1; |
1076 | } | |
1077 | ||
1078 | return ret; | |
1079 | } | |
1080 | ||
0e91398f JF |
1081 | static void restore_cpu_virqs(unsigned int cpu) |
1082 | { | |
1083 | struct evtchn_bind_virq bind_virq; | |
1084 | int virq, irq, evtchn; | |
1085 | ||
1086 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1087 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1088 | continue; | |
1089 | ||
ced40d0f | 1090 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1091 | |
1092 | /* Get a new binding from Xen. */ | |
1093 | bind_virq.virq = virq; | |
1094 | bind_virq.vcpu = cpu; | |
1095 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1096 | &bind_virq) != 0) | |
1097 | BUG(); | |
1098 | evtchn = bind_virq.port; | |
1099 | ||
1100 | /* Record the new mapping. */ | |
1101 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1102 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f JF |
1103 | bind_evtchn_to_cpu(evtchn, cpu); |
1104 | ||
1105 | /* Ready for use. */ | |
1106 | unmask_evtchn(evtchn); | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | static void restore_cpu_ipis(unsigned int cpu) | |
1111 | { | |
1112 | struct evtchn_bind_ipi bind_ipi; | |
1113 | int ipi, irq, evtchn; | |
1114 | ||
1115 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1116 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1117 | continue; | |
1118 | ||
ced40d0f | 1119 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1120 | |
1121 | /* Get a new binding from Xen. */ | |
1122 | bind_ipi.vcpu = cpu; | |
1123 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1124 | &bind_ipi) != 0) | |
1125 | BUG(); | |
1126 | evtchn = bind_ipi.port; | |
1127 | ||
1128 | /* Record the new mapping. */ | |
1129 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1130 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f JF |
1131 | bind_evtchn_to_cpu(evtchn, cpu); |
1132 | ||
1133 | /* Ready for use. */ | |
1134 | unmask_evtchn(evtchn); | |
1135 | ||
1136 | } | |
1137 | } | |
1138 | ||
2d9e1e2f JF |
1139 | /* Clear an irq's pending state, in preparation for polling on it */ |
1140 | void xen_clear_irq_pending(int irq) | |
1141 | { | |
1142 | int evtchn = evtchn_from_irq(irq); | |
1143 | ||
1144 | if (VALID_EVTCHN(evtchn)) | |
1145 | clear_evtchn(evtchn); | |
1146 | } | |
d9a8814f | 1147 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1148 | void xen_set_irq_pending(int irq) |
1149 | { | |
1150 | int evtchn = evtchn_from_irq(irq); | |
1151 | ||
1152 | if (VALID_EVTCHN(evtchn)) | |
1153 | set_evtchn(evtchn); | |
1154 | } | |
1155 | ||
1156 | bool xen_test_irq_pending(int irq) | |
1157 | { | |
1158 | int evtchn = evtchn_from_irq(irq); | |
1159 | bool ret = false; | |
1160 | ||
1161 | if (VALID_EVTCHN(evtchn)) | |
1162 | ret = test_evtchn(evtchn); | |
1163 | ||
1164 | return ret; | |
1165 | } | |
1166 | ||
d9a8814f KRW |
1167 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1168 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1169 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1170 | { |
1171 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1172 | ||
1173 | if (VALID_EVTCHN(evtchn)) { | |
1174 | struct sched_poll poll; | |
1175 | ||
1176 | poll.nr_ports = 1; | |
d9a8814f | 1177 | poll.timeout = timeout; |
ff3c5362 | 1178 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1179 | |
1180 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1181 | BUG(); | |
1182 | } | |
1183 | } | |
d9a8814f KRW |
1184 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1185 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1186 | * irq will be disabled so it won't deliver an interrupt. */ | |
1187 | void xen_poll_irq(int irq) | |
1188 | { | |
1189 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1190 | } | |
2d9e1e2f | 1191 | |
0e91398f JF |
1192 | void xen_irq_resume(void) |
1193 | { | |
1194 | unsigned int cpu, irq, evtchn; | |
1195 | ||
1196 | init_evtchn_cpu_bindings(); | |
1197 | ||
1198 | /* New event-channel space is not 'live' yet. */ | |
1199 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1200 | mask_evtchn(evtchn); | |
1201 | ||
1202 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 1203 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
1204 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
1205 | ||
1206 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1207 | evtchn_to_irq[evtchn] = -1; | |
1208 | ||
1209 | for_each_possible_cpu(cpu) { | |
1210 | restore_cpu_virqs(cpu); | |
1211 | restore_cpu_ipis(cpu); | |
1212 | } | |
1213 | } | |
1214 | ||
e46cdb66 JF |
1215 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
1216 | .name = "xen-dyn", | |
54a353a0 JF |
1217 | |
1218 | .disable = disable_dynirq, | |
e46cdb66 JF |
1219 | .mask = disable_dynirq, |
1220 | .unmask = enable_dynirq, | |
54a353a0 | 1221 | |
e46cdb66 JF |
1222 | .ack = ack_dynirq, |
1223 | .set_affinity = set_affinity_irq, | |
1224 | .retrigger = retrigger_dynirq, | |
1225 | }; | |
1226 | ||
d46a78b0 JF |
1227 | static struct irq_chip xen_pirq_chip __read_mostly = { |
1228 | .name = "xen-pirq", | |
1229 | ||
1230 | .startup = startup_pirq, | |
1231 | .shutdown = shutdown_pirq, | |
1232 | ||
1233 | .enable = enable_pirq, | |
1234 | .unmask = enable_pirq, | |
1235 | ||
1236 | .disable = disable_pirq, | |
1237 | .mask = disable_pirq, | |
1238 | ||
1239 | .ack = ack_pirq, | |
1240 | .end = end_pirq, | |
1241 | ||
1242 | .set_affinity = set_affinity_irq, | |
1243 | ||
1244 | .retrigger = retrigger_dynirq, | |
1245 | }; | |
1246 | ||
aaca4964 JF |
1247 | static struct irq_chip xen_percpu_chip __read_mostly = { |
1248 | .name = "xen-percpu", | |
1249 | ||
1250 | .disable = disable_dynirq, | |
1251 | .mask = disable_dynirq, | |
1252 | .unmask = enable_dynirq, | |
1253 | ||
1254 | .ack = ack_dynirq, | |
1255 | }; | |
1256 | ||
38e20b07 SY |
1257 | int xen_set_callback_via(uint64_t via) |
1258 | { | |
1259 | struct xen_hvm_param a; | |
1260 | a.domid = DOMID_SELF; | |
1261 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1262 | a.value = via; | |
1263 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1264 | } | |
1265 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1266 | ||
ca65f9fc | 1267 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1268 | /* Vector callbacks are better than PCI interrupts to receive event |
1269 | * channel notifications because we can receive vector callbacks on any | |
1270 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1271 | void xen_callback_vector(void) | |
1272 | { | |
1273 | int rc; | |
1274 | uint64_t callback_via; | |
1275 | if (xen_have_vector_callback) { | |
1276 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1277 | rc = xen_set_callback_via(callback_via); | |
1278 | if (rc) { | |
1279 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1280 | " failed.\n"); | |
1281 | xen_have_vector_callback = 0; | |
1282 | return; | |
1283 | } | |
1284 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1285 | "enabled\n"); | |
1286 | /* in the restore case the vector has already been allocated */ | |
1287 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1288 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1289 | } | |
1290 | } | |
ca65f9fc SS |
1291 | #else |
1292 | void xen_callback_vector(void) {} | |
1293 | #endif | |
38e20b07 | 1294 | |
e46cdb66 JF |
1295 | void __init xen_init_IRQ(void) |
1296 | { | |
1297 | int i; | |
c7a3589e | 1298 | |
a70c352a PE |
1299 | cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s), |
1300 | GFP_KERNEL); | |
b21ddbf5 JF |
1301 | irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL); |
1302 | ||
1303 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), | |
1304 | GFP_KERNEL); | |
1305 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1306 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1307 | |
1308 | init_evtchn_cpu_bindings(); | |
1309 | ||
1310 | /* No event channels are 'live' right now. */ | |
1311 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1312 | mask_evtchn(i); | |
1313 | ||
38e20b07 SY |
1314 | if (xen_hvm_domain()) { |
1315 | xen_callback_vector(); | |
1316 | native_init_IRQ(); | |
1317 | } else { | |
1318 | irq_ctx_init(smp_processor_id()); | |
1319 | } | |
e46cdb66 | 1320 | } |