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xen: remap GSIs as pirqs when running as initial domain
[mirror_ubuntu-focal-kernel.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
e46cdb66 32
38e20b07 33#include <asm/desc.h>
e46cdb66
JF
34#include <asm/ptrace.h>
35#include <asm/irq.h>
792dc4f6 36#include <asm/idle.h>
0794bfc7 37#include <asm/io_apic.h>
e46cdb66 38#include <asm/sync_bitops.h>
42a1de56 39#include <asm/xen/pci.h>
e46cdb66 40#include <asm/xen/hypercall.h>
8d1b8753 41#include <asm/xen/hypervisor.h>
e46cdb66 42
38e20b07
SY
43#include <xen/xen.h>
44#include <xen/hvm.h>
e04d0d07 45#include <xen/xen-ops.h>
e46cdb66
JF
46#include <xen/events.h>
47#include <xen/interface/xen.h>
48#include <xen/interface/event_channel.h>
38e20b07
SY
49#include <xen/interface/hvm/hvm_op.h>
50#include <xen/interface/hvm/params.h>
e46cdb66 51
e46cdb66
JF
52/*
53 * This lock protects updates to the following mapping and reference-count
54 * arrays. The lock does not need to be acquired to read the mapping tables.
55 */
56static DEFINE_SPINLOCK(irq_mapping_update_lock);
57
58/* IRQ <-> VIRQ mapping. */
204fba4a 59static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 60
f87e4cac 61/* IRQ <-> IPI mapping */
204fba4a 62static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 63
ced40d0f
JF
64/* Interrupt types. */
65enum xen_irq_type {
d77bbd4d 66 IRQT_UNBOUND = 0,
f87e4cac
JF
67 IRQT_PIRQ,
68 IRQT_VIRQ,
69 IRQT_IPI,
70 IRQT_EVTCHN
71};
e46cdb66 72
ced40d0f
JF
73/*
74 * Packed IRQ information:
75 * type - enum xen_irq_type
76 * event channel - irq->event channel mapping
77 * cpu - cpu this event channel is bound to
78 * index - type-specific information:
42a1de56
SS
79 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
80 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
81 * VIRQ - virq number
82 * IPI - IPI vector
83 * EVTCHN -
84 */
85struct irq_info
86{
87 enum xen_irq_type type; /* type */
88 unsigned short evtchn; /* event channel */
89 unsigned short cpu; /* cpu bound */
90
91 union {
92 unsigned short virq;
93 enum ipi_vector ipi;
94 struct {
7a043f11 95 unsigned short pirq;
ced40d0f 96 unsigned short gsi;
d46a78b0
JF
97 unsigned char vector;
98 unsigned char flags;
ced40d0f
JF
99 } pirq;
100 } u;
101};
d46a78b0 102#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 103#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 104
b21ddbf5 105static struct irq_info *irq_info;
7a043f11 106static int *pirq_to_irq;
01557baf 107static int nr_pirqs;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
ced40d0f 173 return info_for_irq(irq)->evtchn;
e46cdb66
JF
174}
175
d4c04536
IC
176unsigned irq_from_evtchn(unsigned int evtchn)
177{
178 return evtchn_to_irq[evtchn];
179}
180EXPORT_SYMBOL_GPL(irq_from_evtchn);
181
ced40d0f 182static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 183{
ced40d0f
JF
184 struct irq_info *info = info_for_irq(irq);
185
186 BUG_ON(info == NULL);
187 BUG_ON(info->type != IRQT_IPI);
188
189 return info->u.ipi;
190}
191
192static unsigned virq_from_irq(unsigned irq)
193{
194 struct irq_info *info = info_for_irq(irq);
195
196 BUG_ON(info == NULL);
197 BUG_ON(info->type != IRQT_VIRQ);
198
199 return info->u.virq;
200}
201
7a043f11
SS
202static unsigned pirq_from_irq(unsigned irq)
203{
204 struct irq_info *info = info_for_irq(irq);
205
206 BUG_ON(info == NULL);
207 BUG_ON(info->type != IRQT_PIRQ);
208
209 return info->u.pirq.pirq;
210}
211
ced40d0f
JF
212static unsigned gsi_from_irq(unsigned irq)
213{
214 struct irq_info *info = info_for_irq(irq);
215
216 BUG_ON(info == NULL);
217 BUG_ON(info->type != IRQT_PIRQ);
218
219 return info->u.pirq.gsi;
220}
221
222static unsigned vector_from_irq(unsigned irq)
223{
224 struct irq_info *info = info_for_irq(irq);
225
226 BUG_ON(info == NULL);
227 BUG_ON(info->type != IRQT_PIRQ);
228
229 return info->u.pirq.vector;
230}
231
232static enum xen_irq_type type_from_irq(unsigned irq)
233{
234 return info_for_irq(irq)->type;
235}
236
237static unsigned cpu_from_irq(unsigned irq)
238{
239 return info_for_irq(irq)->cpu;
240}
241
242static unsigned int cpu_from_evtchn(unsigned int evtchn)
243{
244 int irq = evtchn_to_irq[evtchn];
245 unsigned ret = 0;
246
247 if (irq != -1)
248 ret = cpu_from_irq(irq);
249
250 return ret;
e46cdb66
JF
251}
252
d46a78b0
JF
253static bool pirq_needs_eoi(unsigned irq)
254{
255 struct irq_info *info = info_for_irq(irq);
256
257 BUG_ON(info->type != IRQT_PIRQ);
258
259 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
260}
261
e46cdb66
JF
262static inline unsigned long active_evtchns(unsigned int cpu,
263 struct shared_info *sh,
264 unsigned int idx)
265{
266 return (sh->evtchn_pending[idx] &
c7a3589e 267 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
268 ~sh->evtchn_mask[idx]);
269}
270
271static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
272{
273 int irq = evtchn_to_irq[chn];
274
275 BUG_ON(irq == -1);
276#ifdef CONFIG_SMP
7f7ace0c 277 cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
e46cdb66
JF
278#endif
279
ced40d0f 280 __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
c7a3589e 281 __set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 282
ced40d0f 283 irq_info[irq].cpu = cpu;
e46cdb66
JF
284}
285
286static void init_evtchn_cpu_bindings(void)
287{
288#ifdef CONFIG_SMP
10e58084 289 struct irq_desc *desc;
e46cdb66 290 int i;
10e58084 291
e46cdb66 292 /* By default all event channels notify CPU#0. */
0b8f1efa 293 for_each_irq_desc(i, desc) {
7f7ace0c 294 cpumask_copy(desc->affinity, cpumask_of(0));
0b8f1efa 295 }
e46cdb66
JF
296#endif
297
c7a3589e 298 memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0)));
e46cdb66
JF
299}
300
e46cdb66
JF
301static inline void clear_evtchn(int port)
302{
303 struct shared_info *s = HYPERVISOR_shared_info;
304 sync_clear_bit(port, &s->evtchn_pending[0]);
305}
306
307static inline void set_evtchn(int port)
308{
309 struct shared_info *s = HYPERVISOR_shared_info;
310 sync_set_bit(port, &s->evtchn_pending[0]);
311}
312
168d2f46
JF
313static inline int test_evtchn(int port)
314{
315 struct shared_info *s = HYPERVISOR_shared_info;
316 return sync_test_bit(port, &s->evtchn_pending[0]);
317}
318
e46cdb66
JF
319
320/**
321 * notify_remote_via_irq - send event to remote end of event channel via irq
322 * @irq: irq of event channel to send event to
323 *
324 * Unlike notify_remote_via_evtchn(), this is safe to use across
325 * save/restore. Notifications on a broken connection are silently
326 * dropped.
327 */
328void notify_remote_via_irq(int irq)
329{
330 int evtchn = evtchn_from_irq(irq);
331
332 if (VALID_EVTCHN(evtchn))
333 notify_remote_via_evtchn(evtchn);
334}
335EXPORT_SYMBOL_GPL(notify_remote_via_irq);
336
337static void mask_evtchn(int port)
338{
339 struct shared_info *s = HYPERVISOR_shared_info;
340 sync_set_bit(port, &s->evtchn_mask[0]);
341}
342
343static void unmask_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
346 unsigned int cpu = get_cpu();
347
348 BUG_ON(!irqs_disabled());
349
350 /* Slow path (hypercall) if this is a non-local port. */
351 if (unlikely(cpu != cpu_from_evtchn(port))) {
352 struct evtchn_unmask unmask = { .port = port };
353 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
354 } else {
355 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
356
357 sync_clear_bit(port, &s->evtchn_mask[0]);
358
359 /*
360 * The following is basically the equivalent of
361 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
362 * the interrupt edge' if the channel is masked.
363 */
364 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
365 !sync_test_and_set_bit(port / BITS_PER_LONG,
366 &vcpu_info->evtchn_pending_sel))
367 vcpu_info->evtchn_upcall_pending = 1;
368 }
369
370 put_cpu();
371}
372
0794bfc7
KRW
373static int get_nr_hw_irqs(void)
374{
375 int ret = 1;
376
377#ifdef CONFIG_X86_IO_APIC
378 ret = get_nr_irqs_gsi();
379#endif
380
381 return ret;
382}
383
01557baf
SS
384/* callers of this function should make sure that PHYSDEVOP_get_nr_pirqs
385 * succeeded otherwise nr_pirqs won't hold the right value */
7a043f11
SS
386static int find_unbound_pirq(void)
387{
388 int i;
01557baf 389 for (i = nr_pirqs-1; i >= 0; i--) {
7a043f11
SS
390 if (pirq_to_irq[i] < 0)
391 return i;
392 }
393 return -1;
394}
395
e46cdb66
JF
396static int find_unbound_irq(void)
397{
77dff1c7
TG
398 struct irq_data *data;
399 int irq, res;
3a69e916 400 int start = get_nr_hw_irqs();
e46cdb66 401
3a69e916
KRW
402 if (start == nr_irqs)
403 goto no_irqs;
404
405 /* nr_irqs is a magic value. Must not use it.*/
406 for (irq = nr_irqs-1; irq > start; irq--) {
77dff1c7 407 data = irq_get_irq_data(irq);
99ad198c 408 /* only 0->15 have init'd desc; handle irq > 16 */
77dff1c7 409 if (!data)
99ad198c 410 break;
77dff1c7 411 if (data->chip == &no_irq_chip)
99ad198c 412 break;
77dff1c7 413 if (data->chip != &xen_dynamic_chip)
99ad198c 414 continue;
d77bbd4d 415 if (irq_info[irq].type == IRQT_UNBOUND)
77dff1c7 416 return irq;
99ad198c 417 }
e46cdb66 418
3a69e916
KRW
419 if (irq == start)
420 goto no_irqs;
e46cdb66 421
77dff1c7 422 res = irq_alloc_desc_at(irq, 0);
6f8a0ed4 423
77dff1c7
TG
424 if (WARN_ON(res != irq))
425 return -1;
ced40d0f 426
e46cdb66 427 return irq;
3a69e916
KRW
428
429no_irqs:
430 panic("No available IRQ to bind to: increase nr_irqs!\n");
e46cdb66
JF
431}
432
d46a78b0
JF
433static bool identity_mapped_irq(unsigned irq)
434{
0794bfc7
KRW
435 /* identity map all the hardware irqs */
436 return irq < get_nr_hw_irqs();
d46a78b0
JF
437}
438
439static void pirq_unmask_notify(int irq)
440{
7a043f11 441 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
442
443 if (unlikely(pirq_needs_eoi(irq))) {
444 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
445 WARN_ON(rc);
446 }
447}
448
449static void pirq_query_unmask(int irq)
450{
451 struct physdev_irq_status_query irq_status;
452 struct irq_info *info = info_for_irq(irq);
453
454 BUG_ON(info->type != IRQT_PIRQ);
455
7a043f11 456 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
457 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
458 irq_status.flags = 0;
459
460 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
461 if (irq_status.flags & XENIRQSTAT_needs_eoi)
462 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
463}
464
465static bool probing_irq(int irq)
466{
467 struct irq_desc *desc = irq_to_desc(irq);
468
469 return desc && desc->action == NULL;
470}
471
472static unsigned int startup_pirq(unsigned int irq)
473{
474 struct evtchn_bind_pirq bind_pirq;
475 struct irq_info *info = info_for_irq(irq);
476 int evtchn = evtchn_from_irq(irq);
15ebbb82 477 int rc;
d46a78b0
JF
478
479 BUG_ON(info->type != IRQT_PIRQ);
480
481 if (VALID_EVTCHN(evtchn))
482 goto out;
483
7a043f11 484 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 485 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
486 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
487 BIND_PIRQ__WILL_SHARE : 0;
488 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
489 if (rc != 0) {
d46a78b0
JF
490 if (!probing_irq(irq))
491 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
492 irq);
493 return 0;
494 }
495 evtchn = bind_pirq.port;
496
497 pirq_query_unmask(irq);
498
499 evtchn_to_irq[evtchn] = irq;
500 bind_evtchn_to_cpu(evtchn, 0);
501 info->evtchn = evtchn;
502
503out:
504 unmask_evtchn(evtchn);
505 pirq_unmask_notify(irq);
506
507 return 0;
508}
509
510static void shutdown_pirq(unsigned int irq)
511{
512 struct evtchn_close close;
513 struct irq_info *info = info_for_irq(irq);
514 int evtchn = evtchn_from_irq(irq);
515
516 BUG_ON(info->type != IRQT_PIRQ);
517
518 if (!VALID_EVTCHN(evtchn))
519 return;
520
521 mask_evtchn(evtchn);
522
523 close.port = evtchn;
524 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
525 BUG();
526
527 bind_evtchn_to_cpu(evtchn, 0);
528 evtchn_to_irq[evtchn] = -1;
529 info->evtchn = 0;
530}
531
532static void enable_pirq(unsigned int irq)
533{
534 startup_pirq(irq);
535}
536
537static void disable_pirq(unsigned int irq)
538{
539}
540
541static void ack_pirq(unsigned int irq)
542{
543 int evtchn = evtchn_from_irq(irq);
544
545 move_native_irq(irq);
546
547 if (VALID_EVTCHN(evtchn)) {
548 mask_evtchn(evtchn);
549 clear_evtchn(evtchn);
550 }
551}
552
553static void end_pirq(unsigned int irq)
554{
555 int evtchn = evtchn_from_irq(irq);
556 struct irq_desc *desc = irq_to_desc(irq);
557
558 if (WARN_ON(!desc))
559 return;
560
561 if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) ==
562 (IRQ_DISABLED|IRQ_PENDING)) {
563 shutdown_pirq(irq);
564 } else if (VALID_EVTCHN(evtchn)) {
565 unmask_evtchn(evtchn);
566 pirq_unmask_notify(irq);
567 }
568}
569
570static int find_irq_by_gsi(unsigned gsi)
571{
572 int irq;
573
b21ddbf5 574 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
575 struct irq_info *info = info_for_irq(irq);
576
577 if (info == NULL || info->type != IRQT_PIRQ)
578 continue;
579
580 if (gsi_from_irq(irq) == gsi)
581 return irq;
582 }
583
584 return -1;
585}
586
7a043f11
SS
587int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
588{
589 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
590}
591
592/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
593 * consequence don't assume that the irq number returned has a low value
594 * or can be used as a pirq number unless you know otherwise.
595 *
7a043f11 596 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 597 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
598 * matches the gsi number passed as second argument.
599 *
600 * Note: We don't assign an event channel until the irq actually started
601 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 602 */
7a043f11 603int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 604{
7a043f11 605 int irq = 0;
d46a78b0
JF
606 struct physdev_irq irq_op;
607
608 spin_lock(&irq_mapping_update_lock);
609
01557baf
SS
610 if ((pirq > nr_pirqs) || (gsi > nr_irqs)) {
611 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
612 pirq > nr_pirqs ? "nr_pirqs" :"",
613 gsi > nr_irqs ? "nr_irqs" : "");
614 goto out;
615 }
616
d46a78b0
JF
617 irq = find_irq_by_gsi(gsi);
618 if (irq != -1) {
7a043f11 619 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
620 irq, gsi);
621 goto out; /* XXX need refcount? */
622 }
623
b5401a96
AN
624 /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore
625 * we are using the !xen_initial_domain() to drop in the function.*/
3942b740
SS
626 if (identity_mapped_irq(gsi) || (!xen_initial_domain() &&
627 xen_pv_domain())) {
d46a78b0 628 irq = gsi;
2c52f8d3 629 irq_alloc_desc_at(irq, 0);
d46a78b0
JF
630 } else
631 irq = find_unbound_irq();
632
633 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 634 handle_level_irq, name);
d46a78b0
JF
635
636 irq_op.irq = irq;
b5401a96
AN
637 irq_op.vector = 0;
638
639 /* Only the privileged domain can do this. For non-priv, the pcifront
640 * driver provides a PCI bus that does the call to do exactly
641 * this in the priv domain. */
642 if (xen_initial_domain() &&
643 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
2c52f8d3 644 irq_free_desc(irq);
d46a78b0
JF
645 irq = -ENOSPC;
646 goto out;
647 }
648
7a043f11 649 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 650 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 651 pirq_to_irq[pirq] = irq;
d46a78b0
JF
652
653out:
654 spin_unlock(&irq_mapping_update_lock);
655
656 return irq;
657}
658
809f9267
SS
659void xen_allocate_pirq_msi(char *name, int *irq, int *pirq)
660{
661 spin_lock(&irq_mapping_update_lock);
662
663 *irq = find_unbound_irq();
664 if (*irq == -1)
665 goto out;
666
667 *pirq = find_unbound_pirq();
668 if (*pirq == -1)
669 goto out;
670
671 set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
672 handle_level_irq, name);
673
674 irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
675 pirq_to_irq[*pirq] = *irq;
676
677out:
678 spin_unlock(&irq_mapping_update_lock);
679}
680
b5401a96
AN
681int xen_destroy_irq(int irq)
682{
683 struct irq_desc *desc;
38aa66fc
JF
684 struct physdev_unmap_pirq unmap_irq;
685 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
686 int rc = -ENOENT;
687
688 spin_lock(&irq_mapping_update_lock);
689
690 desc = irq_to_desc(irq);
691 if (!desc)
692 goto out;
693
38aa66fc
JF
694 if (xen_initial_domain()) {
695 unmap_irq.pirq = info->u.pirq.gsi;
696 unmap_irq.domid = DOMID_SELF;
697 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
698 if (rc) {
699 printk(KERN_WARNING "unmap irq failed %d\n", rc);
700 goto out;
701 }
702 }
b5401a96
AN
703 irq_info[irq] = mk_unbound_info();
704
2c52f8d3 705 irq_free_desc(irq);
b5401a96
AN
706
707out:
708 spin_unlock(&irq_mapping_update_lock);
709 return rc;
710}
711
d46a78b0
JF
712int xen_vector_from_irq(unsigned irq)
713{
714 return vector_from_irq(irq);
715}
716
717int xen_gsi_from_irq(unsigned irq)
718{
719 return gsi_from_irq(irq);
720}
721
b536b4b9 722int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
723{
724 int irq;
725
726 spin_lock(&irq_mapping_update_lock);
727
728 irq = evtchn_to_irq[evtchn];
729
730 if (irq == -1) {
731 irq = find_unbound_irq();
732
e46cdb66 733 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
dffe2e1e 734 handle_edge_irq, "event");
e46cdb66
JF
735
736 evtchn_to_irq[evtchn] = irq;
ced40d0f 737 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
738 }
739
e46cdb66
JF
740 spin_unlock(&irq_mapping_update_lock);
741
742 return irq;
743}
b536b4b9 744EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 745
f87e4cac
JF
746static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
747{
748 struct evtchn_bind_ipi bind_ipi;
749 int evtchn, irq;
750
751 spin_lock(&irq_mapping_update_lock);
752
753 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 754
f87e4cac
JF
755 if (irq == -1) {
756 irq = find_unbound_irq();
757 if (irq < 0)
758 goto out;
759
aaca4964
JF
760 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
761 handle_percpu_irq, "ipi");
f87e4cac
JF
762
763 bind_ipi.vcpu = cpu;
764 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
765 &bind_ipi) != 0)
766 BUG();
767 evtchn = bind_ipi.port;
768
769 evtchn_to_irq[evtchn] = irq;
ced40d0f 770 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
771 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
772
773 bind_evtchn_to_cpu(evtchn, cpu);
774 }
775
f87e4cac
JF
776 out:
777 spin_unlock(&irq_mapping_update_lock);
778 return irq;
779}
780
781
e46cdb66
JF
782static int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
783{
784 struct evtchn_bind_virq bind_virq;
785 int evtchn, irq;
786
787 spin_lock(&irq_mapping_update_lock);
788
789 irq = per_cpu(virq_to_irq, cpu)[virq];
790
791 if (irq == -1) {
792 bind_virq.virq = virq;
793 bind_virq.vcpu = cpu;
794 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
795 &bind_virq) != 0)
796 BUG();
797 evtchn = bind_virq.port;
798
799 irq = find_unbound_irq();
800
aaca4964
JF
801 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
802 handle_percpu_irq, "virq");
e46cdb66
JF
803
804 evtchn_to_irq[evtchn] = irq;
ced40d0f 805 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
806
807 per_cpu(virq_to_irq, cpu)[virq] = irq;
808
809 bind_evtchn_to_cpu(evtchn, cpu);
810 }
811
e46cdb66
JF
812 spin_unlock(&irq_mapping_update_lock);
813
814 return irq;
815}
816
817static void unbind_from_irq(unsigned int irq)
818{
819 struct evtchn_close close;
820 int evtchn = evtchn_from_irq(irq);
821
822 spin_lock(&irq_mapping_update_lock);
823
d77bbd4d 824 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
825 close.port = evtchn;
826 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
827 BUG();
828
829 switch (type_from_irq(irq)) {
830 case IRQT_VIRQ:
831 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 832 [virq_from_irq(irq)] = -1;
e46cdb66 833 break;
d68d82af
AN
834 case IRQT_IPI:
835 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 836 [ipi_from_irq(irq)] = -1;
d68d82af 837 break;
e46cdb66
JF
838 default:
839 break;
840 }
841
842 /* Closed ports are implicitly re-bound to VCPU0. */
843 bind_evtchn_to_cpu(evtchn, 0);
844
845 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
846 }
847
848 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 849 irq_info[irq] = mk_unbound_info();
e46cdb66 850
77dff1c7 851 irq_free_desc(irq);
e46cdb66
JF
852 }
853
854 spin_unlock(&irq_mapping_update_lock);
855}
856
857int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 858 irq_handler_t handler,
e46cdb66
JF
859 unsigned long irqflags,
860 const char *devname, void *dev_id)
861{
862 unsigned int irq;
863 int retval;
864
865 irq = bind_evtchn_to_irq(evtchn);
866 retval = request_irq(irq, handler, irqflags, devname, dev_id);
867 if (retval != 0) {
868 unbind_from_irq(irq);
869 return retval;
870 }
871
872 return irq;
873}
874EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
875
876int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 877 irq_handler_t handler,
e46cdb66
JF
878 unsigned long irqflags, const char *devname, void *dev_id)
879{
880 unsigned int irq;
881 int retval;
882
883 irq = bind_virq_to_irq(virq, cpu);
884 retval = request_irq(irq, handler, irqflags, devname, dev_id);
885 if (retval != 0) {
886 unbind_from_irq(irq);
887 return retval;
888 }
889
890 return irq;
891}
892EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
893
f87e4cac
JF
894int bind_ipi_to_irqhandler(enum ipi_vector ipi,
895 unsigned int cpu,
896 irq_handler_t handler,
897 unsigned long irqflags,
898 const char *devname,
899 void *dev_id)
900{
901 int irq, retval;
902
903 irq = bind_ipi_to_irq(ipi, cpu);
904 if (irq < 0)
905 return irq;
906
4877c737 907 irqflags |= IRQF_NO_SUSPEND;
f87e4cac
JF
908 retval = request_irq(irq, handler, irqflags, devname, dev_id);
909 if (retval != 0) {
910 unbind_from_irq(irq);
911 return retval;
912 }
913
914 return irq;
915}
916
e46cdb66
JF
917void unbind_from_irqhandler(unsigned int irq, void *dev_id)
918{
919 free_irq(irq, dev_id);
920 unbind_from_irq(irq);
921}
922EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
923
f87e4cac
JF
924void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
925{
926 int irq = per_cpu(ipi_to_irq, cpu)[vector];
927 BUG_ON(irq < 0);
928 notify_remote_via_irq(irq);
929}
930
ee523ca1
JF
931irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
932{
933 struct shared_info *sh = HYPERVISOR_shared_info;
934 int cpu = smp_processor_id();
935 int i;
936 unsigned long flags;
937 static DEFINE_SPINLOCK(debug_lock);
938
939 spin_lock_irqsave(&debug_lock, flags);
940
941 printk("vcpu %d\n ", cpu);
942
943 for_each_online_cpu(i) {
944 struct vcpu_info *v = per_cpu(xen_vcpu, i);
945 printk("%d: masked=%d pending=%d event_sel %08lx\n ", i,
e849c3e9 946 (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask,
ee523ca1
JF
947 v->evtchn_upcall_pending,
948 v->evtchn_pending_sel);
949 }
950 printk("pending:\n ");
951 for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
952 printk("%08lx%s", sh->evtchn_pending[i],
953 i % 8 == 0 ? "\n " : " ");
954 printk("\nmasks:\n ");
955 for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
956 printk("%08lx%s", sh->evtchn_mask[i],
957 i % 8 == 0 ? "\n " : " ");
958
959 printk("\nunmasked:\n ");
960 for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
961 printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
962 i % 8 == 0 ? "\n " : " ");
963
964 printk("\npending list:\n");
965 for(i = 0; i < NR_EVENT_CHANNELS; i++) {
966 if (sync_test_bit(i, sh->evtchn_pending)) {
967 printk(" %d: event %d -> irq %d\n",
ced40d0f
JF
968 cpu_from_evtchn(i), i,
969 evtchn_to_irq[i]);
ee523ca1
JF
970 }
971 }
972
973 spin_unlock_irqrestore(&debug_lock, flags);
974
975 return IRQ_HANDLED;
976}
977
245b2e70
TH
978static DEFINE_PER_CPU(unsigned, xed_nesting_count);
979
e46cdb66
JF
980/*
981 * Search the CPUs pending events bitmasks. For each one found, map
982 * the event number to an irq, and feed it into do_IRQ() for
983 * handling.
984 *
985 * Xen uses a two-level bitmap to speed searching. The first level is
986 * a bitset of words which contain pending event bits. The second
987 * level is a bitset of pending events themselves.
988 */
38e20b07 989static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
990{
991 int cpu = get_cpu();
992 struct shared_info *s = HYPERVISOR_shared_info;
993 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
229664be 994 unsigned count;
e46cdb66 995
229664be
JF
996 do {
997 unsigned long pending_words;
e46cdb66 998
229664be 999 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1000
245b2e70 1001 if (__get_cpu_var(xed_nesting_count)++)
229664be 1002 goto out;
e46cdb66 1003
e849c3e9
IY
1004#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1005 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1006 wmb();
e849c3e9 1007#endif
229664be
JF
1008 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1009 while (pending_words != 0) {
1010 unsigned long pending_bits;
1011 int word_idx = __ffs(pending_words);
1012 pending_words &= ~(1UL << word_idx);
1013
1014 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1015 int bit_idx = __ffs(pending_bits);
1016 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1017 int irq = evtchn_to_irq[port];
ca4dbc66 1018 struct irq_desc *desc;
229664be 1019
ca4dbc66
EB
1020 if (irq != -1) {
1021 desc = irq_to_desc(irq);
1022 if (desc)
1023 generic_handle_irq_desc(irq, desc);
1024 }
e46cdb66
JF
1025 }
1026 }
e46cdb66 1027
229664be
JF
1028 BUG_ON(!irqs_disabled());
1029
245b2e70
TH
1030 count = __get_cpu_var(xed_nesting_count);
1031 __get_cpu_var(xed_nesting_count) = 0;
183d03cc 1032 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1033
1034out:
38e20b07
SY
1035
1036 put_cpu();
1037}
1038
1039void xen_evtchn_do_upcall(struct pt_regs *regs)
1040{
1041 struct pt_regs *old_regs = set_irq_regs(regs);
1042
1043 exit_idle();
1044 irq_enter();
1045
1046 __xen_evtchn_do_upcall();
1047
3445a8fd
JF
1048 irq_exit();
1049 set_irq_regs(old_regs);
38e20b07 1050}
3445a8fd 1051
38e20b07
SY
1052void xen_hvm_evtchn_do_upcall(void)
1053{
1054 __xen_evtchn_do_upcall();
e46cdb66 1055}
183d03cc 1056EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1057
eb1e305f
JF
1058/* Rebind a new event channel to an existing irq. */
1059void rebind_evtchn_irq(int evtchn, int irq)
1060{
d77bbd4d
JF
1061 struct irq_info *info = info_for_irq(irq);
1062
eb1e305f
JF
1063 /* Make sure the irq is masked, since the new event channel
1064 will also be masked. */
1065 disable_irq(irq);
1066
1067 spin_lock(&irq_mapping_update_lock);
1068
1069 /* After resume the irq<->evtchn mappings are all cleared out */
1070 BUG_ON(evtchn_to_irq[evtchn] != -1);
1071 /* Expect irq to have been bound before,
d77bbd4d
JF
1072 so there should be a proper type */
1073 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1074
1075 evtchn_to_irq[evtchn] = irq;
ced40d0f 1076 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1077
1078 spin_unlock(&irq_mapping_update_lock);
1079
1080 /* new event channels are always bound to cpu 0 */
0de26520 1081 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1082
1083 /* Unmask the event channel. */
1084 enable_irq(irq);
1085}
1086
e46cdb66 1087/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1088static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1089{
1090 struct evtchn_bind_vcpu bind_vcpu;
1091 int evtchn = evtchn_from_irq(irq);
1092
183d03cc
SS
1093 /* events delivered via platform PCI interrupts are always
1094 * routed to vcpu 0 */
1095 if (!VALID_EVTCHN(evtchn) ||
1096 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1097 return -1;
e46cdb66
JF
1098
1099 /* Send future instances of this interrupt to other vcpu. */
1100 bind_vcpu.port = evtchn;
1101 bind_vcpu.vcpu = tcpu;
1102
1103 /*
1104 * If this fails, it usually just indicates that we're dealing with a
1105 * virq or IPI channel, which don't actually need to be rebound. Ignore
1106 * it, but don't do the xenlinux-level rebind in that case.
1107 */
1108 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1109 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1110
d5dedd45
YL
1111 return 0;
1112}
e46cdb66 1113
d5dedd45 1114static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
e46cdb66 1115{
0de26520 1116 unsigned tcpu = cpumask_first(dest);
d5dedd45
YL
1117
1118 return rebind_irq_to_cpu(irq, tcpu);
e46cdb66
JF
1119}
1120
642e0c88
IY
1121int resend_irq_on_evtchn(unsigned int irq)
1122{
1123 int masked, evtchn = evtchn_from_irq(irq);
1124 struct shared_info *s = HYPERVISOR_shared_info;
1125
1126 if (!VALID_EVTCHN(evtchn))
1127 return 1;
1128
1129 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1130 sync_set_bit(evtchn, s->evtchn_pending);
1131 if (!masked)
1132 unmask_evtchn(evtchn);
1133
1134 return 1;
1135}
1136
e46cdb66
JF
1137static void enable_dynirq(unsigned int irq)
1138{
1139 int evtchn = evtchn_from_irq(irq);
1140
1141 if (VALID_EVTCHN(evtchn))
1142 unmask_evtchn(evtchn);
1143}
1144
1145static void disable_dynirq(unsigned int irq)
1146{
1147 int evtchn = evtchn_from_irq(irq);
1148
1149 if (VALID_EVTCHN(evtchn))
1150 mask_evtchn(evtchn);
1151}
1152
1153static void ack_dynirq(unsigned int irq)
1154{
1155 int evtchn = evtchn_from_irq(irq);
1156
1157 move_native_irq(irq);
1158
1159 if (VALID_EVTCHN(evtchn))
1160 clear_evtchn(evtchn);
1161}
1162
1163static int retrigger_dynirq(unsigned int irq)
1164{
1165 int evtchn = evtchn_from_irq(irq);
ee8fa1c6 1166 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1167 int ret = 0;
1168
1169 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1170 int masked;
1171
1172 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1173 sync_set_bit(evtchn, sh->evtchn_pending);
1174 if (!masked)
1175 unmask_evtchn(evtchn);
e46cdb66
JF
1176 ret = 1;
1177 }
1178
1179 return ret;
1180}
1181
0e91398f
JF
1182static void restore_cpu_virqs(unsigned int cpu)
1183{
1184 struct evtchn_bind_virq bind_virq;
1185 int virq, irq, evtchn;
1186
1187 for (virq = 0; virq < NR_VIRQS; virq++) {
1188 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1189 continue;
1190
ced40d0f 1191 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1192
1193 /* Get a new binding from Xen. */
1194 bind_virq.virq = virq;
1195 bind_virq.vcpu = cpu;
1196 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1197 &bind_virq) != 0)
1198 BUG();
1199 evtchn = bind_virq.port;
1200
1201 /* Record the new mapping. */
1202 evtchn_to_irq[evtchn] = irq;
ced40d0f 1203 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f
JF
1204 bind_evtchn_to_cpu(evtchn, cpu);
1205
1206 /* Ready for use. */
1207 unmask_evtchn(evtchn);
1208 }
1209}
1210
1211static void restore_cpu_ipis(unsigned int cpu)
1212{
1213 struct evtchn_bind_ipi bind_ipi;
1214 int ipi, irq, evtchn;
1215
1216 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1217 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1218 continue;
1219
ced40d0f 1220 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1221
1222 /* Get a new binding from Xen. */
1223 bind_ipi.vcpu = cpu;
1224 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1225 &bind_ipi) != 0)
1226 BUG();
1227 evtchn = bind_ipi.port;
1228
1229 /* Record the new mapping. */
1230 evtchn_to_irq[evtchn] = irq;
ced40d0f 1231 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f
JF
1232 bind_evtchn_to_cpu(evtchn, cpu);
1233
1234 /* Ready for use. */
1235 unmask_evtchn(evtchn);
1236
1237 }
1238}
1239
2d9e1e2f
JF
1240/* Clear an irq's pending state, in preparation for polling on it */
1241void xen_clear_irq_pending(int irq)
1242{
1243 int evtchn = evtchn_from_irq(irq);
1244
1245 if (VALID_EVTCHN(evtchn))
1246 clear_evtchn(evtchn);
1247}
d9a8814f 1248EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1249void xen_set_irq_pending(int irq)
1250{
1251 int evtchn = evtchn_from_irq(irq);
1252
1253 if (VALID_EVTCHN(evtchn))
1254 set_evtchn(evtchn);
1255}
1256
1257bool xen_test_irq_pending(int irq)
1258{
1259 int evtchn = evtchn_from_irq(irq);
1260 bool ret = false;
1261
1262 if (VALID_EVTCHN(evtchn))
1263 ret = test_evtchn(evtchn);
1264
1265 return ret;
1266}
1267
d9a8814f
KRW
1268/* Poll waiting for an irq to become pending with timeout. In the usual case,
1269 * the irq will be disabled so it won't deliver an interrupt. */
1270void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1271{
1272 evtchn_port_t evtchn = evtchn_from_irq(irq);
1273
1274 if (VALID_EVTCHN(evtchn)) {
1275 struct sched_poll poll;
1276
1277 poll.nr_ports = 1;
d9a8814f 1278 poll.timeout = timeout;
ff3c5362 1279 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1280
1281 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1282 BUG();
1283 }
1284}
d9a8814f
KRW
1285EXPORT_SYMBOL(xen_poll_irq_timeout);
1286/* Poll waiting for an irq to become pending. In the usual case, the
1287 * irq will be disabled so it won't deliver an interrupt. */
1288void xen_poll_irq(int irq)
1289{
1290 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1291}
2d9e1e2f 1292
0e91398f
JF
1293void xen_irq_resume(void)
1294{
1295 unsigned int cpu, irq, evtchn;
1296
1297 init_evtchn_cpu_bindings();
1298
1299 /* New event-channel space is not 'live' yet. */
1300 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1301 mask_evtchn(evtchn);
1302
1303 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1304 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1305 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1306
1307 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1308 evtchn_to_irq[evtchn] = -1;
1309
1310 for_each_possible_cpu(cpu) {
1311 restore_cpu_virqs(cpu);
1312 restore_cpu_ipis(cpu);
1313 }
1314}
1315
e46cdb66
JF
1316static struct irq_chip xen_dynamic_chip __read_mostly = {
1317 .name = "xen-dyn",
54a353a0
JF
1318
1319 .disable = disable_dynirq,
e46cdb66
JF
1320 .mask = disable_dynirq,
1321 .unmask = enable_dynirq,
54a353a0 1322
e46cdb66
JF
1323 .ack = ack_dynirq,
1324 .set_affinity = set_affinity_irq,
1325 .retrigger = retrigger_dynirq,
1326};
1327
d46a78b0
JF
1328static struct irq_chip xen_pirq_chip __read_mostly = {
1329 .name = "xen-pirq",
1330
1331 .startup = startup_pirq,
1332 .shutdown = shutdown_pirq,
1333
1334 .enable = enable_pirq,
1335 .unmask = enable_pirq,
1336
1337 .disable = disable_pirq,
1338 .mask = disable_pirq,
1339
1340 .ack = ack_pirq,
1341 .end = end_pirq,
1342
1343 .set_affinity = set_affinity_irq,
1344
1345 .retrigger = retrigger_dynirq,
1346};
1347
aaca4964
JF
1348static struct irq_chip xen_percpu_chip __read_mostly = {
1349 .name = "xen-percpu",
1350
1351 .disable = disable_dynirq,
1352 .mask = disable_dynirq,
1353 .unmask = enable_dynirq,
1354
1355 .ack = ack_dynirq,
1356};
1357
38e20b07
SY
1358int xen_set_callback_via(uint64_t via)
1359{
1360 struct xen_hvm_param a;
1361 a.domid = DOMID_SELF;
1362 a.index = HVM_PARAM_CALLBACK_IRQ;
1363 a.value = via;
1364 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1365}
1366EXPORT_SYMBOL_GPL(xen_set_callback_via);
1367
ca65f9fc 1368#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1369/* Vector callbacks are better than PCI interrupts to receive event
1370 * channel notifications because we can receive vector callbacks on any
1371 * vcpu and we don't need PCI support or APIC interactions. */
1372void xen_callback_vector(void)
1373{
1374 int rc;
1375 uint64_t callback_via;
1376 if (xen_have_vector_callback) {
1377 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1378 rc = xen_set_callback_via(callback_via);
1379 if (rc) {
1380 printk(KERN_ERR "Request for Xen HVM callback vector"
1381 " failed.\n");
1382 xen_have_vector_callback = 0;
1383 return;
1384 }
1385 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1386 "enabled\n");
1387 /* in the restore case the vector has already been allocated */
1388 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1389 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1390 }
1391}
ca65f9fc
SS
1392#else
1393void xen_callback_vector(void) {}
1394#endif
38e20b07 1395
e46cdb66
JF
1396void __init xen_init_IRQ(void)
1397{
01557baf
SS
1398 int i, rc;
1399 struct physdev_nr_pirqs op_nr_pirqs;
c7a3589e 1400
a70c352a
PE
1401 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1402 GFP_KERNEL);
b21ddbf5
JF
1403 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1404
01557baf
SS
1405 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_nr_pirqs, &op_nr_pirqs);
1406 if (rc < 0) {
1407 nr_pirqs = nr_irqs;
1408 if (rc != -ENOSYS)
1409 printk(KERN_WARNING "PHYSDEVOP_get_nr_pirqs returned rc=%d\n", rc);
1410 } else {
1411 if (xen_pv_domain() && !xen_initial_domain())
1412 nr_pirqs = max((int)op_nr_pirqs.nr_pirqs, nr_irqs);
1413 else
1414 nr_pirqs = op_nr_pirqs.nr_pirqs;
1415 }
1416 pirq_to_irq = kcalloc(nr_pirqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1417 for (i = 0; i < nr_pirqs; i++)
7a043f11
SS
1418 pirq_to_irq[i] = -1;
1419
b21ddbf5
JF
1420 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1421 GFP_KERNEL);
1422 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1423 evtchn_to_irq[i] = -1;
e46cdb66
JF
1424
1425 init_evtchn_cpu_bindings();
1426
1427 /* No event channels are 'live' right now. */
1428 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1429 mask_evtchn(i);
1430
38e20b07
SY
1431 if (xen_hvm_domain()) {
1432 xen_callback_vector();
1433 native_init_IRQ();
3942b740
SS
1434 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1435 * __acpi_register_gsi can point at the right function */
1436 pci_xen_hvm_init();
38e20b07
SY
1437 } else {
1438 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1439 if (xen_initial_domain())
1440 xen_setup_pirqs();
38e20b07 1441 }
e46cdb66 1442}