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x86/xen: event channels delivery on HVM.
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e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
19 * 4. Hardware interrupts. Not supported at present.
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
e46cdb66 31
38e20b07 32#include <asm/desc.h>
e46cdb66
JF
33#include <asm/ptrace.h>
34#include <asm/irq.h>
792dc4f6 35#include <asm/idle.h>
e46cdb66
JF
36#include <asm/sync_bitops.h>
37#include <asm/xen/hypercall.h>
8d1b8753 38#include <asm/xen/hypervisor.h>
e46cdb66 39
38e20b07
SY
40#include <xen/xen.h>
41#include <xen/hvm.h>
e04d0d07 42#include <xen/xen-ops.h>
e46cdb66
JF
43#include <xen/events.h>
44#include <xen/interface/xen.h>
45#include <xen/interface/event_channel.h>
38e20b07
SY
46#include <xen/interface/hvm/hvm_op.h>
47#include <xen/interface/hvm/params.h>
e46cdb66 48
e46cdb66
JF
49/*
50 * This lock protects updates to the following mapping and reference-count
51 * arrays. The lock does not need to be acquired to read the mapping tables.
52 */
53static DEFINE_SPINLOCK(irq_mapping_update_lock);
54
55/* IRQ <-> VIRQ mapping. */
204fba4a 56static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 57
f87e4cac 58/* IRQ <-> IPI mapping */
204fba4a 59static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 60
ced40d0f
JF
61/* Interrupt types. */
62enum xen_irq_type {
d77bbd4d 63 IRQT_UNBOUND = 0,
f87e4cac
JF
64 IRQT_PIRQ,
65 IRQT_VIRQ,
66 IRQT_IPI,
67 IRQT_EVTCHN
68};
e46cdb66 69
ced40d0f
JF
70/*
71 * Packed IRQ information:
72 * type - enum xen_irq_type
73 * event channel - irq->event channel mapping
74 * cpu - cpu this event channel is bound to
75 * index - type-specific information:
76 * PIRQ - vector, with MSB being "needs EIO"
77 * VIRQ - virq number
78 * IPI - IPI vector
79 * EVTCHN -
80 */
81struct irq_info
82{
83 enum xen_irq_type type; /* type */
84 unsigned short evtchn; /* event channel */
85 unsigned short cpu; /* cpu bound */
86
87 union {
88 unsigned short virq;
89 enum ipi_vector ipi;
90 struct {
91 unsigned short gsi;
92 unsigned short vector;
93 } pirq;
94 } u;
95};
96
97static struct irq_info irq_info[NR_IRQS];
e46cdb66
JF
98
99static int evtchn_to_irq[NR_EVENT_CHANNELS] = {
100 [0 ... NR_EVENT_CHANNELS-1] = -1
101};
c7a3589e
MT
102struct cpu_evtchn_s {
103 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
104};
105static struct cpu_evtchn_s *cpu_evtchn_mask_p;
106static inline unsigned long *cpu_evtchn_mask(int cpu)
107{
108 return cpu_evtchn_mask_p[cpu].bits;
109}
e46cdb66 110
e46cdb66
JF
111/* Xen will never allocate port zero for any purpose. */
112#define VALID_EVTCHN(chn) ((chn) != 0)
113
e46cdb66
JF
114static struct irq_chip xen_dynamic_chip;
115
116/* Constructor for packed IRQ information. */
ced40d0f
JF
117static struct irq_info mk_unbound_info(void)
118{
119 return (struct irq_info) { .type = IRQT_UNBOUND };
120}
121
122static struct irq_info mk_evtchn_info(unsigned short evtchn)
123{
90af9514
IC
124 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
125 .cpu = 0 };
ced40d0f
JF
126}
127
128static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 129{
ced40d0f 130 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 131 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
132}
133
134static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
135{
136 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 137 .cpu = 0, .u.virq = virq };
ced40d0f
JF
138}
139
140static struct irq_info mk_pirq_info(unsigned short evtchn,
141 unsigned short gsi, unsigned short vector)
142{
143 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
90af9514 144 .cpu = 0, .u.pirq = { .gsi = gsi, .vector = vector } };
e46cdb66
JF
145}
146
147/*
148 * Accessors for packed IRQ information.
149 */
ced40d0f 150static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 151{
ced40d0f 152 return &irq_info[irq];
e46cdb66
JF
153}
154
ced40d0f 155static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 156{
ced40d0f 157 return info_for_irq(irq)->evtchn;
e46cdb66
JF
158}
159
d4c04536
IC
160unsigned irq_from_evtchn(unsigned int evtchn)
161{
162 return evtchn_to_irq[evtchn];
163}
164EXPORT_SYMBOL_GPL(irq_from_evtchn);
165
ced40d0f 166static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 167{
ced40d0f
JF
168 struct irq_info *info = info_for_irq(irq);
169
170 BUG_ON(info == NULL);
171 BUG_ON(info->type != IRQT_IPI);
172
173 return info->u.ipi;
174}
175
176static unsigned virq_from_irq(unsigned irq)
177{
178 struct irq_info *info = info_for_irq(irq);
179
180 BUG_ON(info == NULL);
181 BUG_ON(info->type != IRQT_VIRQ);
182
183 return info->u.virq;
184}
185
186static unsigned gsi_from_irq(unsigned irq)
187{
188 struct irq_info *info = info_for_irq(irq);
189
190 BUG_ON(info == NULL);
191 BUG_ON(info->type != IRQT_PIRQ);
192
193 return info->u.pirq.gsi;
194}
195
196static unsigned vector_from_irq(unsigned irq)
197{
198 struct irq_info *info = info_for_irq(irq);
199
200 BUG_ON(info == NULL);
201 BUG_ON(info->type != IRQT_PIRQ);
202
203 return info->u.pirq.vector;
204}
205
206static enum xen_irq_type type_from_irq(unsigned irq)
207{
208 return info_for_irq(irq)->type;
209}
210
211static unsigned cpu_from_irq(unsigned irq)
212{
213 return info_for_irq(irq)->cpu;
214}
215
216static unsigned int cpu_from_evtchn(unsigned int evtchn)
217{
218 int irq = evtchn_to_irq[evtchn];
219 unsigned ret = 0;
220
221 if (irq != -1)
222 ret = cpu_from_irq(irq);
223
224 return ret;
e46cdb66
JF
225}
226
227static inline unsigned long active_evtchns(unsigned int cpu,
228 struct shared_info *sh,
229 unsigned int idx)
230{
231 return (sh->evtchn_pending[idx] &
c7a3589e 232 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
233 ~sh->evtchn_mask[idx]);
234}
235
236static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
237{
238 int irq = evtchn_to_irq[chn];
239
240 BUG_ON(irq == -1);
241#ifdef CONFIG_SMP
7f7ace0c 242 cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
e46cdb66
JF
243#endif
244
ced40d0f 245 __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
c7a3589e 246 __set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 247
ced40d0f 248 irq_info[irq].cpu = cpu;
e46cdb66
JF
249}
250
251static void init_evtchn_cpu_bindings(void)
252{
253#ifdef CONFIG_SMP
10e58084 254 struct irq_desc *desc;
e46cdb66 255 int i;
10e58084 256
e46cdb66 257 /* By default all event channels notify CPU#0. */
0b8f1efa 258 for_each_irq_desc(i, desc) {
7f7ace0c 259 cpumask_copy(desc->affinity, cpumask_of(0));
0b8f1efa 260 }
e46cdb66
JF
261#endif
262
c7a3589e 263 memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0)));
e46cdb66
JF
264}
265
e46cdb66
JF
266static inline void clear_evtchn(int port)
267{
268 struct shared_info *s = HYPERVISOR_shared_info;
269 sync_clear_bit(port, &s->evtchn_pending[0]);
270}
271
272static inline void set_evtchn(int port)
273{
274 struct shared_info *s = HYPERVISOR_shared_info;
275 sync_set_bit(port, &s->evtchn_pending[0]);
276}
277
168d2f46
JF
278static inline int test_evtchn(int port)
279{
280 struct shared_info *s = HYPERVISOR_shared_info;
281 return sync_test_bit(port, &s->evtchn_pending[0]);
282}
283
e46cdb66
JF
284
285/**
286 * notify_remote_via_irq - send event to remote end of event channel via irq
287 * @irq: irq of event channel to send event to
288 *
289 * Unlike notify_remote_via_evtchn(), this is safe to use across
290 * save/restore. Notifications on a broken connection are silently
291 * dropped.
292 */
293void notify_remote_via_irq(int irq)
294{
295 int evtchn = evtchn_from_irq(irq);
296
297 if (VALID_EVTCHN(evtchn))
298 notify_remote_via_evtchn(evtchn);
299}
300EXPORT_SYMBOL_GPL(notify_remote_via_irq);
301
302static void mask_evtchn(int port)
303{
304 struct shared_info *s = HYPERVISOR_shared_info;
305 sync_set_bit(port, &s->evtchn_mask[0]);
306}
307
308static void unmask_evtchn(int port)
309{
310 struct shared_info *s = HYPERVISOR_shared_info;
311 unsigned int cpu = get_cpu();
312
313 BUG_ON(!irqs_disabled());
314
315 /* Slow path (hypercall) if this is a non-local port. */
316 if (unlikely(cpu != cpu_from_evtchn(port))) {
317 struct evtchn_unmask unmask = { .port = port };
318 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
319 } else {
320 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
321
322 sync_clear_bit(port, &s->evtchn_mask[0]);
323
324 /*
325 * The following is basically the equivalent of
326 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
327 * the interrupt edge' if the channel is masked.
328 */
329 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
330 !sync_test_and_set_bit(port / BITS_PER_LONG,
331 &vcpu_info->evtchn_pending_sel))
332 vcpu_info->evtchn_upcall_pending = 1;
333 }
334
335 put_cpu();
336}
337
338static int find_unbound_irq(void)
339{
340 int irq;
6f8a0ed4 341 struct irq_desc *desc;
e46cdb66 342
0b8f1efa 343 for (irq = 0; irq < nr_irqs; irq++)
d77bbd4d 344 if (irq_info[irq].type == IRQT_UNBOUND)
e46cdb66
JF
345 break;
346
5a15d7e8
YL
347 if (irq == nr_irqs)
348 panic("No available IRQ to bind to: increase nr_irqs!\n");
e46cdb66 349
85ac16d0 350 desc = irq_to_desc_alloc_node(irq, 0);
6f8a0ed4
JF
351 if (WARN_ON(desc == NULL))
352 return -1;
353
ced40d0f
JF
354 dynamic_irq_init(irq);
355
e46cdb66
JF
356 return irq;
357}
358
b536b4b9 359int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
360{
361 int irq;
362
363 spin_lock(&irq_mapping_update_lock);
364
365 irq = evtchn_to_irq[evtchn];
366
367 if (irq == -1) {
368 irq = find_unbound_irq();
369
e46cdb66
JF
370 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
371 handle_level_irq, "event");
372
373 evtchn_to_irq[evtchn] = irq;
ced40d0f 374 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
375 }
376
e46cdb66
JF
377 spin_unlock(&irq_mapping_update_lock);
378
379 return irq;
380}
b536b4b9 381EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 382
f87e4cac
JF
383static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
384{
385 struct evtchn_bind_ipi bind_ipi;
386 int evtchn, irq;
387
388 spin_lock(&irq_mapping_update_lock);
389
390 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 391
f87e4cac
JF
392 if (irq == -1) {
393 irq = find_unbound_irq();
394 if (irq < 0)
395 goto out;
396
f87e4cac
JF
397 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
398 handle_level_irq, "ipi");
399
400 bind_ipi.vcpu = cpu;
401 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
402 &bind_ipi) != 0)
403 BUG();
404 evtchn = bind_ipi.port;
405
406 evtchn_to_irq[evtchn] = irq;
ced40d0f 407 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
408 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
409
410 bind_evtchn_to_cpu(evtchn, cpu);
411 }
412
f87e4cac
JF
413 out:
414 spin_unlock(&irq_mapping_update_lock);
415 return irq;
416}
417
418
e46cdb66
JF
419static int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
420{
421 struct evtchn_bind_virq bind_virq;
422 int evtchn, irq;
423
424 spin_lock(&irq_mapping_update_lock);
425
426 irq = per_cpu(virq_to_irq, cpu)[virq];
427
428 if (irq == -1) {
429 bind_virq.virq = virq;
430 bind_virq.vcpu = cpu;
431 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
432 &bind_virq) != 0)
433 BUG();
434 evtchn = bind_virq.port;
435
436 irq = find_unbound_irq();
437
e46cdb66
JF
438 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
439 handle_level_irq, "virq");
440
441 evtchn_to_irq[evtchn] = irq;
ced40d0f 442 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
443
444 per_cpu(virq_to_irq, cpu)[virq] = irq;
445
446 bind_evtchn_to_cpu(evtchn, cpu);
447 }
448
e46cdb66
JF
449 spin_unlock(&irq_mapping_update_lock);
450
451 return irq;
452}
453
454static void unbind_from_irq(unsigned int irq)
455{
456 struct evtchn_close close;
457 int evtchn = evtchn_from_irq(irq);
458
459 spin_lock(&irq_mapping_update_lock);
460
d77bbd4d 461 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
462 close.port = evtchn;
463 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
464 BUG();
465
466 switch (type_from_irq(irq)) {
467 case IRQT_VIRQ:
468 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 469 [virq_from_irq(irq)] = -1;
e46cdb66 470 break;
d68d82af
AN
471 case IRQT_IPI:
472 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 473 [ipi_from_irq(irq)] = -1;
d68d82af 474 break;
e46cdb66
JF
475 default:
476 break;
477 }
478
479 /* Closed ports are implicitly re-bound to VCPU0. */
480 bind_evtchn_to_cpu(evtchn, 0);
481
482 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
483 }
484
485 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 486 irq_info[irq] = mk_unbound_info();
e46cdb66 487
0f2287ad 488 dynamic_irq_cleanup(irq);
e46cdb66
JF
489 }
490
491 spin_unlock(&irq_mapping_update_lock);
492}
493
494int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 495 irq_handler_t handler,
e46cdb66
JF
496 unsigned long irqflags,
497 const char *devname, void *dev_id)
498{
499 unsigned int irq;
500 int retval;
501
502 irq = bind_evtchn_to_irq(evtchn);
503 retval = request_irq(irq, handler, irqflags, devname, dev_id);
504 if (retval != 0) {
505 unbind_from_irq(irq);
506 return retval;
507 }
508
509 return irq;
510}
511EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
512
513int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 514 irq_handler_t handler,
e46cdb66
JF
515 unsigned long irqflags, const char *devname, void *dev_id)
516{
517 unsigned int irq;
518 int retval;
519
520 irq = bind_virq_to_irq(virq, cpu);
521 retval = request_irq(irq, handler, irqflags, devname, dev_id);
522 if (retval != 0) {
523 unbind_from_irq(irq);
524 return retval;
525 }
526
527 return irq;
528}
529EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
530
f87e4cac
JF
531int bind_ipi_to_irqhandler(enum ipi_vector ipi,
532 unsigned int cpu,
533 irq_handler_t handler,
534 unsigned long irqflags,
535 const char *devname,
536 void *dev_id)
537{
538 int irq, retval;
539
540 irq = bind_ipi_to_irq(ipi, cpu);
541 if (irq < 0)
542 return irq;
543
544 retval = request_irq(irq, handler, irqflags, devname, dev_id);
545 if (retval != 0) {
546 unbind_from_irq(irq);
547 return retval;
548 }
549
550 return irq;
551}
552
e46cdb66
JF
553void unbind_from_irqhandler(unsigned int irq, void *dev_id)
554{
555 free_irq(irq, dev_id);
556 unbind_from_irq(irq);
557}
558EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
559
f87e4cac
JF
560void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
561{
562 int irq = per_cpu(ipi_to_irq, cpu)[vector];
563 BUG_ON(irq < 0);
564 notify_remote_via_irq(irq);
565}
566
ee523ca1
JF
567irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
568{
569 struct shared_info *sh = HYPERVISOR_shared_info;
570 int cpu = smp_processor_id();
571 int i;
572 unsigned long flags;
573 static DEFINE_SPINLOCK(debug_lock);
574
575 spin_lock_irqsave(&debug_lock, flags);
576
577 printk("vcpu %d\n ", cpu);
578
579 for_each_online_cpu(i) {
580 struct vcpu_info *v = per_cpu(xen_vcpu, i);
581 printk("%d: masked=%d pending=%d event_sel %08lx\n ", i,
e849c3e9 582 (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask,
ee523ca1
JF
583 v->evtchn_upcall_pending,
584 v->evtchn_pending_sel);
585 }
586 printk("pending:\n ");
587 for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
588 printk("%08lx%s", sh->evtchn_pending[i],
589 i % 8 == 0 ? "\n " : " ");
590 printk("\nmasks:\n ");
591 for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
592 printk("%08lx%s", sh->evtchn_mask[i],
593 i % 8 == 0 ? "\n " : " ");
594
595 printk("\nunmasked:\n ");
596 for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
597 printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
598 i % 8 == 0 ? "\n " : " ");
599
600 printk("\npending list:\n");
601 for(i = 0; i < NR_EVENT_CHANNELS; i++) {
602 if (sync_test_bit(i, sh->evtchn_pending)) {
603 printk(" %d: event %d -> irq %d\n",
ced40d0f
JF
604 cpu_from_evtchn(i), i,
605 evtchn_to_irq[i]);
ee523ca1
JF
606 }
607 }
608
609 spin_unlock_irqrestore(&debug_lock, flags);
610
611 return IRQ_HANDLED;
612}
613
245b2e70
TH
614static DEFINE_PER_CPU(unsigned, xed_nesting_count);
615
e46cdb66
JF
616/*
617 * Search the CPUs pending events bitmasks. For each one found, map
618 * the event number to an irq, and feed it into do_IRQ() for
619 * handling.
620 *
621 * Xen uses a two-level bitmap to speed searching. The first level is
622 * a bitset of words which contain pending event bits. The second
623 * level is a bitset of pending events themselves.
624 */
38e20b07 625static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
626{
627 int cpu = get_cpu();
628 struct shared_info *s = HYPERVISOR_shared_info;
629 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
229664be 630 unsigned count;
e46cdb66 631
229664be
JF
632 do {
633 unsigned long pending_words;
e46cdb66 634
229664be 635 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 636
245b2e70 637 if (__get_cpu_var(xed_nesting_count)++)
229664be 638 goto out;
e46cdb66 639
e849c3e9
IY
640#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
641 /* Clear master flag /before/ clearing selector flag. */
6673cf63 642 wmb();
e849c3e9 643#endif
229664be
JF
644 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
645 while (pending_words != 0) {
646 unsigned long pending_bits;
647 int word_idx = __ffs(pending_words);
648 pending_words &= ~(1UL << word_idx);
649
650 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
651 int bit_idx = __ffs(pending_bits);
652 int port = (word_idx * BITS_PER_LONG) + bit_idx;
653 int irq = evtchn_to_irq[port];
ca4dbc66 654 struct irq_desc *desc;
229664be 655
ca4dbc66
EB
656 if (irq != -1) {
657 desc = irq_to_desc(irq);
658 if (desc)
659 generic_handle_irq_desc(irq, desc);
660 }
e46cdb66
JF
661 }
662 }
e46cdb66 663
229664be
JF
664 BUG_ON(!irqs_disabled());
665
245b2e70
TH
666 count = __get_cpu_var(xed_nesting_count);
667 __get_cpu_var(xed_nesting_count) = 0;
229664be
JF
668 } while(count != 1);
669
670out:
38e20b07
SY
671
672 put_cpu();
673}
674
675void xen_evtchn_do_upcall(struct pt_regs *regs)
676{
677 struct pt_regs *old_regs = set_irq_regs(regs);
678
679 exit_idle();
680 irq_enter();
681
682 __xen_evtchn_do_upcall();
683
3445a8fd
JF
684 irq_exit();
685 set_irq_regs(old_regs);
38e20b07 686}
3445a8fd 687
38e20b07
SY
688void xen_hvm_evtchn_do_upcall(void)
689{
690 __xen_evtchn_do_upcall();
e46cdb66
JF
691}
692
eb1e305f
JF
693/* Rebind a new event channel to an existing irq. */
694void rebind_evtchn_irq(int evtchn, int irq)
695{
d77bbd4d
JF
696 struct irq_info *info = info_for_irq(irq);
697
eb1e305f
JF
698 /* Make sure the irq is masked, since the new event channel
699 will also be masked. */
700 disable_irq(irq);
701
702 spin_lock(&irq_mapping_update_lock);
703
704 /* After resume the irq<->evtchn mappings are all cleared out */
705 BUG_ON(evtchn_to_irq[evtchn] != -1);
706 /* Expect irq to have been bound before,
d77bbd4d
JF
707 so there should be a proper type */
708 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
709
710 evtchn_to_irq[evtchn] = irq;
ced40d0f 711 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
712
713 spin_unlock(&irq_mapping_update_lock);
714
715 /* new event channels are always bound to cpu 0 */
0de26520 716 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
717
718 /* Unmask the event channel. */
719 enable_irq(irq);
720}
721
e46cdb66 722/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 723static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
724{
725 struct evtchn_bind_vcpu bind_vcpu;
726 int evtchn = evtchn_from_irq(irq);
727
728 if (!VALID_EVTCHN(evtchn))
d5dedd45 729 return -1;
e46cdb66
JF
730
731 /* Send future instances of this interrupt to other vcpu. */
732 bind_vcpu.port = evtchn;
733 bind_vcpu.vcpu = tcpu;
734
735 /*
736 * If this fails, it usually just indicates that we're dealing with a
737 * virq or IPI channel, which don't actually need to be rebound. Ignore
738 * it, but don't do the xenlinux-level rebind in that case.
739 */
740 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
741 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 742
d5dedd45
YL
743 return 0;
744}
e46cdb66 745
d5dedd45 746static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
e46cdb66 747{
0de26520 748 unsigned tcpu = cpumask_first(dest);
d5dedd45
YL
749
750 return rebind_irq_to_cpu(irq, tcpu);
e46cdb66
JF
751}
752
642e0c88
IY
753int resend_irq_on_evtchn(unsigned int irq)
754{
755 int masked, evtchn = evtchn_from_irq(irq);
756 struct shared_info *s = HYPERVISOR_shared_info;
757
758 if (!VALID_EVTCHN(evtchn))
759 return 1;
760
761 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
762 sync_set_bit(evtchn, s->evtchn_pending);
763 if (!masked)
764 unmask_evtchn(evtchn);
765
766 return 1;
767}
768
e46cdb66
JF
769static void enable_dynirq(unsigned int irq)
770{
771 int evtchn = evtchn_from_irq(irq);
772
773 if (VALID_EVTCHN(evtchn))
774 unmask_evtchn(evtchn);
775}
776
777static void disable_dynirq(unsigned int irq)
778{
779 int evtchn = evtchn_from_irq(irq);
780
781 if (VALID_EVTCHN(evtchn))
782 mask_evtchn(evtchn);
783}
784
785static void ack_dynirq(unsigned int irq)
786{
787 int evtchn = evtchn_from_irq(irq);
788
789 move_native_irq(irq);
790
791 if (VALID_EVTCHN(evtchn))
792 clear_evtchn(evtchn);
793}
794
795static int retrigger_dynirq(unsigned int irq)
796{
797 int evtchn = evtchn_from_irq(irq);
ee8fa1c6 798 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
799 int ret = 0;
800
801 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
802 int masked;
803
804 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
805 sync_set_bit(evtchn, sh->evtchn_pending);
806 if (!masked)
807 unmask_evtchn(evtchn);
e46cdb66
JF
808 ret = 1;
809 }
810
811 return ret;
812}
813
0e91398f
JF
814static void restore_cpu_virqs(unsigned int cpu)
815{
816 struct evtchn_bind_virq bind_virq;
817 int virq, irq, evtchn;
818
819 for (virq = 0; virq < NR_VIRQS; virq++) {
820 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
821 continue;
822
ced40d0f 823 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
824
825 /* Get a new binding from Xen. */
826 bind_virq.virq = virq;
827 bind_virq.vcpu = cpu;
828 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
829 &bind_virq) != 0)
830 BUG();
831 evtchn = bind_virq.port;
832
833 /* Record the new mapping. */
834 evtchn_to_irq[evtchn] = irq;
ced40d0f 835 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f
JF
836 bind_evtchn_to_cpu(evtchn, cpu);
837
838 /* Ready for use. */
839 unmask_evtchn(evtchn);
840 }
841}
842
843static void restore_cpu_ipis(unsigned int cpu)
844{
845 struct evtchn_bind_ipi bind_ipi;
846 int ipi, irq, evtchn;
847
848 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
849 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
850 continue;
851
ced40d0f 852 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
853
854 /* Get a new binding from Xen. */
855 bind_ipi.vcpu = cpu;
856 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
857 &bind_ipi) != 0)
858 BUG();
859 evtchn = bind_ipi.port;
860
861 /* Record the new mapping. */
862 evtchn_to_irq[evtchn] = irq;
ced40d0f 863 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f
JF
864 bind_evtchn_to_cpu(evtchn, cpu);
865
866 /* Ready for use. */
867 unmask_evtchn(evtchn);
868
869 }
870}
871
2d9e1e2f
JF
872/* Clear an irq's pending state, in preparation for polling on it */
873void xen_clear_irq_pending(int irq)
874{
875 int evtchn = evtchn_from_irq(irq);
876
877 if (VALID_EVTCHN(evtchn))
878 clear_evtchn(evtchn);
879}
880
168d2f46
JF
881void xen_set_irq_pending(int irq)
882{
883 int evtchn = evtchn_from_irq(irq);
884
885 if (VALID_EVTCHN(evtchn))
886 set_evtchn(evtchn);
887}
888
889bool xen_test_irq_pending(int irq)
890{
891 int evtchn = evtchn_from_irq(irq);
892 bool ret = false;
893
894 if (VALID_EVTCHN(evtchn))
895 ret = test_evtchn(evtchn);
896
897 return ret;
898}
899
2d9e1e2f
JF
900/* Poll waiting for an irq to become pending. In the usual case, the
901 irq will be disabled so it won't deliver an interrupt. */
902void xen_poll_irq(int irq)
903{
904 evtchn_port_t evtchn = evtchn_from_irq(irq);
905
906 if (VALID_EVTCHN(evtchn)) {
907 struct sched_poll poll;
908
909 poll.nr_ports = 1;
910 poll.timeout = 0;
ff3c5362 911 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
912
913 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
914 BUG();
915 }
916}
917
0e91398f
JF
918void xen_irq_resume(void)
919{
920 unsigned int cpu, irq, evtchn;
921
922 init_evtchn_cpu_bindings();
923
924 /* New event-channel space is not 'live' yet. */
925 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
926 mask_evtchn(evtchn);
927
928 /* No IRQ <-> event-channel mappings. */
0b8f1efa 929 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
930 irq_info[irq].evtchn = 0; /* zap event-channel binding */
931
932 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
933 evtchn_to_irq[evtchn] = -1;
934
935 for_each_possible_cpu(cpu) {
936 restore_cpu_virqs(cpu);
937 restore_cpu_ipis(cpu);
938 }
939}
940
e46cdb66
JF
941static struct irq_chip xen_dynamic_chip __read_mostly = {
942 .name = "xen-dyn",
54a353a0
JF
943
944 .disable = disable_dynirq,
e46cdb66
JF
945 .mask = disable_dynirq,
946 .unmask = enable_dynirq,
54a353a0 947
e46cdb66
JF
948 .ack = ack_dynirq,
949 .set_affinity = set_affinity_irq,
950 .retrigger = retrigger_dynirq,
951};
952
38e20b07
SY
953int xen_set_callback_via(uint64_t via)
954{
955 struct xen_hvm_param a;
956 a.domid = DOMID_SELF;
957 a.index = HVM_PARAM_CALLBACK_IRQ;
958 a.value = via;
959 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
960}
961EXPORT_SYMBOL_GPL(xen_set_callback_via);
962
963/* Vector callbacks are better than PCI interrupts to receive event
964 * channel notifications because we can receive vector callbacks on any
965 * vcpu and we don't need PCI support or APIC interactions. */
966void xen_callback_vector(void)
967{
968 int rc;
969 uint64_t callback_via;
970 if (xen_have_vector_callback) {
971 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
972 rc = xen_set_callback_via(callback_via);
973 if (rc) {
974 printk(KERN_ERR "Request for Xen HVM callback vector"
975 " failed.\n");
976 xen_have_vector_callback = 0;
977 return;
978 }
979 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
980 "enabled\n");
981 /* in the restore case the vector has already been allocated */
982 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
983 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
984 }
985}
986
e46cdb66
JF
987void __init xen_init_IRQ(void)
988{
989 int i;
c7a3589e 990
a70c352a
PE
991 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
992 GFP_KERNEL);
28e08861 993 BUG_ON(cpu_evtchn_mask_p == NULL);
e46cdb66
JF
994
995 init_evtchn_cpu_bindings();
996
997 /* No event channels are 'live' right now. */
998 for (i = 0; i < NR_EVENT_CHANNELS; i++)
999 mask_evtchn(i);
1000
38e20b07
SY
1001 if (xen_hvm_domain()) {
1002 xen_callback_vector();
1003 native_init_IRQ();
1004 } else {
1005 irq_ctx_init(smp_processor_id());
1006 }
e46cdb66 1007}