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xen: mask x2APIC feature in PV
[mirror_ubuntu-focal-kernel.git] / drivers / xen / events.c
CommitLineData
e46cdb66
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1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
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20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
0ec53ecf 34#ifdef CONFIG_X86
38e20b07 35#include <asm/desc.h>
e46cdb66
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36#include <asm/ptrace.h>
37#include <asm/irq.h>
792dc4f6 38#include <asm/idle.h>
0794bfc7 39#include <asm/io_apic.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
0ec53ecf
SS
42#endif
43#include <asm/sync_bitops.h>
e46cdb66 44#include <asm/xen/hypercall.h>
8d1b8753 45#include <asm/xen/hypervisor.h>
e46cdb66 46
38e20b07
SY
47#include <xen/xen.h>
48#include <xen/hvm.h>
e04d0d07 49#include <xen/xen-ops.h>
e46cdb66
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50#include <xen/events.h>
51#include <xen/interface/xen.h>
52#include <xen/interface/event_channel.h>
38e20b07
SY
53#include <xen/interface/hvm/hvm_op.h>
54#include <xen/interface/hvm/params.h>
0ec53ecf
SS
55#include <xen/interface/physdev.h>
56#include <xen/interface/sched.h>
57#include <asm/hw_irq.h>
e46cdb66 58
e46cdb66
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59/*
60 * This lock protects updates to the following mapping and reference-count
61 * arrays. The lock does not need to be acquired to read the mapping tables.
62 */
77365948 63static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 64
6cb6537d
IC
65static LIST_HEAD(xen_irq_list_head);
66
e46cdb66 67/* IRQ <-> VIRQ mapping. */
204fba4a 68static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 69
f87e4cac 70/* IRQ <-> IPI mapping */
204fba4a 71static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 72
ced40d0f
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73/* Interrupt types. */
74enum xen_irq_type {
d77bbd4d 75 IRQT_UNBOUND = 0,
f87e4cac
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76 IRQT_PIRQ,
77 IRQT_VIRQ,
78 IRQT_IPI,
79 IRQT_EVTCHN
80};
e46cdb66 81
ced40d0f
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82/*
83 * Packed IRQ information:
84 * type - enum xen_irq_type
85 * event channel - irq->event channel mapping
86 * cpu - cpu this event channel is bound to
87 * index - type-specific information:
dec02dea 88 * PIRQ - physical IRQ, GSI, flags, and owner domain
ced40d0f
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89 * VIRQ - virq number
90 * IPI - IPI vector
91 * EVTCHN -
92 */
088c05a8 93struct irq_info {
6cb6537d 94 struct list_head list;
420eb554 95 int refcnt;
ced40d0f 96 enum xen_irq_type type; /* type */
6cb6537d 97 unsigned irq;
ced40d0f
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98 unsigned short evtchn; /* event channel */
99 unsigned short cpu; /* cpu bound */
100
101 union {
102 unsigned short virq;
103 enum ipi_vector ipi;
104 struct {
7a043f11 105 unsigned short pirq;
ced40d0f 106 unsigned short gsi;
d46a78b0 107 unsigned char flags;
beafbdc1 108 uint16_t domid;
ced40d0f
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109 } pirq;
110 } u;
111};
d46a78b0 112#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 113#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 114
b21ddbf5 115static int *evtchn_to_irq;
bf86ad80 116#ifdef CONFIG_X86
9846ff10 117static unsigned long *pirq_eoi_map;
bf86ad80 118#endif
9846ff10 119static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 120
c81611c4
IC
121/*
122 * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
123 * careful to only use bitops which allow for this (e.g
124 * test_bit/find_first_bit and friends but not __ffs) and to pass
125 * BITS_PER_EVTCHN_WORD as the bitmask length.
126 */
127#define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
128/*
129 * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
130 * array. Primarily to avoid long lines (hence the terse name).
131 */
132#define BM(x) (unsigned long *)(x)
133/* Find the first set bit in a evtchn mask */
134#define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
135
136static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
cb60d114 137 cpu_evtchn_mask);
e46cdb66 138
e46cdb66
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139/* Xen will never allocate port zero for any purpose. */
140#define VALID_EVTCHN(chn) ((chn) != 0)
141
e46cdb66 142static struct irq_chip xen_dynamic_chip;
aaca4964 143static struct irq_chip xen_percpu_chip;
d46a78b0 144static struct irq_chip xen_pirq_chip;
7e186bdd
SS
145static void enable_dynirq(struct irq_data *data);
146static void disable_dynirq(struct irq_data *data);
e46cdb66 147
9158c358
IC
148/* Get info for IRQ */
149static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 150{
c442b806 151 return irq_get_handler_data(irq);
ced40d0f
JF
152}
153
9158c358
IC
154/* Constructors for packed IRQ information. */
155static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 156 unsigned irq,
9158c358
IC
157 enum xen_irq_type type,
158 unsigned short evtchn,
159 unsigned short cpu)
ced40d0f 160{
9158c358
IC
161
162 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
163
164 info->type = type;
6cb6537d 165 info->irq = irq;
9158c358
IC
166 info->evtchn = evtchn;
167 info->cpu = cpu;
3d4cfa37
IC
168
169 evtchn_to_irq[evtchn] = irq;
ced40d0f
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170}
171
9158c358
IC
172static void xen_irq_info_evtchn_init(unsigned irq,
173 unsigned short evtchn)
ced40d0f 174{
9158c358
IC
175 struct irq_info *info = info_for_irq(irq);
176
3d4cfa37 177 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
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178}
179
3d4cfa37
IC
180static void xen_irq_info_ipi_init(unsigned cpu,
181 unsigned irq,
9158c358
IC
182 unsigned short evtchn,
183 enum ipi_vector ipi)
e46cdb66 184{
9158c358
IC
185 struct irq_info *info = info_for_irq(irq);
186
3d4cfa37 187 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
188
189 info->u.ipi = ipi;
3d4cfa37
IC
190
191 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
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192}
193
3d4cfa37
IC
194static void xen_irq_info_virq_init(unsigned cpu,
195 unsigned irq,
9158c358
IC
196 unsigned short evtchn,
197 unsigned short virq)
ced40d0f 198{
9158c358
IC
199 struct irq_info *info = info_for_irq(irq);
200
3d4cfa37 201 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
202
203 info->u.virq = virq;
3d4cfa37
IC
204
205 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
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206}
207
9158c358
IC
208static void xen_irq_info_pirq_init(unsigned irq,
209 unsigned short evtchn,
210 unsigned short pirq,
211 unsigned short gsi,
beafbdc1 212 uint16_t domid,
9158c358 213 unsigned char flags)
ced40d0f 214{
9158c358
IC
215 struct irq_info *info = info_for_irq(irq);
216
3d4cfa37 217 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
218
219 info->u.pirq.pirq = pirq;
220 info->u.pirq.gsi = gsi;
beafbdc1 221 info->u.pirq.domid = domid;
9158c358 222 info->u.pirq.flags = flags;
e46cdb66
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223}
224
225/*
226 * Accessors for packed IRQ information.
227 */
ced40d0f 228static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 229{
110e7c7e
JJ
230 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
231 return 0;
232
ced40d0f 233 return info_for_irq(irq)->evtchn;
e46cdb66
JF
234}
235
d4c04536
IC
236unsigned irq_from_evtchn(unsigned int evtchn)
237{
238 return evtchn_to_irq[evtchn];
239}
240EXPORT_SYMBOL_GPL(irq_from_evtchn);
241
ced40d0f 242static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 243{
ced40d0f
JF
244 struct irq_info *info = info_for_irq(irq);
245
246 BUG_ON(info == NULL);
247 BUG_ON(info->type != IRQT_IPI);
248
249 return info->u.ipi;
250}
251
252static unsigned virq_from_irq(unsigned irq)
253{
254 struct irq_info *info = info_for_irq(irq);
255
256 BUG_ON(info == NULL);
257 BUG_ON(info->type != IRQT_VIRQ);
258
259 return info->u.virq;
260}
261
7a043f11
SS
262static unsigned pirq_from_irq(unsigned irq)
263{
264 struct irq_info *info = info_for_irq(irq);
265
266 BUG_ON(info == NULL);
267 BUG_ON(info->type != IRQT_PIRQ);
268
269 return info->u.pirq.pirq;
270}
271
ced40d0f
JF
272static enum xen_irq_type type_from_irq(unsigned irq)
273{
274 return info_for_irq(irq)->type;
275}
276
277static unsigned cpu_from_irq(unsigned irq)
278{
279 return info_for_irq(irq)->cpu;
280}
281
282static unsigned int cpu_from_evtchn(unsigned int evtchn)
283{
284 int irq = evtchn_to_irq[evtchn];
285 unsigned ret = 0;
286
287 if (irq != -1)
288 ret = cpu_from_irq(irq);
289
290 return ret;
e46cdb66
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291}
292
bf86ad80 293#ifdef CONFIG_X86
9846ff10 294static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 295{
521394e4 296 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 297}
bf86ad80 298#endif
d46a78b0 299
9846ff10
SS
300static bool pirq_needs_eoi_flag(unsigned irq)
301{
302 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
303 BUG_ON(info->type != IRQT_PIRQ);
304
305 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
306}
307
c81611c4
IC
308static inline xen_ulong_t active_evtchns(unsigned int cpu,
309 struct shared_info *sh,
310 unsigned int idx)
e46cdb66 311{
088c05a8 312 return sh->evtchn_pending[idx] &
cb60d114 313 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 314 ~sh->evtchn_mask[idx];
e46cdb66
JF
315}
316
317static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
318{
319 int irq = evtchn_to_irq[chn];
320
321 BUG_ON(irq == -1);
322#ifdef CONFIG_SMP
c9e265e0 323 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
324#endif
325
c81611c4
IC
326 clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
327 set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
e46cdb66 328
ca62ce8c 329 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
330}
331
332static void init_evtchn_cpu_bindings(void)
333{
1c6969ec 334 int i;
e46cdb66 335#ifdef CONFIG_SMP
6cb6537d 336 struct irq_info *info;
10e58084 337
e46cdb66 338 /* By default all event channels notify CPU#0. */
6cb6537d
IC
339 list_for_each_entry(info, &xen_irq_list_head, list) {
340 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 341 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 342 }
e46cdb66
JF
343#endif
344
1c6969ec 345 for_each_possible_cpu(i)
cb60d114
IC
346 memset(per_cpu(cpu_evtchn_mask, i),
347 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
348}
349
e46cdb66
JF
350static inline void clear_evtchn(int port)
351{
352 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 353 sync_clear_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
354}
355
356static inline void set_evtchn(int port)
357{
358 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 359 sync_set_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
360}
361
168d2f46
JF
362static inline int test_evtchn(int port)
363{
364 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 365 return sync_test_bit(port, BM(&s->evtchn_pending[0]));
168d2f46
JF
366}
367
e46cdb66
JF
368
369/**
370 * notify_remote_via_irq - send event to remote end of event channel via irq
371 * @irq: irq of event channel to send event to
372 *
373 * Unlike notify_remote_via_evtchn(), this is safe to use across
374 * save/restore. Notifications on a broken connection are silently
375 * dropped.
376 */
377void notify_remote_via_irq(int irq)
378{
379 int evtchn = evtchn_from_irq(irq);
380
381 if (VALID_EVTCHN(evtchn))
382 notify_remote_via_evtchn(evtchn);
383}
384EXPORT_SYMBOL_GPL(notify_remote_via_irq);
385
386static void mask_evtchn(int port)
387{
388 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 389 sync_set_bit(port, BM(&s->evtchn_mask[0]));
e46cdb66
JF
390}
391
392static void unmask_evtchn(int port)
393{
394 struct shared_info *s = HYPERVISOR_shared_info;
395 unsigned int cpu = get_cpu();
b5e57923 396 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
JF
397
398 BUG_ON(!irqs_disabled());
399
b5e57923
SS
400 if (unlikely((cpu != cpu_from_evtchn(port))))
401 do_hypercall = 1;
c26377e6
DV
402 else {
403 /*
404 * Need to clear the mask before checking pending to
405 * avoid a race with an event becoming pending.
406 *
407 * EVTCHNOP_unmask will only trigger an upcall if the
408 * mask bit was set, so if a hypercall is needed
409 * remask the event.
410 */
411 sync_clear_bit(port, BM(&s->evtchn_mask[0]));
c81611c4 412 evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
b5e57923 413
c26377e6
DV
414 if (unlikely(evtchn_pending && xen_hvm_domain())) {
415 sync_set_bit(port, BM(&s->evtchn_mask[0]));
416 do_hypercall = 1;
417 }
418 }
b5e57923
SS
419
420 /* Slow path (hypercall) if this is a non-local port or if this is
421 * an hvm domain and an event is pending (hvm domains don't have
422 * their own implementation of irq_enable). */
423 if (do_hypercall) {
e46cdb66
JF
424 struct evtchn_unmask unmask = { .port = port };
425 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
426 } else {
780f36d8 427 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66 428
e46cdb66
JF
429 /*
430 * The following is basically the equivalent of
431 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
432 * the interrupt edge' if the channel is masked.
433 */
b5e57923 434 if (evtchn_pending &&
c81611c4
IC
435 !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
436 BM(&vcpu_info->evtchn_pending_sel)))
e46cdb66
JF
437 vcpu_info->evtchn_upcall_pending = 1;
438 }
439
440 put_cpu();
441}
442
6cb6537d
IC
443static void xen_irq_init(unsigned irq)
444{
445 struct irq_info *info;
b5328cd1 446#ifdef CONFIG_SMP
6cb6537d
IC
447 struct irq_desc *desc = irq_to_desc(irq);
448
449 /* By default all event channels notify CPU#0. */
450 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 451#endif
6cb6537d 452
ca62ce8c
IC
453 info = kzalloc(sizeof(*info), GFP_KERNEL);
454 if (info == NULL)
455 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
456
457 info->type = IRQT_UNBOUND;
420eb554 458 info->refcnt = -1;
6cb6537d 459
c442b806 460 irq_set_handler_data(irq, info);
ca62ce8c 461
6cb6537d
IC
462 list_add_tail(&info->list, &xen_irq_list_head);
463}
464
7bee9768 465static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 466{
89911501
IC
467 int first = 0;
468 int irq;
0794bfc7
KRW
469
470#ifdef CONFIG_X86_IO_APIC
89911501
IC
471 /*
472 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 473 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
474 * e.g. those corresponding to event channels or MSIs
475 * etc. from the range above those "real" GSIs to avoid
476 * collisions.
477 */
478 if (xen_initial_domain() || xen_hvm_domain())
479 first = get_nr_irqs_gsi();
0794bfc7
KRW
480#endif
481
89911501 482 irq = irq_alloc_desc_from(first, -1);
3a69e916 483
e6599225
KRW
484 if (irq >= 0)
485 xen_irq_init(irq);
ced40d0f 486
e46cdb66 487 return irq;
d46a78b0
JF
488}
489
7bee9768 490static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
491{
492 int irq;
493
89911501
IC
494 /*
495 * A PV guest has no concept of a GSI (since it has no ACPI
496 * nor access to/knowledge of the physical APICs). Therefore
497 * all IRQs are dynamically allocated from the entire IRQ
498 * space.
499 */
500 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
501 return xen_allocate_irq_dynamic();
502
503 /* Legacy IRQ descriptors are already allocated by the arch. */
504 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
505 irq = gsi;
506 else
507 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 508
6cb6537d 509 xen_irq_init(irq);
c9df1ce5
IC
510
511 return irq;
512}
513
514static void xen_free_irq(unsigned irq)
515{
c442b806 516 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 517
94032c50
KRW
518 if (WARN_ON(!info))
519 return;
520
6cb6537d 521 list_del(&info->list);
9158c358 522
c442b806 523 irq_set_handler_data(irq, NULL);
ca62ce8c 524
420eb554
DDG
525 WARN_ON(info->refcnt > 0);
526
ca62ce8c
IC
527 kfree(info);
528
72146104
IC
529 /* Legacy IRQ descriptors are managed by the arch. */
530 if (irq < NR_IRQS_LEGACY)
531 return;
532
c9df1ce5
IC
533 irq_free_desc(irq);
534}
535
d46a78b0
JF
536static void pirq_query_unmask(int irq)
537{
538 struct physdev_irq_status_query irq_status;
539 struct irq_info *info = info_for_irq(irq);
540
541 BUG_ON(info->type != IRQT_PIRQ);
542
7a043f11 543 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
544 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
545 irq_status.flags = 0;
546
547 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
548 if (irq_status.flags & XENIRQSTAT_needs_eoi)
549 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
550}
551
552static bool probing_irq(int irq)
553{
554 struct irq_desc *desc = irq_to_desc(irq);
555
556 return desc && desc->action == NULL;
557}
558
7e186bdd
SS
559static void eoi_pirq(struct irq_data *data)
560{
561 int evtchn = evtchn_from_irq(data->irq);
562 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
563 int rc = 0;
564
565 irq_move_irq(data);
566
567 if (VALID_EVTCHN(evtchn))
568 clear_evtchn(evtchn);
569
570 if (pirq_needs_eoi(data->irq)) {
571 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
572 WARN_ON(rc);
573 }
574}
575
576static void mask_ack_pirq(struct irq_data *data)
577{
578 disable_dynirq(data);
579 eoi_pirq(data);
580}
581
c9e265e0 582static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
583{
584 struct evtchn_bind_pirq bind_pirq;
585 struct irq_info *info = info_for_irq(irq);
586 int evtchn = evtchn_from_irq(irq);
15ebbb82 587 int rc;
d46a78b0
JF
588
589 BUG_ON(info->type != IRQT_PIRQ);
590
591 if (VALID_EVTCHN(evtchn))
592 goto out;
593
7a043f11 594 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 595 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
596 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
597 BIND_PIRQ__WILL_SHARE : 0;
598 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
599 if (rc != 0) {
d46a78b0
JF
600 if (!probing_irq(irq))
601 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
602 irq);
603 return 0;
604 }
605 evtchn = bind_pirq.port;
606
607 pirq_query_unmask(irq);
608
609 evtchn_to_irq[evtchn] = irq;
610 bind_evtchn_to_cpu(evtchn, 0);
611 info->evtchn = evtchn;
612
613out:
614 unmask_evtchn(evtchn);
7e186bdd 615 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
616
617 return 0;
618}
619
c9e265e0
TG
620static unsigned int startup_pirq(struct irq_data *data)
621{
622 return __startup_pirq(data->irq);
623}
624
625static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
626{
627 struct evtchn_close close;
c9e265e0 628 unsigned int irq = data->irq;
d46a78b0
JF
629 struct irq_info *info = info_for_irq(irq);
630 int evtchn = evtchn_from_irq(irq);
631
632 BUG_ON(info->type != IRQT_PIRQ);
633
634 if (!VALID_EVTCHN(evtchn))
635 return;
636
637 mask_evtchn(evtchn);
638
639 close.port = evtchn;
640 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
641 BUG();
642
643 bind_evtchn_to_cpu(evtchn, 0);
644 evtchn_to_irq[evtchn] = -1;
645 info->evtchn = 0;
646}
647
c9e265e0 648static void enable_pirq(struct irq_data *data)
d46a78b0 649{
c9e265e0 650 startup_pirq(data);
d46a78b0
JF
651}
652
c9e265e0 653static void disable_pirq(struct irq_data *data)
d46a78b0 654{
7e186bdd 655 disable_dynirq(data);
d46a78b0
JF
656}
657
68c2c39a 658int xen_irq_from_gsi(unsigned gsi)
d46a78b0 659{
6cb6537d 660 struct irq_info *info;
d46a78b0 661
6cb6537d
IC
662 list_for_each_entry(info, &xen_irq_list_head, list) {
663 if (info->type != IRQT_PIRQ)
d46a78b0
JF
664 continue;
665
6cb6537d
IC
666 if (info->u.pirq.gsi == gsi)
667 return info->irq;
d46a78b0
JF
668 }
669
670 return -1;
671}
68c2c39a 672EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 673
653378ac
IC
674/*
675 * Do not make any assumptions regarding the relationship between the
676 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
677 *
678 * Note: We don't assign an event channel until the irq actually started
679 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
680 *
681 * Shareable implies level triggered, not shareable implies edge
682 * triggered here.
d46a78b0 683 */
f4d0635b
IC
684int xen_bind_pirq_gsi_to_irq(unsigned gsi,
685 unsigned pirq, int shareable, char *name)
d46a78b0 686{
a0e18116 687 int irq = -1;
d46a78b0
JF
688 struct physdev_irq irq_op;
689
77365948 690 mutex_lock(&irq_mapping_update_lock);
d46a78b0 691
68c2c39a 692 irq = xen_irq_from_gsi(gsi);
d46a78b0 693 if (irq != -1) {
7a043f11 694 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 695 irq, gsi);
420eb554 696 goto out;
d46a78b0
JF
697 }
698
c9df1ce5 699 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
700 if (irq < 0)
701 goto out;
d46a78b0 702
d46a78b0 703 irq_op.irq = irq;
b5401a96
AN
704 irq_op.vector = 0;
705
706 /* Only the privileged domain can do this. For non-priv, the pcifront
707 * driver provides a PCI bus that does the call to do exactly
708 * this in the priv domain. */
709 if (xen_initial_domain() &&
710 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 711 xen_free_irq(irq);
d46a78b0
JF
712 irq = -ENOSPC;
713 goto out;
714 }
715
dec02dea 716 xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 717 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 718
7e186bdd
SS
719 pirq_query_unmask(irq);
720 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
721 * type of interrupt: if the interrupt is an edge triggered
722 * interrupt we use handle_edge_irq.
7e186bdd 723 *
e5ac0bda
SS
724 * On the other hand if the interrupt is level triggered we use
725 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 726 * interrupts.
e5ac0bda 727 *
7e186bdd
SS
728 * Depending on the Xen version, pirq_needs_eoi might return true
729 * not only for level triggered interrupts but for edge triggered
730 * interrupts too. In any case Xen always honors the eoi mechanism,
731 * not injecting any more pirqs of the same kind if the first one
732 * hasn't received an eoi yet. Therefore using the fasteoi handler
733 * is the right choice either way.
734 */
e5ac0bda 735 if (shareable)
7e186bdd
SS
736 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
737 handle_fasteoi_irq, name);
738 else
739 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
740 handle_edge_irq, name);
741
d46a78b0 742out:
77365948 743 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
744
745 return irq;
746}
747
f731e3ef 748#ifdef CONFIG_PCI_MSI
bf480d95 749int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 750{
5cad61a6 751 int rc;
cbf6aa89 752 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 753
bf480d95 754 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 755 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 756
5cad61a6
IC
757 WARN_ONCE(rc == -ENOSYS,
758 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
759
760 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
761}
762
bf480d95 763int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 764 int pirq, const char *name, domid_t domid)
809f9267 765{
bf480d95 766 int irq, ret;
4b41df7f 767
77365948 768 mutex_lock(&irq_mapping_update_lock);
809f9267 769
4b41df7f 770 irq = xen_allocate_irq_dynamic();
e6599225 771 if (irq < 0)
bb5d079a 772 goto out;
809f9267 773
7e186bdd
SS
774 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
775 name);
809f9267 776
dec02dea 777 xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0);
5f6fb454 778 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
779 if (ret < 0)
780 goto error_irq;
809f9267 781out:
77365948 782 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 783 return irq;
bf480d95 784error_irq:
77365948 785 mutex_unlock(&irq_mapping_update_lock);
bf480d95 786 xen_free_irq(irq);
e6599225 787 return ret;
809f9267 788}
f731e3ef
QH
789#endif
790
b5401a96
AN
791int xen_destroy_irq(int irq)
792{
793 struct irq_desc *desc;
38aa66fc
JF
794 struct physdev_unmap_pirq unmap_irq;
795 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
796 int rc = -ENOENT;
797
77365948 798 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
799
800 desc = irq_to_desc(irq);
801 if (!desc)
802 goto out;
803
38aa66fc 804 if (xen_initial_domain()) {
12334715 805 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 806 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 807 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
808 /* If another domain quits without making the pci_disable_msix
809 * call, the Xen hypervisor takes care of freeing the PIRQs
810 * (free_domain_pirqs).
811 */
812 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
813 printk(KERN_INFO "domain %d does not have %d anymore\n",
814 info->u.pirq.domid, info->u.pirq.pirq);
815 else if (rc) {
38aa66fc
JF
816 printk(KERN_WARNING "unmap irq failed %d\n", rc);
817 goto out;
818 }
819 }
b5401a96 820
c9df1ce5 821 xen_free_irq(irq);
b5401a96
AN
822
823out:
77365948 824 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
825 return rc;
826}
827
af42b8d1 828int xen_irq_from_pirq(unsigned pirq)
d46a78b0 829{
69c358ce 830 int irq;
d46a78b0 831
69c358ce 832 struct irq_info *info;
e46cdb66 833
77365948 834 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
835
836 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 837 if (info->type != IRQT_PIRQ)
69c358ce
IC
838 continue;
839 irq = info->irq;
840 if (info->u.pirq.pirq == pirq)
841 goto out;
842 }
843 irq = -1;
844out:
77365948 845 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
846
847 return irq;
af42b8d1
SS
848}
849
e6197acc
KRW
850
851int xen_pirq_from_irq(unsigned irq)
852{
853 return pirq_from_irq(irq);
854}
855EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 856int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
857{
858 int irq;
859
77365948 860 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
861
862 irq = evtchn_to_irq[evtchn];
863
864 if (irq == -1) {
c9df1ce5 865 irq = xen_allocate_irq_dynamic();
68ba45ff 866 if (irq < 0)
7bee9768 867 goto out;
e46cdb66 868
c442b806 869 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 870 handle_edge_irq, "event");
e46cdb66 871
9158c358 872 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
873 } else {
874 struct irq_info *info = info_for_irq(irq);
875 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66 876 }
a8636c0b 877 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
e46cdb66 878
7bee9768 879out:
77365948 880 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
881
882 return irq;
883}
b536b4b9 884EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 885
f87e4cac
JF
886static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
887{
888 struct evtchn_bind_ipi bind_ipi;
889 int evtchn, irq;
890
77365948 891 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
892
893 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 894
f87e4cac 895 if (irq == -1) {
c9df1ce5 896 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
897 if (irq < 0)
898 goto out;
899
c442b806 900 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 901 handle_percpu_irq, "ipi");
f87e4cac
JF
902
903 bind_ipi.vcpu = cpu;
904 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
905 &bind_ipi) != 0)
906 BUG();
907 evtchn = bind_ipi.port;
908
3d4cfa37 909 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
910
911 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
912 } else {
913 struct irq_info *info = info_for_irq(irq);
914 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
915 }
916
f87e4cac 917 out:
77365948 918 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
919 return irq;
920}
921
2e820f58
IC
922static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
923 unsigned int remote_port)
924{
925 struct evtchn_bind_interdomain bind_interdomain;
926 int err;
927
928 bind_interdomain.remote_dom = remote_domain;
929 bind_interdomain.remote_port = remote_port;
930
931 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
932 &bind_interdomain);
933
934 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
935}
936
62cc5fc7
OH
937static int find_virq(unsigned int virq, unsigned int cpu)
938{
939 struct evtchn_status status;
940 int port, rc = -ENOENT;
941
942 memset(&status, 0, sizeof(status));
943 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
944 status.dom = DOMID_SELF;
945 status.port = port;
946 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
947 if (rc < 0)
948 continue;
949 if (status.status != EVTCHNSTAT_virq)
950 continue;
951 if (status.u.virq == virq && status.vcpu == cpu) {
952 rc = port;
953 break;
954 }
955 }
956 return rc;
957}
f87e4cac 958
4fe7d5a7 959int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
960{
961 struct evtchn_bind_virq bind_virq;
62cc5fc7 962 int evtchn, irq, ret;
e46cdb66 963
77365948 964 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
965
966 irq = per_cpu(virq_to_irq, cpu)[virq];
967
968 if (irq == -1) {
c9df1ce5 969 irq = xen_allocate_irq_dynamic();
68ba45ff 970 if (irq < 0)
7bee9768 971 goto out;
a52521f1 972
c442b806 973 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
974 handle_percpu_irq, "virq");
975
e46cdb66
JF
976 bind_virq.virq = virq;
977 bind_virq.vcpu = cpu;
62cc5fc7
OH
978 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
979 &bind_virq);
980 if (ret == 0)
981 evtchn = bind_virq.port;
982 else {
983 if (ret == -EEXIST)
984 ret = find_virq(virq, cpu);
985 BUG_ON(ret < 0);
986 evtchn = ret;
987 }
e46cdb66 988
3d4cfa37 989 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
990
991 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
992 } else {
993 struct irq_info *info = info_for_irq(irq);
994 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
995 }
996
7bee9768 997out:
77365948 998 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
999
1000 return irq;
1001}
1002
1003static void unbind_from_irq(unsigned int irq)
1004{
1005 struct evtchn_close close;
1006 int evtchn = evtchn_from_irq(irq);
420eb554 1007 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 1008
94032c50
KRW
1009 if (WARN_ON(!info))
1010 return;
1011
77365948 1012 mutex_lock(&irq_mapping_update_lock);
e46cdb66 1013
420eb554
DDG
1014 if (info->refcnt > 0) {
1015 info->refcnt--;
1016 if (info->refcnt != 0)
1017 goto done;
1018 }
1019
d77bbd4d 1020 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
1021 close.port = evtchn;
1022 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
1023 BUG();
1024
1025 switch (type_from_irq(irq)) {
1026 case IRQT_VIRQ:
1027 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1028 [virq_from_irq(irq)] = -1;
e46cdb66 1029 break;
d68d82af
AN
1030 case IRQT_IPI:
1031 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1032 [ipi_from_irq(irq)] = -1;
d68d82af 1033 break;
e46cdb66
JF
1034 default:
1035 break;
1036 }
1037
1038 /* Closed ports are implicitly re-bound to VCPU0. */
1039 bind_evtchn_to_cpu(evtchn, 0);
1040
1041 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1042 }
1043
ca62ce8c 1044 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1045
9158c358 1046 xen_free_irq(irq);
e46cdb66 1047
420eb554 1048 done:
77365948 1049 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1050}
1051
1052int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1053 irq_handler_t handler,
e46cdb66
JF
1054 unsigned long irqflags,
1055 const char *devname, void *dev_id)
1056{
361ae8cb 1057 int irq, retval;
e46cdb66
JF
1058
1059 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1060 if (irq < 0)
1061 return irq;
e46cdb66
JF
1062 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1063 if (retval != 0) {
1064 unbind_from_irq(irq);
1065 return retval;
1066 }
1067
1068 return irq;
1069}
1070EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1071
2e820f58
IC
1072int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1073 unsigned int remote_port,
1074 irq_handler_t handler,
1075 unsigned long irqflags,
1076 const char *devname,
1077 void *dev_id)
1078{
1079 int irq, retval;
1080
1081 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1082 if (irq < 0)
1083 return irq;
1084
1085 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1086 if (retval != 0) {
1087 unbind_from_irq(irq);
1088 return retval;
1089 }
1090
1091 return irq;
1092}
1093EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1094
e46cdb66 1095int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1096 irq_handler_t handler,
e46cdb66
JF
1097 unsigned long irqflags, const char *devname, void *dev_id)
1098{
361ae8cb 1099 int irq, retval;
e46cdb66
JF
1100
1101 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1102 if (irq < 0)
1103 return irq;
e46cdb66
JF
1104 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1105 if (retval != 0) {
1106 unbind_from_irq(irq);
1107 return retval;
1108 }
1109
1110 return irq;
1111}
1112EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1113
f87e4cac
JF
1114int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1115 unsigned int cpu,
1116 irq_handler_t handler,
1117 unsigned long irqflags,
1118 const char *devname,
1119 void *dev_id)
1120{
1121 int irq, retval;
1122
1123 irq = bind_ipi_to_irq(ipi, cpu);
1124 if (irq < 0)
1125 return irq;
1126
9bab0b7f 1127 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1128 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1129 if (retval != 0) {
1130 unbind_from_irq(irq);
1131 return retval;
1132 }
1133
1134 return irq;
1135}
1136
e46cdb66
JF
1137void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1138{
94032c50
KRW
1139 struct irq_info *info = irq_get_handler_data(irq);
1140
1141 if (WARN_ON(!info))
1142 return;
e46cdb66
JF
1143 free_irq(irq, dev_id);
1144 unbind_from_irq(irq);
1145}
1146EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1147
420eb554
DDG
1148int evtchn_make_refcounted(unsigned int evtchn)
1149{
1150 int irq = evtchn_to_irq[evtchn];
1151 struct irq_info *info;
1152
1153 if (irq == -1)
1154 return -ENOENT;
1155
1156 info = irq_get_handler_data(irq);
1157
1158 if (!info)
1159 return -ENOENT;
1160
1161 WARN_ON(info->refcnt != -1);
1162
1163 info->refcnt = 1;
1164
1165 return 0;
1166}
1167EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1168
1169int evtchn_get(unsigned int evtchn)
1170{
1171 int irq;
1172 struct irq_info *info;
1173 int err = -ENOENT;
1174
c3b3f16d
DDG
1175 if (evtchn >= NR_EVENT_CHANNELS)
1176 return -EINVAL;
1177
420eb554
DDG
1178 mutex_lock(&irq_mapping_update_lock);
1179
1180 irq = evtchn_to_irq[evtchn];
1181 if (irq == -1)
1182 goto done;
1183
1184 info = irq_get_handler_data(irq);
1185
1186 if (!info)
1187 goto done;
1188
1189 err = -EINVAL;
1190 if (info->refcnt <= 0)
1191 goto done;
1192
1193 info->refcnt++;
1194 err = 0;
1195 done:
1196 mutex_unlock(&irq_mapping_update_lock);
1197
1198 return err;
1199}
1200EXPORT_SYMBOL_GPL(evtchn_get);
1201
1202void evtchn_put(unsigned int evtchn)
1203{
1204 int irq = evtchn_to_irq[evtchn];
1205 if (WARN_ON(irq == -1))
1206 return;
1207 unbind_from_irq(irq);
1208}
1209EXPORT_SYMBOL_GPL(evtchn_put);
1210
f87e4cac
JF
1211void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1212{
1213 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1214 BUG_ON(irq < 0);
1215 notify_remote_via_irq(irq);
1216}
1217
ee523ca1
JF
1218irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1219{
1220 struct shared_info *sh = HYPERVISOR_shared_info;
1221 int cpu = smp_processor_id();
c81611c4 1222 xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1223 int i;
1224 unsigned long flags;
1225 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1226 struct vcpu_info *v;
ee523ca1
JF
1227
1228 spin_lock_irqsave(&debug_lock, flags);
1229
cb52e6d9 1230 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1231
1232 for_each_online_cpu(i) {
cb52e6d9
IC
1233 int pending;
1234 v = per_cpu(xen_vcpu, i);
1235 pending = (get_irq_regs() && i == cpu)
1236 ? xen_irqs_disabled(get_irq_regs())
1237 : v->evtchn_upcall_mask;
c81611c4 1238 printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
cb52e6d9
IC
1239 pending, v->evtchn_upcall_pending,
1240 (int)(sizeof(v->evtchn_pending_sel)*2),
1241 v->evtchn_pending_sel);
1242 }
1243 v = per_cpu(xen_vcpu, cpu);
1244
1245 printk("\npending:\n ");
1246 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
c81611c4
IC
1247 printk("%0*"PRI_xen_ulong"%s",
1248 (int)sizeof(sh->evtchn_pending[0])*2,
cb52e6d9
IC
1249 sh->evtchn_pending[i],
1250 i % 8 == 0 ? "\n " : " ");
1251 printk("\nglobal mask:\n ");
1252 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4 1253 printk("%0*"PRI_xen_ulong"%s",
cb52e6d9
IC
1254 (int)(sizeof(sh->evtchn_mask[0])*2),
1255 sh->evtchn_mask[i],
1256 i % 8 == 0 ? "\n " : " ");
1257
1258 printk("\nglobally unmasked:\n ");
1259 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4
IC
1260 printk("%0*"PRI_xen_ulong"%s",
1261 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9
IC
1262 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1263 i % 8 == 0 ? "\n " : " ");
1264
1265 printk("\nlocal cpu%d mask:\n ", cpu);
c81611c4
IC
1266 for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
1267 printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
cb52e6d9
IC
1268 cpu_evtchn[i],
1269 i % 8 == 0 ? "\n " : " ");
1270
1271 printk("\nlocally unmasked:\n ");
1272 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
c81611c4 1273 xen_ulong_t pending = sh->evtchn_pending[i]
cb52e6d9
IC
1274 & ~sh->evtchn_mask[i]
1275 & cpu_evtchn[i];
c81611c4
IC
1276 printk("%0*"PRI_xen_ulong"%s",
1277 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9 1278 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1279 }
ee523ca1
JF
1280
1281 printk("\npending list:\n");
cb52e6d9 1282 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
c81611c4
IC
1283 if (sync_test_bit(i, BM(sh->evtchn_pending))) {
1284 int word_idx = i / BITS_PER_EVTCHN_WORD;
cb52e6d9 1285 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1286 cpu_from_evtchn(i), i,
cb52e6d9 1287 evtchn_to_irq[i],
c81611c4 1288 sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
cb52e6d9 1289 ? "" : " l2-clear",
c81611c4 1290 !sync_test_bit(i, BM(sh->evtchn_mask))
cb52e6d9 1291 ? "" : " globally-masked",
c81611c4 1292 sync_test_bit(i, BM(cpu_evtchn))
cb52e6d9 1293 ? "" : " locally-masked");
ee523ca1
JF
1294 }
1295 }
1296
1297 spin_unlock_irqrestore(&debug_lock, flags);
1298
1299 return IRQ_HANDLED;
1300}
1301
245b2e70 1302static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1303static DEFINE_PER_CPU(unsigned int, current_word_idx);
1304static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1305
ab7f863e
SR
1306/*
1307 * Mask out the i least significant bits of w
1308 */
c81611c4 1309#define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
245b2e70 1310
e46cdb66
JF
1311/*
1312 * Search the CPUs pending events bitmasks. For each one found, map
1313 * the event number to an irq, and feed it into do_IRQ() for
1314 * handling.
1315 *
1316 * Xen uses a two-level bitmap to speed searching. The first level is
1317 * a bitset of words which contain pending event bits. The second
1318 * level is a bitset of pending events themselves.
1319 */
38e20b07 1320static void __xen_evtchn_do_upcall(void)
e46cdb66 1321{
24b51c2f 1322 int start_word_idx, start_bit_idx;
ab7f863e 1323 int word_idx, bit_idx;
24b51c2f 1324 int i;
e46cdb66
JF
1325 int cpu = get_cpu();
1326 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1327 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1328 unsigned count;
e46cdb66 1329
229664be 1330 do {
c81611c4 1331 xen_ulong_t pending_words;
e46cdb66 1332
229664be 1333 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1334
b2e4ae69 1335 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1336 goto out;
e46cdb66 1337
c81611c4
IC
1338 /*
1339 * Master flag must be cleared /before/ clearing
1340 * selector flag. xchg_xen_ulong must contain an
1341 * appropriate barrier.
1342 */
1343 pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1344
24b51c2f
KF
1345 start_word_idx = __this_cpu_read(current_word_idx);
1346 start_bit_idx = __this_cpu_read(current_bit_idx);
1347
1348 word_idx = start_word_idx;
ab7f863e 1349
24b51c2f 1350 for (i = 0; pending_words != 0; i++) {
c81611c4
IC
1351 xen_ulong_t pending_bits;
1352 xen_ulong_t words;
229664be 1353
ab7f863e
SR
1354 words = MASK_LSBS(pending_words, word_idx);
1355
1356 /*
ada6814c 1357 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1358 */
1359 if (words == 0) {
ada6814c
KF
1360 word_idx = 0;
1361 bit_idx = 0;
ab7f863e
SR
1362 continue;
1363 }
c81611c4 1364 word_idx = EVTCHN_FIRST_BIT(words);
229664be 1365
24b51c2f
KF
1366 pending_bits = active_evtchns(cpu, s, word_idx);
1367 bit_idx = 0; /* usually scan entire word from start */
1368 if (word_idx == start_word_idx) {
1369 /* We scan the starting word in two parts */
1370 if (i == 0)
1371 /* 1st time: start in the middle */
1372 bit_idx = start_bit_idx;
1373 else
1374 /* 2nd time: mask bits done already */
1375 bit_idx &= (1UL << start_bit_idx) - 1;
1376 }
1377
ab7f863e 1378 do {
c81611c4 1379 xen_ulong_t bits;
ab7f863e 1380 int port, irq;
ca4dbc66 1381 struct irq_desc *desc;
229664be 1382
ab7f863e
SR
1383 bits = MASK_LSBS(pending_bits, bit_idx);
1384
1385 /* If we masked out all events, move on. */
ada6814c 1386 if (bits == 0)
ab7f863e 1387 break;
ab7f863e 1388
c81611c4 1389 bit_idx = EVTCHN_FIRST_BIT(bits);
ab7f863e
SR
1390
1391 /* Process port. */
c81611c4 1392 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
ab7f863e
SR
1393 irq = evtchn_to_irq[port];
1394
ca4dbc66
EB
1395 if (irq != -1) {
1396 desc = irq_to_desc(irq);
1397 if (desc)
1398 generic_handle_irq_desc(irq, desc);
1399 }
ab7f863e 1400
c81611c4 1401 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
ada6814c
KF
1402
1403 /* Next caller starts at last processed + 1 */
1404 __this_cpu_write(current_word_idx,
1405 bit_idx ? word_idx :
c81611c4 1406 (word_idx+1) % BITS_PER_EVTCHN_WORD);
ada6814c
KF
1407 __this_cpu_write(current_bit_idx, bit_idx);
1408 } while (bit_idx != 0);
ab7f863e 1409
24b51c2f
KF
1410 /* Scan start_l1i twice; all others once. */
1411 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1412 pending_words &= ~(1UL << word_idx);
ada6814c 1413
c81611c4 1414 word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
e46cdb66 1415 }
e46cdb66 1416
229664be
JF
1417 BUG_ON(!irqs_disabled());
1418
780f36d8
CL
1419 count = __this_cpu_read(xed_nesting_count);
1420 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1421 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1422
1423out:
38e20b07
SY
1424
1425 put_cpu();
1426}
1427
1428void xen_evtchn_do_upcall(struct pt_regs *regs)
1429{
1430 struct pt_regs *old_regs = set_irq_regs(regs);
1431
772aebce 1432 irq_enter();
0ec53ecf 1433#ifdef CONFIG_X86
38e20b07 1434 exit_idle();
0ec53ecf 1435#endif
38e20b07
SY
1436
1437 __xen_evtchn_do_upcall();
1438
3445a8fd
JF
1439 irq_exit();
1440 set_irq_regs(old_regs);
38e20b07 1441}
3445a8fd 1442
38e20b07
SY
1443void xen_hvm_evtchn_do_upcall(void)
1444{
1445 __xen_evtchn_do_upcall();
e46cdb66 1446}
183d03cc 1447EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1448
eb1e305f
JF
1449/* Rebind a new event channel to an existing irq. */
1450void rebind_evtchn_irq(int evtchn, int irq)
1451{
d77bbd4d
JF
1452 struct irq_info *info = info_for_irq(irq);
1453
94032c50
KRW
1454 if (WARN_ON(!info))
1455 return;
1456
eb1e305f
JF
1457 /* Make sure the irq is masked, since the new event channel
1458 will also be masked. */
1459 disable_irq(irq);
1460
77365948 1461 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1462
1463 /* After resume the irq<->evtchn mappings are all cleared out */
1464 BUG_ON(evtchn_to_irq[evtchn] != -1);
1465 /* Expect irq to have been bound before,
d77bbd4d
JF
1466 so there should be a proper type */
1467 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1468
9158c358 1469 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1470
77365948 1471 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1472
1473 /* new event channels are always bound to cpu 0 */
0de26520 1474 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1475
1476 /* Unmask the event channel. */
1477 enable_irq(irq);
1478}
1479
e46cdb66 1480/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1481static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1482{
1483 struct evtchn_bind_vcpu bind_vcpu;
1484 int evtchn = evtchn_from_irq(irq);
1485
be49472f
IC
1486 if (!VALID_EVTCHN(evtchn))
1487 return -1;
1488
1489 /*
1490 * Events delivered via platform PCI interrupts are always
1491 * routed to vcpu 0 and hence cannot be rebound.
1492 */
1493 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1494 return -1;
e46cdb66
JF
1495
1496 /* Send future instances of this interrupt to other vcpu. */
1497 bind_vcpu.port = evtchn;
1498 bind_vcpu.vcpu = tcpu;
1499
1500 /*
1501 * If this fails, it usually just indicates that we're dealing with a
1502 * virq or IPI channel, which don't actually need to be rebound. Ignore
1503 * it, but don't do the xenlinux-level rebind in that case.
1504 */
1505 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1506 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1507
d5dedd45
YL
1508 return 0;
1509}
e46cdb66 1510
c9e265e0
TG
1511static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1512 bool force)
e46cdb66 1513{
0de26520 1514 unsigned tcpu = cpumask_first(dest);
d5dedd45 1515
c9e265e0 1516 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1517}
1518
642e0c88
IY
1519int resend_irq_on_evtchn(unsigned int irq)
1520{
1521 int masked, evtchn = evtchn_from_irq(irq);
1522 struct shared_info *s = HYPERVISOR_shared_info;
1523
1524 if (!VALID_EVTCHN(evtchn))
1525 return 1;
1526
c81611c4
IC
1527 masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
1528 sync_set_bit(evtchn, BM(s->evtchn_pending));
642e0c88
IY
1529 if (!masked)
1530 unmask_evtchn(evtchn);
1531
1532 return 1;
1533}
1534
c9e265e0 1535static void enable_dynirq(struct irq_data *data)
e46cdb66 1536{
c9e265e0 1537 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1538
1539 if (VALID_EVTCHN(evtchn))
1540 unmask_evtchn(evtchn);
1541}
1542
c9e265e0 1543static void disable_dynirq(struct irq_data *data)
e46cdb66 1544{
c9e265e0 1545 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1546
1547 if (VALID_EVTCHN(evtchn))
1548 mask_evtchn(evtchn);
1549}
1550
c9e265e0 1551static void ack_dynirq(struct irq_data *data)
e46cdb66 1552{
c9e265e0 1553 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1554
7e186bdd 1555 irq_move_irq(data);
e46cdb66
JF
1556
1557 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1558 clear_evtchn(evtchn);
1559}
1560
1561static void mask_ack_dynirq(struct irq_data *data)
1562{
1563 disable_dynirq(data);
1564 ack_dynirq(data);
e46cdb66
JF
1565}
1566
c9e265e0 1567static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1568{
c9e265e0 1569 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1570 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1571 int ret = 0;
1572
1573 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1574 int masked;
1575
c81611c4
IC
1576 masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
1577 sync_set_bit(evtchn, BM(sh->evtchn_pending));
ee8fa1c6
JF
1578 if (!masked)
1579 unmask_evtchn(evtchn);
e46cdb66
JF
1580 ret = 1;
1581 }
1582
1583 return ret;
1584}
1585
0a85226f 1586static void restore_pirqs(void)
9a069c33
SS
1587{
1588 int pirq, rc, irq, gsi;
1589 struct physdev_map_pirq map_irq;
69c358ce 1590 struct irq_info *info;
9a069c33 1591
69c358ce
IC
1592 list_for_each_entry(info, &xen_irq_list_head, list) {
1593 if (info->type != IRQT_PIRQ)
9a069c33
SS
1594 continue;
1595
69c358ce
IC
1596 pirq = info->u.pirq.pirq;
1597 gsi = info->u.pirq.gsi;
1598 irq = info->irq;
1599
9a069c33
SS
1600 /* save/restore of PT devices doesn't work, so at this point the
1601 * only devices present are GSI based emulated devices */
9a069c33
SS
1602 if (!gsi)
1603 continue;
1604
1605 map_irq.domid = DOMID_SELF;
1606 map_irq.type = MAP_PIRQ_TYPE_GSI;
1607 map_irq.index = gsi;
1608 map_irq.pirq = pirq;
1609
1610 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1611 if (rc) {
1612 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1613 gsi, irq, pirq, rc);
9158c358 1614 xen_free_irq(irq);
9a069c33
SS
1615 continue;
1616 }
1617
1618 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1619
c9e265e0 1620 __startup_pirq(irq);
9a069c33
SS
1621 }
1622}
1623
0e91398f
JF
1624static void restore_cpu_virqs(unsigned int cpu)
1625{
1626 struct evtchn_bind_virq bind_virq;
1627 int virq, irq, evtchn;
1628
1629 for (virq = 0; virq < NR_VIRQS; virq++) {
1630 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1631 continue;
1632
ced40d0f 1633 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1634
1635 /* Get a new binding from Xen. */
1636 bind_virq.virq = virq;
1637 bind_virq.vcpu = cpu;
1638 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1639 &bind_virq) != 0)
1640 BUG();
1641 evtchn = bind_virq.port;
1642
1643 /* Record the new mapping. */
3d4cfa37 1644 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1645 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1646 }
1647}
1648
1649static void restore_cpu_ipis(unsigned int cpu)
1650{
1651 struct evtchn_bind_ipi bind_ipi;
1652 int ipi, irq, evtchn;
1653
1654 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1655 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1656 continue;
1657
ced40d0f 1658 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1659
1660 /* Get a new binding from Xen. */
1661 bind_ipi.vcpu = cpu;
1662 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1663 &bind_ipi) != 0)
1664 BUG();
1665 evtchn = bind_ipi.port;
1666
1667 /* Record the new mapping. */
3d4cfa37 1668 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1669 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1670 }
1671}
1672
2d9e1e2f
JF
1673/* Clear an irq's pending state, in preparation for polling on it */
1674void xen_clear_irq_pending(int irq)
1675{
1676 int evtchn = evtchn_from_irq(irq);
1677
1678 if (VALID_EVTCHN(evtchn))
1679 clear_evtchn(evtchn);
1680}
d9a8814f 1681EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1682void xen_set_irq_pending(int irq)
1683{
1684 int evtchn = evtchn_from_irq(irq);
1685
1686 if (VALID_EVTCHN(evtchn))
1687 set_evtchn(evtchn);
1688}
1689
1690bool xen_test_irq_pending(int irq)
1691{
1692 int evtchn = evtchn_from_irq(irq);
1693 bool ret = false;
1694
1695 if (VALID_EVTCHN(evtchn))
1696 ret = test_evtchn(evtchn);
1697
1698 return ret;
1699}
1700
d9a8814f
KRW
1701/* Poll waiting for an irq to become pending with timeout. In the usual case,
1702 * the irq will be disabled so it won't deliver an interrupt. */
1703void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1704{
1705 evtchn_port_t evtchn = evtchn_from_irq(irq);
1706
1707 if (VALID_EVTCHN(evtchn)) {
1708 struct sched_poll poll;
1709
1710 poll.nr_ports = 1;
d9a8814f 1711 poll.timeout = timeout;
ff3c5362 1712 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1713
1714 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1715 BUG();
1716 }
1717}
d9a8814f
KRW
1718EXPORT_SYMBOL(xen_poll_irq_timeout);
1719/* Poll waiting for an irq to become pending. In the usual case, the
1720 * irq will be disabled so it won't deliver an interrupt. */
1721void xen_poll_irq(int irq)
1722{
1723 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1724}
2d9e1e2f 1725
c7c2c3a2
KRW
1726/* Check whether the IRQ line is shared with other guests. */
1727int xen_test_irq_shared(int irq)
1728{
1729 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1730 struct physdev_irq_status_query irq_status;
1731
1732 if (WARN_ON(!info))
1733 return -ENOENT;
1734
1735 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1736
1737 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1738 return 0;
1739 return !(irq_status.flags & XENIRQSTAT_shared);
1740}
1741EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1742
0e91398f
JF
1743void xen_irq_resume(void)
1744{
6cb6537d
IC
1745 unsigned int cpu, evtchn;
1746 struct irq_info *info;
0e91398f
JF
1747
1748 init_evtchn_cpu_bindings();
1749
1750 /* New event-channel space is not 'live' yet. */
1751 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1752 mask_evtchn(evtchn);
1753
1754 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1755 list_for_each_entry(info, &xen_irq_list_head, list)
1756 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1757
1758 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1759 evtchn_to_irq[evtchn] = -1;
1760
1761 for_each_possible_cpu(cpu) {
1762 restore_cpu_virqs(cpu);
1763 restore_cpu_ipis(cpu);
1764 }
6903591f 1765
0a85226f 1766 restore_pirqs();
0e91398f
JF
1767}
1768
e46cdb66 1769static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1770 .name = "xen-dyn",
54a353a0 1771
c9e265e0
TG
1772 .irq_disable = disable_dynirq,
1773 .irq_mask = disable_dynirq,
1774 .irq_unmask = enable_dynirq,
54a353a0 1775
7e186bdd
SS
1776 .irq_ack = ack_dynirq,
1777 .irq_mask_ack = mask_ack_dynirq,
1778
c9e265e0
TG
1779 .irq_set_affinity = set_affinity_irq,
1780 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1781};
1782
d46a78b0 1783static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1784 .name = "xen-pirq",
d46a78b0 1785
c9e265e0
TG
1786 .irq_startup = startup_pirq,
1787 .irq_shutdown = shutdown_pirq,
c9e265e0 1788 .irq_enable = enable_pirq,
c9e265e0 1789 .irq_disable = disable_pirq,
d46a78b0 1790
7e186bdd
SS
1791 .irq_mask = disable_dynirq,
1792 .irq_unmask = enable_dynirq,
1793
1794 .irq_ack = eoi_pirq,
1795 .irq_eoi = eoi_pirq,
1796 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1797
c9e265e0 1798 .irq_set_affinity = set_affinity_irq,
d46a78b0 1799
c9e265e0 1800 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1801};
1802
aaca4964 1803static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1804 .name = "xen-percpu",
aaca4964 1805
c9e265e0
TG
1806 .irq_disable = disable_dynirq,
1807 .irq_mask = disable_dynirq,
1808 .irq_unmask = enable_dynirq,
aaca4964 1809
c9e265e0 1810 .irq_ack = ack_dynirq,
aaca4964
JF
1811};
1812
38e20b07
SY
1813int xen_set_callback_via(uint64_t via)
1814{
1815 struct xen_hvm_param a;
1816 a.domid = DOMID_SELF;
1817 a.index = HVM_PARAM_CALLBACK_IRQ;
1818 a.value = via;
1819 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1820}
1821EXPORT_SYMBOL_GPL(xen_set_callback_via);
1822
ca65f9fc 1823#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1824/* Vector callbacks are better than PCI interrupts to receive event
1825 * channel notifications because we can receive vector callbacks on any
1826 * vcpu and we don't need PCI support or APIC interactions. */
1827void xen_callback_vector(void)
1828{
1829 int rc;
1830 uint64_t callback_via;
1831 if (xen_have_vector_callback) {
bc2b0331 1832 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1833 rc = xen_set_callback_via(callback_via);
1834 if (rc) {
1835 printk(KERN_ERR "Request for Xen HVM callback vector"
1836 " failed.\n");
1837 xen_have_vector_callback = 0;
1838 return;
1839 }
1840 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1841 "enabled\n");
1842 /* in the restore case the vector has already been allocated */
bc2b0331
S
1843 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1844 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1845 xen_hvm_callback_vector);
38e20b07
SY
1846 }
1847}
ca65f9fc
SS
1848#else
1849void xen_callback_vector(void) {}
1850#endif
38e20b07 1851
2e3d8860 1852void __init xen_init_IRQ(void)
e46cdb66 1853{
0ec53ecf 1854 int i;
c7a3589e 1855
b21ddbf5
JF
1856 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1857 GFP_KERNEL);
9d093e29 1858 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1859 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1860 evtchn_to_irq[i] = -1;
e46cdb66
JF
1861
1862 init_evtchn_cpu_bindings();
1863
1864 /* No event channels are 'live' right now. */
1865 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1866 mask_evtchn(i);
1867
9846ff10
SS
1868 pirq_needs_eoi = pirq_needs_eoi_flag;
1869
0ec53ecf 1870#ifdef CONFIG_X86
38e20b07
SY
1871 if (xen_hvm_domain()) {
1872 xen_callback_vector();
1873 native_init_IRQ();
3942b740
SS
1874 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1875 * __acpi_register_gsi can point at the right function */
1876 pci_xen_hvm_init();
38e20b07 1877 } else {
0ec53ecf 1878 int rc;
9846ff10
SS
1879 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1880
38e20b07 1881 irq_ctx_init(smp_processor_id());
38aa66fc 1882 if (xen_initial_domain())
a0ee0567 1883 pci_xen_initial_domain();
9846ff10
SS
1884
1885 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1886 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1887 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1888 if (rc != 0) {
1889 free_page((unsigned long) pirq_eoi_map);
1890 pirq_eoi_map = NULL;
1891 } else
1892 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1893 }
0ec53ecf 1894#endif
e46cdb66 1895}