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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
19 | * 4. Hardware interrupts. Not supported at present. | |
20 | * | |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
e46cdb66 JF |
31 | |
32 | #include <asm/ptrace.h> | |
33 | #include <asm/irq.h> | |
792dc4f6 | 34 | #include <asm/idle.h> |
e46cdb66 JF |
35 | #include <asm/sync_bitops.h> |
36 | #include <asm/xen/hypercall.h> | |
8d1b8753 | 37 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 38 | |
e04d0d07 | 39 | #include <xen/xen-ops.h> |
e46cdb66 JF |
40 | #include <xen/events.h> |
41 | #include <xen/interface/xen.h> | |
42 | #include <xen/interface/event_channel.h> | |
43 | ||
e46cdb66 JF |
44 | /* |
45 | * This lock protects updates to the following mapping and reference-count | |
46 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
47 | */ | |
48 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
49 | ||
50 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 51 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 52 | |
f87e4cac | 53 | /* IRQ <-> IPI mapping */ |
204fba4a | 54 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 55 | |
ced40d0f JF |
56 | /* Interrupt types. */ |
57 | enum xen_irq_type { | |
d77bbd4d | 58 | IRQT_UNBOUND = 0, |
f87e4cac JF |
59 | IRQT_PIRQ, |
60 | IRQT_VIRQ, | |
61 | IRQT_IPI, | |
62 | IRQT_EVTCHN | |
63 | }; | |
e46cdb66 | 64 | |
ced40d0f JF |
65 | /* |
66 | * Packed IRQ information: | |
67 | * type - enum xen_irq_type | |
68 | * event channel - irq->event channel mapping | |
69 | * cpu - cpu this event channel is bound to | |
70 | * index - type-specific information: | |
71 | * PIRQ - vector, with MSB being "needs EIO" | |
72 | * VIRQ - virq number | |
73 | * IPI - IPI vector | |
74 | * EVTCHN - | |
75 | */ | |
76 | struct irq_info | |
77 | { | |
78 | enum xen_irq_type type; /* type */ | |
79 | unsigned short evtchn; /* event channel */ | |
80 | unsigned short cpu; /* cpu bound */ | |
81 | ||
82 | union { | |
83 | unsigned short virq; | |
84 | enum ipi_vector ipi; | |
85 | struct { | |
86 | unsigned short gsi; | |
87 | unsigned short vector; | |
88 | } pirq; | |
89 | } u; | |
90 | }; | |
91 | ||
92 | static struct irq_info irq_info[NR_IRQS]; | |
e46cdb66 JF |
93 | |
94 | static int evtchn_to_irq[NR_EVENT_CHANNELS] = { | |
95 | [0 ... NR_EVENT_CHANNELS-1] = -1 | |
96 | }; | |
c7a3589e MT |
97 | struct cpu_evtchn_s { |
98 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
99 | }; | |
100 | static struct cpu_evtchn_s *cpu_evtchn_mask_p; | |
101 | static inline unsigned long *cpu_evtchn_mask(int cpu) | |
102 | { | |
103 | return cpu_evtchn_mask_p[cpu].bits; | |
104 | } | |
e46cdb66 | 105 | |
e46cdb66 JF |
106 | /* Xen will never allocate port zero for any purpose. */ |
107 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
108 | ||
e46cdb66 JF |
109 | static struct irq_chip xen_dynamic_chip; |
110 | ||
111 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
112 | static struct irq_info mk_unbound_info(void) |
113 | { | |
114 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
115 | } | |
116 | ||
117 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
118 | { | |
90af9514 IC |
119 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn, |
120 | .cpu = 0 }; | |
ced40d0f JF |
121 | } |
122 | ||
123 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 124 | { |
ced40d0f | 125 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
90af9514 | 126 | .cpu = 0, .u.ipi = ipi }; |
ced40d0f JF |
127 | } |
128 | ||
129 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
130 | { | |
131 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
90af9514 | 132 | .cpu = 0, .u.virq = virq }; |
ced40d0f JF |
133 | } |
134 | ||
135 | static struct irq_info mk_pirq_info(unsigned short evtchn, | |
136 | unsigned short gsi, unsigned short vector) | |
137 | { | |
138 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
90af9514 | 139 | .cpu = 0, .u.pirq = { .gsi = gsi, .vector = vector } }; |
e46cdb66 JF |
140 | } |
141 | ||
142 | /* | |
143 | * Accessors for packed IRQ information. | |
144 | */ | |
ced40d0f | 145 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 146 | { |
ced40d0f | 147 | return &irq_info[irq]; |
e46cdb66 JF |
148 | } |
149 | ||
ced40d0f | 150 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 151 | { |
ced40d0f | 152 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
153 | } |
154 | ||
d4c04536 IC |
155 | unsigned irq_from_evtchn(unsigned int evtchn) |
156 | { | |
157 | return evtchn_to_irq[evtchn]; | |
158 | } | |
159 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
160 | ||
ced40d0f | 161 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 162 | { |
ced40d0f JF |
163 | struct irq_info *info = info_for_irq(irq); |
164 | ||
165 | BUG_ON(info == NULL); | |
166 | BUG_ON(info->type != IRQT_IPI); | |
167 | ||
168 | return info->u.ipi; | |
169 | } | |
170 | ||
171 | static unsigned virq_from_irq(unsigned irq) | |
172 | { | |
173 | struct irq_info *info = info_for_irq(irq); | |
174 | ||
175 | BUG_ON(info == NULL); | |
176 | BUG_ON(info->type != IRQT_VIRQ); | |
177 | ||
178 | return info->u.virq; | |
179 | } | |
180 | ||
181 | static unsigned gsi_from_irq(unsigned irq) | |
182 | { | |
183 | struct irq_info *info = info_for_irq(irq); | |
184 | ||
185 | BUG_ON(info == NULL); | |
186 | BUG_ON(info->type != IRQT_PIRQ); | |
187 | ||
188 | return info->u.pirq.gsi; | |
189 | } | |
190 | ||
191 | static unsigned vector_from_irq(unsigned irq) | |
192 | { | |
193 | struct irq_info *info = info_for_irq(irq); | |
194 | ||
195 | BUG_ON(info == NULL); | |
196 | BUG_ON(info->type != IRQT_PIRQ); | |
197 | ||
198 | return info->u.pirq.vector; | |
199 | } | |
200 | ||
201 | static enum xen_irq_type type_from_irq(unsigned irq) | |
202 | { | |
203 | return info_for_irq(irq)->type; | |
204 | } | |
205 | ||
206 | static unsigned cpu_from_irq(unsigned irq) | |
207 | { | |
208 | return info_for_irq(irq)->cpu; | |
209 | } | |
210 | ||
211 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
212 | { | |
213 | int irq = evtchn_to_irq[evtchn]; | |
214 | unsigned ret = 0; | |
215 | ||
216 | if (irq != -1) | |
217 | ret = cpu_from_irq(irq); | |
218 | ||
219 | return ret; | |
e46cdb66 JF |
220 | } |
221 | ||
222 | static inline unsigned long active_evtchns(unsigned int cpu, | |
223 | struct shared_info *sh, | |
224 | unsigned int idx) | |
225 | { | |
226 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 227 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
228 | ~sh->evtchn_mask[idx]); |
229 | } | |
230 | ||
231 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
232 | { | |
233 | int irq = evtchn_to_irq[chn]; | |
234 | ||
235 | BUG_ON(irq == -1); | |
236 | #ifdef CONFIG_SMP | |
7f7ace0c | 237 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
238 | #endif |
239 | ||
ced40d0f | 240 | __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
c7a3589e | 241 | __set_bit(chn, cpu_evtchn_mask(cpu)); |
e46cdb66 | 242 | |
ced40d0f | 243 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
244 | } |
245 | ||
246 | static void init_evtchn_cpu_bindings(void) | |
247 | { | |
248 | #ifdef CONFIG_SMP | |
10e58084 | 249 | struct irq_desc *desc; |
e46cdb66 | 250 | int i; |
10e58084 | 251 | |
e46cdb66 | 252 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 253 | for_each_irq_desc(i, desc) { |
7f7ace0c | 254 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 255 | } |
e46cdb66 JF |
256 | #endif |
257 | ||
c7a3589e | 258 | memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0))); |
e46cdb66 JF |
259 | } |
260 | ||
e46cdb66 JF |
261 | static inline void clear_evtchn(int port) |
262 | { | |
263 | struct shared_info *s = HYPERVISOR_shared_info; | |
264 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
265 | } | |
266 | ||
267 | static inline void set_evtchn(int port) | |
268 | { | |
269 | struct shared_info *s = HYPERVISOR_shared_info; | |
270 | sync_set_bit(port, &s->evtchn_pending[0]); | |
271 | } | |
272 | ||
168d2f46 JF |
273 | static inline int test_evtchn(int port) |
274 | { | |
275 | struct shared_info *s = HYPERVISOR_shared_info; | |
276 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
277 | } | |
278 | ||
e46cdb66 JF |
279 | |
280 | /** | |
281 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
282 | * @irq: irq of event channel to send event to | |
283 | * | |
284 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
285 | * save/restore. Notifications on a broken connection are silently | |
286 | * dropped. | |
287 | */ | |
288 | void notify_remote_via_irq(int irq) | |
289 | { | |
290 | int evtchn = evtchn_from_irq(irq); | |
291 | ||
292 | if (VALID_EVTCHN(evtchn)) | |
293 | notify_remote_via_evtchn(evtchn); | |
294 | } | |
295 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
296 | ||
297 | static void mask_evtchn(int port) | |
298 | { | |
299 | struct shared_info *s = HYPERVISOR_shared_info; | |
300 | sync_set_bit(port, &s->evtchn_mask[0]); | |
301 | } | |
302 | ||
303 | static void unmask_evtchn(int port) | |
304 | { | |
305 | struct shared_info *s = HYPERVISOR_shared_info; | |
306 | unsigned int cpu = get_cpu(); | |
307 | ||
308 | BUG_ON(!irqs_disabled()); | |
309 | ||
310 | /* Slow path (hypercall) if this is a non-local port. */ | |
311 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
312 | struct evtchn_unmask unmask = { .port = port }; | |
313 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
314 | } else { | |
315 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
316 | ||
317 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
318 | ||
319 | /* | |
320 | * The following is basically the equivalent of | |
321 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
322 | * the interrupt edge' if the channel is masked. | |
323 | */ | |
324 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
325 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
326 | &vcpu_info->evtchn_pending_sel)) | |
327 | vcpu_info->evtchn_upcall_pending = 1; | |
328 | } | |
329 | ||
330 | put_cpu(); | |
331 | } | |
332 | ||
333 | static int find_unbound_irq(void) | |
334 | { | |
335 | int irq; | |
6f8a0ed4 | 336 | struct irq_desc *desc; |
e46cdb66 | 337 | |
0b8f1efa | 338 | for (irq = 0; irq < nr_irqs; irq++) |
d77bbd4d | 339 | if (irq_info[irq].type == IRQT_UNBOUND) |
e46cdb66 JF |
340 | break; |
341 | ||
5a15d7e8 YL |
342 | if (irq == nr_irqs) |
343 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 | 344 | |
85ac16d0 | 345 | desc = irq_to_desc_alloc_node(irq, 0); |
6f8a0ed4 JF |
346 | if (WARN_ON(desc == NULL)) |
347 | return -1; | |
348 | ||
ced40d0f JF |
349 | dynamic_irq_init(irq); |
350 | ||
e46cdb66 JF |
351 | return irq; |
352 | } | |
353 | ||
b536b4b9 | 354 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
355 | { |
356 | int irq; | |
357 | ||
358 | spin_lock(&irq_mapping_update_lock); | |
359 | ||
360 | irq = evtchn_to_irq[evtchn]; | |
361 | ||
362 | if (irq == -1) { | |
363 | irq = find_unbound_irq(); | |
364 | ||
e46cdb66 JF |
365 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
366 | handle_level_irq, "event"); | |
367 | ||
368 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 369 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
370 | } |
371 | ||
e46cdb66 JF |
372 | spin_unlock(&irq_mapping_update_lock); |
373 | ||
374 | return irq; | |
375 | } | |
b536b4b9 | 376 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 377 | |
f87e4cac JF |
378 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
379 | { | |
380 | struct evtchn_bind_ipi bind_ipi; | |
381 | int evtchn, irq; | |
382 | ||
383 | spin_lock(&irq_mapping_update_lock); | |
384 | ||
385 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 386 | |
f87e4cac JF |
387 | if (irq == -1) { |
388 | irq = find_unbound_irq(); | |
389 | if (irq < 0) | |
390 | goto out; | |
391 | ||
f87e4cac JF |
392 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
393 | handle_level_irq, "ipi"); | |
394 | ||
395 | bind_ipi.vcpu = cpu; | |
396 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
397 | &bind_ipi) != 0) | |
398 | BUG(); | |
399 | evtchn = bind_ipi.port; | |
400 | ||
401 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 402 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
403 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
404 | ||
405 | bind_evtchn_to_cpu(evtchn, cpu); | |
406 | } | |
407 | ||
f87e4cac JF |
408 | out: |
409 | spin_unlock(&irq_mapping_update_lock); | |
410 | return irq; | |
411 | } | |
412 | ||
413 | ||
e46cdb66 JF |
414 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
415 | { | |
416 | struct evtchn_bind_virq bind_virq; | |
417 | int evtchn, irq; | |
418 | ||
419 | spin_lock(&irq_mapping_update_lock); | |
420 | ||
421 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
422 | ||
423 | if (irq == -1) { | |
424 | bind_virq.virq = virq; | |
425 | bind_virq.vcpu = cpu; | |
426 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
427 | &bind_virq) != 0) | |
428 | BUG(); | |
429 | evtchn = bind_virq.port; | |
430 | ||
431 | irq = find_unbound_irq(); | |
432 | ||
e46cdb66 JF |
433 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
434 | handle_level_irq, "virq"); | |
435 | ||
436 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 437 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
438 | |
439 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
440 | ||
441 | bind_evtchn_to_cpu(evtchn, cpu); | |
442 | } | |
443 | ||
e46cdb66 JF |
444 | spin_unlock(&irq_mapping_update_lock); |
445 | ||
446 | return irq; | |
447 | } | |
448 | ||
449 | static void unbind_from_irq(unsigned int irq) | |
450 | { | |
451 | struct evtchn_close close; | |
452 | int evtchn = evtchn_from_irq(irq); | |
453 | ||
454 | spin_lock(&irq_mapping_update_lock); | |
455 | ||
d77bbd4d | 456 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
457 | close.port = evtchn; |
458 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
459 | BUG(); | |
460 | ||
461 | switch (type_from_irq(irq)) { | |
462 | case IRQT_VIRQ: | |
463 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 464 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 465 | break; |
d68d82af AN |
466 | case IRQT_IPI: |
467 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 468 | [ipi_from_irq(irq)] = -1; |
d68d82af | 469 | break; |
e46cdb66 JF |
470 | default: |
471 | break; | |
472 | } | |
473 | ||
474 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
475 | bind_evtchn_to_cpu(evtchn, 0); | |
476 | ||
477 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
478 | } |
479 | ||
480 | if (irq_info[irq].type != IRQT_UNBOUND) { | |
ced40d0f | 481 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 482 | |
0f2287ad | 483 | dynamic_irq_cleanup(irq); |
e46cdb66 JF |
484 | } |
485 | ||
486 | spin_unlock(&irq_mapping_update_lock); | |
487 | } | |
488 | ||
489 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 490 | irq_handler_t handler, |
e46cdb66 JF |
491 | unsigned long irqflags, |
492 | const char *devname, void *dev_id) | |
493 | { | |
494 | unsigned int irq; | |
495 | int retval; | |
496 | ||
497 | irq = bind_evtchn_to_irq(evtchn); | |
498 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
499 | if (retval != 0) { | |
500 | unbind_from_irq(irq); | |
501 | return retval; | |
502 | } | |
503 | ||
504 | return irq; | |
505 | } | |
506 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
507 | ||
508 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 509 | irq_handler_t handler, |
e46cdb66 JF |
510 | unsigned long irqflags, const char *devname, void *dev_id) |
511 | { | |
512 | unsigned int irq; | |
513 | int retval; | |
514 | ||
515 | irq = bind_virq_to_irq(virq, cpu); | |
516 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
517 | if (retval != 0) { | |
518 | unbind_from_irq(irq); | |
519 | return retval; | |
520 | } | |
521 | ||
522 | return irq; | |
523 | } | |
524 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
525 | ||
f87e4cac JF |
526 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
527 | unsigned int cpu, | |
528 | irq_handler_t handler, | |
529 | unsigned long irqflags, | |
530 | const char *devname, | |
531 | void *dev_id) | |
532 | { | |
533 | int irq, retval; | |
534 | ||
535 | irq = bind_ipi_to_irq(ipi, cpu); | |
536 | if (irq < 0) | |
537 | return irq; | |
538 | ||
539 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
540 | if (retval != 0) { | |
541 | unbind_from_irq(irq); | |
542 | return retval; | |
543 | } | |
544 | ||
545 | return irq; | |
546 | } | |
547 | ||
e46cdb66 JF |
548 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
549 | { | |
550 | free_irq(irq, dev_id); | |
551 | unbind_from_irq(irq); | |
552 | } | |
553 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
554 | ||
f87e4cac JF |
555 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
556 | { | |
557 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
558 | BUG_ON(irq < 0); | |
559 | notify_remote_via_irq(irq); | |
560 | } | |
561 | ||
ee523ca1 JF |
562 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
563 | { | |
564 | struct shared_info *sh = HYPERVISOR_shared_info; | |
565 | int cpu = smp_processor_id(); | |
566 | int i; | |
567 | unsigned long flags; | |
568 | static DEFINE_SPINLOCK(debug_lock); | |
569 | ||
570 | spin_lock_irqsave(&debug_lock, flags); | |
571 | ||
572 | printk("vcpu %d\n ", cpu); | |
573 | ||
574 | for_each_online_cpu(i) { | |
575 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
576 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 577 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
578 | v->evtchn_upcall_pending, |
579 | v->evtchn_pending_sel); | |
580 | } | |
581 | printk("pending:\n "); | |
582 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
583 | printk("%08lx%s", sh->evtchn_pending[i], | |
584 | i % 8 == 0 ? "\n " : " "); | |
585 | printk("\nmasks:\n "); | |
586 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
587 | printk("%08lx%s", sh->evtchn_mask[i], | |
588 | i % 8 == 0 ? "\n " : " "); | |
589 | ||
590 | printk("\nunmasked:\n "); | |
591 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
592 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
593 | i % 8 == 0 ? "\n " : " "); | |
594 | ||
595 | printk("\npending list:\n"); | |
596 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
597 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
598 | printk(" %d: event %d -> irq %d\n", | |
ced40d0f JF |
599 | cpu_from_evtchn(i), i, |
600 | evtchn_to_irq[i]); | |
ee523ca1 JF |
601 | } |
602 | } | |
603 | ||
604 | spin_unlock_irqrestore(&debug_lock, flags); | |
605 | ||
606 | return IRQ_HANDLED; | |
607 | } | |
608 | ||
245b2e70 TH |
609 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
610 | ||
e46cdb66 JF |
611 | /* |
612 | * Search the CPUs pending events bitmasks. For each one found, map | |
613 | * the event number to an irq, and feed it into do_IRQ() for | |
614 | * handling. | |
615 | * | |
616 | * Xen uses a two-level bitmap to speed searching. The first level is | |
617 | * a bitset of words which contain pending event bits. The second | |
618 | * level is a bitset of pending events themselves. | |
619 | */ | |
75604d7f | 620 | void xen_evtchn_do_upcall(struct pt_regs *regs) |
e46cdb66 JF |
621 | { |
622 | int cpu = get_cpu(); | |
3445a8fd | 623 | struct pt_regs *old_regs = set_irq_regs(regs); |
e46cdb66 JF |
624 | struct shared_info *s = HYPERVISOR_shared_info; |
625 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be | 626 | unsigned count; |
e46cdb66 | 627 | |
3445a8fd JF |
628 | exit_idle(); |
629 | irq_enter(); | |
630 | ||
229664be JF |
631 | do { |
632 | unsigned long pending_words; | |
e46cdb66 | 633 | |
229664be | 634 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 635 | |
245b2e70 | 636 | if (__get_cpu_var(xed_nesting_count)++) |
229664be | 637 | goto out; |
e46cdb66 | 638 | |
e849c3e9 IY |
639 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
640 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 641 | wmb(); |
e849c3e9 | 642 | #endif |
229664be JF |
643 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
644 | while (pending_words != 0) { | |
645 | unsigned long pending_bits; | |
646 | int word_idx = __ffs(pending_words); | |
647 | pending_words &= ~(1UL << word_idx); | |
648 | ||
649 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
650 | int bit_idx = __ffs(pending_bits); | |
651 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
652 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 653 | struct irq_desc *desc; |
229664be | 654 | |
ca4dbc66 EB |
655 | if (irq != -1) { |
656 | desc = irq_to_desc(irq); | |
657 | if (desc) | |
658 | generic_handle_irq_desc(irq, desc); | |
659 | } | |
e46cdb66 JF |
660 | } |
661 | } | |
e46cdb66 | 662 | |
229664be JF |
663 | BUG_ON(!irqs_disabled()); |
664 | ||
245b2e70 TH |
665 | count = __get_cpu_var(xed_nesting_count); |
666 | __get_cpu_var(xed_nesting_count) = 0; | |
229664be JF |
667 | } while(count != 1); |
668 | ||
669 | out: | |
3445a8fd JF |
670 | irq_exit(); |
671 | set_irq_regs(old_regs); | |
672 | ||
e46cdb66 JF |
673 | put_cpu(); |
674 | } | |
675 | ||
eb1e305f JF |
676 | /* Rebind a new event channel to an existing irq. */ |
677 | void rebind_evtchn_irq(int evtchn, int irq) | |
678 | { | |
d77bbd4d JF |
679 | struct irq_info *info = info_for_irq(irq); |
680 | ||
eb1e305f JF |
681 | /* Make sure the irq is masked, since the new event channel |
682 | will also be masked. */ | |
683 | disable_irq(irq); | |
684 | ||
685 | spin_lock(&irq_mapping_update_lock); | |
686 | ||
687 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
688 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
689 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
690 | so there should be a proper type */ |
691 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
692 | |
693 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 694 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
695 | |
696 | spin_unlock(&irq_mapping_update_lock); | |
697 | ||
698 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 699 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
700 | |
701 | /* Unmask the event channel. */ | |
702 | enable_irq(irq); | |
703 | } | |
704 | ||
e46cdb66 | 705 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 706 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
707 | { |
708 | struct evtchn_bind_vcpu bind_vcpu; | |
709 | int evtchn = evtchn_from_irq(irq); | |
710 | ||
711 | if (!VALID_EVTCHN(evtchn)) | |
d5dedd45 | 712 | return -1; |
e46cdb66 JF |
713 | |
714 | /* Send future instances of this interrupt to other vcpu. */ | |
715 | bind_vcpu.port = evtchn; | |
716 | bind_vcpu.vcpu = tcpu; | |
717 | ||
718 | /* | |
719 | * If this fails, it usually just indicates that we're dealing with a | |
720 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
721 | * it, but don't do the xenlinux-level rebind in that case. | |
722 | */ | |
723 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
724 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 725 | |
d5dedd45 YL |
726 | return 0; |
727 | } | |
e46cdb66 | 728 | |
d5dedd45 | 729 | static int set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 730 | { |
0de26520 | 731 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 YL |
732 | |
733 | return rebind_irq_to_cpu(irq, tcpu); | |
e46cdb66 JF |
734 | } |
735 | ||
642e0c88 IY |
736 | int resend_irq_on_evtchn(unsigned int irq) |
737 | { | |
738 | int masked, evtchn = evtchn_from_irq(irq); | |
739 | struct shared_info *s = HYPERVISOR_shared_info; | |
740 | ||
741 | if (!VALID_EVTCHN(evtchn)) | |
742 | return 1; | |
743 | ||
744 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
745 | sync_set_bit(evtchn, s->evtchn_pending); | |
746 | if (!masked) | |
747 | unmask_evtchn(evtchn); | |
748 | ||
749 | return 1; | |
750 | } | |
751 | ||
e46cdb66 JF |
752 | static void enable_dynirq(unsigned int irq) |
753 | { | |
754 | int evtchn = evtchn_from_irq(irq); | |
755 | ||
756 | if (VALID_EVTCHN(evtchn)) | |
757 | unmask_evtchn(evtchn); | |
758 | } | |
759 | ||
760 | static void disable_dynirq(unsigned int irq) | |
761 | { | |
762 | int evtchn = evtchn_from_irq(irq); | |
763 | ||
764 | if (VALID_EVTCHN(evtchn)) | |
765 | mask_evtchn(evtchn); | |
766 | } | |
767 | ||
768 | static void ack_dynirq(unsigned int irq) | |
769 | { | |
770 | int evtchn = evtchn_from_irq(irq); | |
771 | ||
772 | move_native_irq(irq); | |
773 | ||
774 | if (VALID_EVTCHN(evtchn)) | |
775 | clear_evtchn(evtchn); | |
776 | } | |
777 | ||
778 | static int retrigger_dynirq(unsigned int irq) | |
779 | { | |
780 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 781 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
782 | int ret = 0; |
783 | ||
784 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
785 | int masked; |
786 | ||
787 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
788 | sync_set_bit(evtchn, sh->evtchn_pending); | |
789 | if (!masked) | |
790 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
791 | ret = 1; |
792 | } | |
793 | ||
794 | return ret; | |
795 | } | |
796 | ||
0e91398f JF |
797 | static void restore_cpu_virqs(unsigned int cpu) |
798 | { | |
799 | struct evtchn_bind_virq bind_virq; | |
800 | int virq, irq, evtchn; | |
801 | ||
802 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
803 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
804 | continue; | |
805 | ||
ced40d0f | 806 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
807 | |
808 | /* Get a new binding from Xen. */ | |
809 | bind_virq.virq = virq; | |
810 | bind_virq.vcpu = cpu; | |
811 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
812 | &bind_virq) != 0) | |
813 | BUG(); | |
814 | evtchn = bind_virq.port; | |
815 | ||
816 | /* Record the new mapping. */ | |
817 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 818 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f JF |
819 | bind_evtchn_to_cpu(evtchn, cpu); |
820 | ||
821 | /* Ready for use. */ | |
822 | unmask_evtchn(evtchn); | |
823 | } | |
824 | } | |
825 | ||
826 | static void restore_cpu_ipis(unsigned int cpu) | |
827 | { | |
828 | struct evtchn_bind_ipi bind_ipi; | |
829 | int ipi, irq, evtchn; | |
830 | ||
831 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
832 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
833 | continue; | |
834 | ||
ced40d0f | 835 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
836 | |
837 | /* Get a new binding from Xen. */ | |
838 | bind_ipi.vcpu = cpu; | |
839 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
840 | &bind_ipi) != 0) | |
841 | BUG(); | |
842 | evtchn = bind_ipi.port; | |
843 | ||
844 | /* Record the new mapping. */ | |
845 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 846 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f JF |
847 | bind_evtchn_to_cpu(evtchn, cpu); |
848 | ||
849 | /* Ready for use. */ | |
850 | unmask_evtchn(evtchn); | |
851 | ||
852 | } | |
853 | } | |
854 | ||
2d9e1e2f JF |
855 | /* Clear an irq's pending state, in preparation for polling on it */ |
856 | void xen_clear_irq_pending(int irq) | |
857 | { | |
858 | int evtchn = evtchn_from_irq(irq); | |
859 | ||
860 | if (VALID_EVTCHN(evtchn)) | |
861 | clear_evtchn(evtchn); | |
862 | } | |
863 | ||
168d2f46 JF |
864 | void xen_set_irq_pending(int irq) |
865 | { | |
866 | int evtchn = evtchn_from_irq(irq); | |
867 | ||
868 | if (VALID_EVTCHN(evtchn)) | |
869 | set_evtchn(evtchn); | |
870 | } | |
871 | ||
872 | bool xen_test_irq_pending(int irq) | |
873 | { | |
874 | int evtchn = evtchn_from_irq(irq); | |
875 | bool ret = false; | |
876 | ||
877 | if (VALID_EVTCHN(evtchn)) | |
878 | ret = test_evtchn(evtchn); | |
879 | ||
880 | return ret; | |
881 | } | |
882 | ||
2d9e1e2f JF |
883 | /* Poll waiting for an irq to become pending. In the usual case, the |
884 | irq will be disabled so it won't deliver an interrupt. */ | |
885 | void xen_poll_irq(int irq) | |
886 | { | |
887 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
888 | ||
889 | if (VALID_EVTCHN(evtchn)) { | |
890 | struct sched_poll poll; | |
891 | ||
892 | poll.nr_ports = 1; | |
893 | poll.timeout = 0; | |
ff3c5362 | 894 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
895 | |
896 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
897 | BUG(); | |
898 | } | |
899 | } | |
900 | ||
0e91398f JF |
901 | void xen_irq_resume(void) |
902 | { | |
903 | unsigned int cpu, irq, evtchn; | |
904 | ||
905 | init_evtchn_cpu_bindings(); | |
906 | ||
907 | /* New event-channel space is not 'live' yet. */ | |
908 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
909 | mask_evtchn(evtchn); | |
910 | ||
911 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 912 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
913 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
914 | ||
915 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
916 | evtchn_to_irq[evtchn] = -1; | |
917 | ||
918 | for_each_possible_cpu(cpu) { | |
919 | restore_cpu_virqs(cpu); | |
920 | restore_cpu_ipis(cpu); | |
921 | } | |
922 | } | |
923 | ||
e46cdb66 JF |
924 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
925 | .name = "xen-dyn", | |
54a353a0 JF |
926 | |
927 | .disable = disable_dynirq, | |
e46cdb66 JF |
928 | .mask = disable_dynirq, |
929 | .unmask = enable_dynirq, | |
54a353a0 | 930 | |
e46cdb66 JF |
931 | .ack = ack_dynirq, |
932 | .set_affinity = set_affinity_irq, | |
933 | .retrigger = retrigger_dynirq, | |
934 | }; | |
935 | ||
936 | void __init xen_init_IRQ(void) | |
937 | { | |
938 | int i; | |
c7a3589e | 939 | |
a70c352a PE |
940 | cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s), |
941 | GFP_KERNEL); | |
28e08861 | 942 | BUG_ON(cpu_evtchn_mask_p == NULL); |
e46cdb66 JF |
943 | |
944 | init_evtchn_cpu_bindings(); | |
945 | ||
946 | /* No event channels are 'live' right now. */ | |
947 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
948 | mask_evtchn(i); | |
949 | ||
e46cdb66 JF |
950 | irq_ctx_init(smp_processor_id()); |
951 | } |