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xen: events: assume PHYSDEVOP_get_free_pirq exists
[mirror_ubuntu-artful-kernel.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
110e7c7e
JJ
173 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
174 return 0;
175
ced40d0f 176 return info_for_irq(irq)->evtchn;
e46cdb66
JF
177}
178
d4c04536
IC
179unsigned irq_from_evtchn(unsigned int evtchn)
180{
181 return evtchn_to_irq[evtchn];
182}
183EXPORT_SYMBOL_GPL(irq_from_evtchn);
184
ced40d0f 185static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 186{
ced40d0f
JF
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_IPI);
191
192 return info->u.ipi;
193}
194
195static unsigned virq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_VIRQ);
201
202 return info->u.virq;
203}
204
7a043f11
SS
205static unsigned pirq_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.pirq;
213}
214
ced40d0f
JF
215static unsigned gsi_from_irq(unsigned irq)
216{
217 struct irq_info *info = info_for_irq(irq);
218
219 BUG_ON(info == NULL);
220 BUG_ON(info->type != IRQT_PIRQ);
221
222 return info->u.pirq.gsi;
223}
224
225static unsigned vector_from_irq(unsigned irq)
226{
227 struct irq_info *info = info_for_irq(irq);
228
229 BUG_ON(info == NULL);
230 BUG_ON(info->type != IRQT_PIRQ);
231
232 return info->u.pirq.vector;
233}
234
235static enum xen_irq_type type_from_irq(unsigned irq)
236{
237 return info_for_irq(irq)->type;
238}
239
240static unsigned cpu_from_irq(unsigned irq)
241{
242 return info_for_irq(irq)->cpu;
243}
244
245static unsigned int cpu_from_evtchn(unsigned int evtchn)
246{
247 int irq = evtchn_to_irq[evtchn];
248 unsigned ret = 0;
249
250 if (irq != -1)
251 ret = cpu_from_irq(irq);
252
253 return ret;
e46cdb66
JF
254}
255
d46a78b0
JF
256static bool pirq_needs_eoi(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info->type != IRQT_PIRQ);
261
262 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
263}
264
e46cdb66
JF
265static inline unsigned long active_evtchns(unsigned int cpu,
266 struct shared_info *sh,
267 unsigned int idx)
268{
269 return (sh->evtchn_pending[idx] &
c7a3589e 270 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
271 ~sh->evtchn_mask[idx]);
272}
273
274static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
275{
276 int irq = evtchn_to_irq[chn];
277
278 BUG_ON(irq == -1);
279#ifdef CONFIG_SMP
c9e265e0 280 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
281#endif
282
e0419564
JF
283 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
284 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 285
ced40d0f 286 irq_info[irq].cpu = cpu;
e46cdb66
JF
287}
288
289static void init_evtchn_cpu_bindings(void)
290{
1c6969ec 291 int i;
e46cdb66 292#ifdef CONFIG_SMP
10e58084 293 struct irq_desc *desc;
10e58084 294
e46cdb66 295 /* By default all event channels notify CPU#0. */
0b8f1efa 296 for_each_irq_desc(i, desc) {
c9e265e0 297 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 298 }
e46cdb66
JF
299#endif
300
1c6969ec
JB
301 for_each_possible_cpu(i)
302 memset(cpu_evtchn_mask(i),
303 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
304
e46cdb66
JF
305}
306
e46cdb66
JF
307static inline void clear_evtchn(int port)
308{
309 struct shared_info *s = HYPERVISOR_shared_info;
310 sync_clear_bit(port, &s->evtchn_pending[0]);
311}
312
313static inline void set_evtchn(int port)
314{
315 struct shared_info *s = HYPERVISOR_shared_info;
316 sync_set_bit(port, &s->evtchn_pending[0]);
317}
318
168d2f46
JF
319static inline int test_evtchn(int port)
320{
321 struct shared_info *s = HYPERVISOR_shared_info;
322 return sync_test_bit(port, &s->evtchn_pending[0]);
323}
324
e46cdb66
JF
325
326/**
327 * notify_remote_via_irq - send event to remote end of event channel via irq
328 * @irq: irq of event channel to send event to
329 *
330 * Unlike notify_remote_via_evtchn(), this is safe to use across
331 * save/restore. Notifications on a broken connection are silently
332 * dropped.
333 */
334void notify_remote_via_irq(int irq)
335{
336 int evtchn = evtchn_from_irq(irq);
337
338 if (VALID_EVTCHN(evtchn))
339 notify_remote_via_evtchn(evtchn);
340}
341EXPORT_SYMBOL_GPL(notify_remote_via_irq);
342
343static void mask_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
346 sync_set_bit(port, &s->evtchn_mask[0]);
347}
348
349static void unmask_evtchn(int port)
350{
351 struct shared_info *s = HYPERVISOR_shared_info;
352 unsigned int cpu = get_cpu();
353
354 BUG_ON(!irqs_disabled());
355
356 /* Slow path (hypercall) if this is a non-local port. */
357 if (unlikely(cpu != cpu_from_evtchn(port))) {
358 struct evtchn_unmask unmask = { .port = port };
359 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
360 } else {
780f36d8 361 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
362
363 sync_clear_bit(port, &s->evtchn_mask[0]);
364
365 /*
366 * The following is basically the equivalent of
367 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
368 * the interrupt edge' if the channel is masked.
369 */
370 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
371 !sync_test_and_set_bit(port / BITS_PER_LONG,
372 &vcpu_info->evtchn_pending_sel))
373 vcpu_info->evtchn_upcall_pending = 1;
374 }
375
376 put_cpu();
377}
378
89911501 379static int xen_allocate_irq_dynamic(void)
0794bfc7 380{
89911501
IC
381 int first = 0;
382 int irq;
0794bfc7
KRW
383
384#ifdef CONFIG_X86_IO_APIC
89911501
IC
385 /*
386 * For an HVM guest or domain 0 which see "real" (emulated or
387 * actual repectively) GSIs we allocate dynamic IRQs
388 * e.g. those corresponding to event channels or MSIs
389 * etc. from the range above those "real" GSIs to avoid
390 * collisions.
391 */
392 if (xen_initial_domain() || xen_hvm_domain())
393 first = get_nr_irqs_gsi();
0794bfc7
KRW
394#endif
395
89911501
IC
396retry:
397 irq = irq_alloc_desc_from(first, -1);
3a69e916 398
89911501
IC
399 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
400 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
401 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
402 goto retry;
99ad198c 403 }
e46cdb66 404
89911501
IC
405 if (irq < 0)
406 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 407
e46cdb66 408 return irq;
d46a78b0
JF
409}
410
c9df1ce5
IC
411static int xen_allocate_irq_gsi(unsigned gsi)
412{
413 int irq;
414
89911501
IC
415 /*
416 * A PV guest has no concept of a GSI (since it has no ACPI
417 * nor access to/knowledge of the physical APICs). Therefore
418 * all IRQs are dynamically allocated from the entire IRQ
419 * space.
420 */
421 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
422 return xen_allocate_irq_dynamic();
423
424 /* Legacy IRQ descriptors are already allocated by the arch. */
425 if (gsi < NR_IRQS_LEGACY)
426 return gsi;
427
428 irq = irq_alloc_desc_at(gsi, -1);
429 if (irq < 0)
430 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
431
432 return irq;
433}
434
435static void xen_free_irq(unsigned irq)
436{
72146104
IC
437 /* Legacy IRQ descriptors are managed by the arch. */
438 if (irq < NR_IRQS_LEGACY)
439 return;
440
c9df1ce5
IC
441 irq_free_desc(irq);
442}
443
d46a78b0
JF
444static void pirq_unmask_notify(int irq)
445{
7a043f11 446 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
447
448 if (unlikely(pirq_needs_eoi(irq))) {
449 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
450 WARN_ON(rc);
451 }
452}
453
454static void pirq_query_unmask(int irq)
455{
456 struct physdev_irq_status_query irq_status;
457 struct irq_info *info = info_for_irq(irq);
458
459 BUG_ON(info->type != IRQT_PIRQ);
460
7a043f11 461 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
462 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
463 irq_status.flags = 0;
464
465 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
466 if (irq_status.flags & XENIRQSTAT_needs_eoi)
467 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
468}
469
470static bool probing_irq(int irq)
471{
472 struct irq_desc *desc = irq_to_desc(irq);
473
474 return desc && desc->action == NULL;
475}
476
c9e265e0 477static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
478{
479 struct evtchn_bind_pirq bind_pirq;
480 struct irq_info *info = info_for_irq(irq);
481 int evtchn = evtchn_from_irq(irq);
15ebbb82 482 int rc;
d46a78b0
JF
483
484 BUG_ON(info->type != IRQT_PIRQ);
485
486 if (VALID_EVTCHN(evtchn))
487 goto out;
488
7a043f11 489 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 490 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
491 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
492 BIND_PIRQ__WILL_SHARE : 0;
493 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
494 if (rc != 0) {
d46a78b0
JF
495 if (!probing_irq(irq))
496 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
497 irq);
498 return 0;
499 }
500 evtchn = bind_pirq.port;
501
502 pirq_query_unmask(irq);
503
504 evtchn_to_irq[evtchn] = irq;
505 bind_evtchn_to_cpu(evtchn, 0);
506 info->evtchn = evtchn;
507
508out:
509 unmask_evtchn(evtchn);
510 pirq_unmask_notify(irq);
511
512 return 0;
513}
514
c9e265e0
TG
515static unsigned int startup_pirq(struct irq_data *data)
516{
517 return __startup_pirq(data->irq);
518}
519
520static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
521{
522 struct evtchn_close close;
c9e265e0 523 unsigned int irq = data->irq;
d46a78b0
JF
524 struct irq_info *info = info_for_irq(irq);
525 int evtchn = evtchn_from_irq(irq);
526
527 BUG_ON(info->type != IRQT_PIRQ);
528
529 if (!VALID_EVTCHN(evtchn))
530 return;
531
532 mask_evtchn(evtchn);
533
534 close.port = evtchn;
535 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
536 BUG();
537
538 bind_evtchn_to_cpu(evtchn, 0);
539 evtchn_to_irq[evtchn] = -1;
540 info->evtchn = 0;
541}
542
c9e265e0 543static void enable_pirq(struct irq_data *data)
d46a78b0 544{
c9e265e0 545 startup_pirq(data);
d46a78b0
JF
546}
547
c9e265e0 548static void disable_pirq(struct irq_data *data)
d46a78b0
JF
549{
550}
551
c9e265e0 552static void ack_pirq(struct irq_data *data)
d46a78b0 553{
c9e265e0 554 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 555
aa673c1c 556 move_native_irq(data->irq);
d46a78b0
JF
557
558 if (VALID_EVTCHN(evtchn)) {
559 mask_evtchn(evtchn);
560 clear_evtchn(evtchn);
561 }
562}
563
d46a78b0
JF
564static int find_irq_by_gsi(unsigned gsi)
565{
566 int irq;
567
b21ddbf5 568 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
569 struct irq_info *info = info_for_irq(irq);
570
571 if (info == NULL || info->type != IRQT_PIRQ)
572 continue;
573
574 if (gsi_from_irq(irq) == gsi)
575 return irq;
576 }
577
578 return -1;
579}
580
7a043f11
SS
581int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
582{
583 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
584}
585
586/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
587 * consequence don't assume that the irq number returned has a low value
588 * or can be used as a pirq number unless you know otherwise.
589 *
7a043f11 590 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 591 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
592 * matches the gsi number passed as second argument.
593 *
594 * Note: We don't assign an event channel until the irq actually started
595 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 596 */
7a043f11 597int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 598{
7a043f11 599 int irq = 0;
d46a78b0
JF
600 struct physdev_irq irq_op;
601
602 spin_lock(&irq_mapping_update_lock);
603
e5fc7345 604 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 605 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
606 pirq > nr_irqs ? "pirq" :"",
607 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
608 goto out;
609 }
610
d46a78b0
JF
611 irq = find_irq_by_gsi(gsi);
612 if (irq != -1) {
7a043f11 613 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
614 irq, gsi);
615 goto out; /* XXX need refcount? */
616 }
617
c9df1ce5 618 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
619
620 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 621 handle_level_irq, name);
d46a78b0
JF
622
623 irq_op.irq = irq;
b5401a96
AN
624 irq_op.vector = 0;
625
626 /* Only the privileged domain can do this. For non-priv, the pcifront
627 * driver provides a PCI bus that does the call to do exactly
628 * this in the priv domain. */
629 if (xen_initial_domain() &&
630 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 631 xen_free_irq(irq);
d46a78b0
JF
632 irq = -ENOSPC;
633 goto out;
634 }
635
7a043f11 636 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 637 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 638 pirq_to_irq[pirq] = irq;
d46a78b0
JF
639
640out:
641 spin_unlock(&irq_mapping_update_lock);
642
643 return irq;
644}
645
f731e3ef
QH
646#ifdef CONFIG_PCI_MSI
647#include <linux/msi.h>
648#include "../pci/msi.h"
649
cbf6aa89
IC
650static int find_unbound_pirq(int type)
651{
5cad61a6 652 int rc;
cbf6aa89 653 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 654
5cad61a6 655 op_get_free_pirq.type = type;
cbf6aa89 656 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 657
5cad61a6
IC
658 WARN_ONCE(rc == -ENOSYS,
659 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
660
661 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
662}
663
4b41df7f 664int xen_allocate_pirq_msi(char *name, int *pirq, int alloc_pirq)
809f9267 665{
4b41df7f
IC
666 int irq;
667
809f9267
SS
668 spin_lock(&irq_mapping_update_lock);
669
4b41df7f
IC
670 irq = xen_allocate_irq_dynamic();
671 if (irq == -1)
bb5d079a 672 goto out;
809f9267 673
bb5d079a 674 if (alloc_pirq) {
af42b8d1 675 *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
ae1635b0 676 if (*pirq == -1) {
4b41df7f
IC
677 xen_free_irq(irq);
678 irq = -1;
af42b8d1 679 goto out;
ae1635b0 680 }
af42b8d1 681 }
809f9267 682
4b41df7f 683 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
809f9267
SS
684 handle_level_irq, name);
685
4b41df7f
IC
686 irq_info[irq] = mk_pirq_info(0, *pirq, 0, 0);
687 pirq_to_irq[*pirq] = irq;
809f9267
SS
688
689out:
690 spin_unlock(&irq_mapping_update_lock);
4b41df7f 691 return irq;
809f9267
SS
692}
693
f731e3ef
QH
694int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
695{
696 int irq = -1;
697 struct physdev_map_pirq map_irq;
698 int rc;
699 int pos;
700 u32 table_offset, bir;
701
702 memset(&map_irq, 0, sizeof(map_irq));
703 map_irq.domid = DOMID_SELF;
704 map_irq.type = MAP_PIRQ_TYPE_MSI;
705 map_irq.index = -1;
706 map_irq.pirq = -1;
707 map_irq.bus = dev->bus->number;
708 map_irq.devfn = dev->devfn;
709
710 if (type == PCI_CAP_ID_MSIX) {
711 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
712
713 pci_read_config_dword(dev, msix_table_offset_reg(pos),
714 &table_offset);
715 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
716
717 map_irq.table_base = pci_resource_start(dev, bir);
718 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
719 }
720
721 spin_lock(&irq_mapping_update_lock);
722
c9df1ce5 723 irq = xen_allocate_irq_dynamic();
f731e3ef
QH
724
725 if (irq == -1)
726 goto out;
727
728 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
729 if (rc) {
730 printk(KERN_WARNING "xen map irq failed %d\n", rc);
731
c9df1ce5 732 xen_free_irq(irq);
f731e3ef
QH
733
734 irq = -1;
735 goto out;
736 }
737 irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
738
739 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
740 handle_level_irq,
741 (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
742
743out:
744 spin_unlock(&irq_mapping_update_lock);
745 return irq;
746}
747#endif
748
b5401a96
AN
749int xen_destroy_irq(int irq)
750{
751 struct irq_desc *desc;
38aa66fc
JF
752 struct physdev_unmap_pirq unmap_irq;
753 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
754 int rc = -ENOENT;
755
756 spin_lock(&irq_mapping_update_lock);
757
758 desc = irq_to_desc(irq);
759 if (!desc)
760 goto out;
761
38aa66fc 762 if (xen_initial_domain()) {
12334715 763 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
764 unmap_irq.domid = DOMID_SELF;
765 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
766 if (rc) {
767 printk(KERN_WARNING "unmap irq failed %d\n", rc);
768 goto out;
769 }
770 }
1aa0b51a
KRW
771 pirq_to_irq[info->u.pirq.pirq] = -1;
772
b5401a96
AN
773 irq_info[irq] = mk_unbound_info();
774
c9df1ce5 775 xen_free_irq(irq);
b5401a96
AN
776
777out:
778 spin_unlock(&irq_mapping_update_lock);
779 return rc;
780}
781
d46a78b0
JF
782int xen_vector_from_irq(unsigned irq)
783{
784 return vector_from_irq(irq);
785}
786
787int xen_gsi_from_irq(unsigned irq)
788{
789 return gsi_from_irq(irq);
e46cdb66
JF
790}
791
af42b8d1
SS
792int xen_irq_from_pirq(unsigned pirq)
793{
794 return pirq_to_irq[pirq];
795}
796
b536b4b9 797int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
798{
799 int irq;
800
801 spin_lock(&irq_mapping_update_lock);
802
803 irq = evtchn_to_irq[evtchn];
804
805 if (irq == -1) {
c9df1ce5 806 irq = xen_allocate_irq_dynamic();
e46cdb66 807
e46cdb66 808 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 809 handle_fasteoi_irq, "event");
e46cdb66
JF
810
811 evtchn_to_irq[evtchn] = irq;
ced40d0f 812 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
813 }
814
e46cdb66
JF
815 spin_unlock(&irq_mapping_update_lock);
816
817 return irq;
818}
b536b4b9 819EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 820
f87e4cac
JF
821static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
822{
823 struct evtchn_bind_ipi bind_ipi;
824 int evtchn, irq;
825
826 spin_lock(&irq_mapping_update_lock);
827
828 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 829
f87e4cac 830 if (irq == -1) {
c9df1ce5 831 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
832 if (irq < 0)
833 goto out;
834
aaca4964
JF
835 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
836 handle_percpu_irq, "ipi");
f87e4cac
JF
837
838 bind_ipi.vcpu = cpu;
839 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
840 &bind_ipi) != 0)
841 BUG();
842 evtchn = bind_ipi.port;
843
844 evtchn_to_irq[evtchn] = irq;
ced40d0f 845 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
846 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
847
848 bind_evtchn_to_cpu(evtchn, cpu);
849 }
850
f87e4cac
JF
851 out:
852 spin_unlock(&irq_mapping_update_lock);
853 return irq;
854}
855
856
4fe7d5a7 857int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
858{
859 struct evtchn_bind_virq bind_virq;
860 int evtchn, irq;
861
862 spin_lock(&irq_mapping_update_lock);
863
864 irq = per_cpu(virq_to_irq, cpu)[virq];
865
866 if (irq == -1) {
c9df1ce5 867 irq = xen_allocate_irq_dynamic();
a52521f1
JF
868
869 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
870 handle_percpu_irq, "virq");
871
e46cdb66
JF
872 bind_virq.virq = virq;
873 bind_virq.vcpu = cpu;
874 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
875 &bind_virq) != 0)
876 BUG();
877 evtchn = bind_virq.port;
878
e46cdb66 879 evtchn_to_irq[evtchn] = irq;
ced40d0f 880 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
881
882 per_cpu(virq_to_irq, cpu)[virq] = irq;
883
884 bind_evtchn_to_cpu(evtchn, cpu);
885 }
886
e46cdb66
JF
887 spin_unlock(&irq_mapping_update_lock);
888
889 return irq;
890}
891
892static void unbind_from_irq(unsigned int irq)
893{
894 struct evtchn_close close;
895 int evtchn = evtchn_from_irq(irq);
896
897 spin_lock(&irq_mapping_update_lock);
898
d77bbd4d 899 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
900 close.port = evtchn;
901 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
902 BUG();
903
904 switch (type_from_irq(irq)) {
905 case IRQT_VIRQ:
906 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 907 [virq_from_irq(irq)] = -1;
e46cdb66 908 break;
d68d82af
AN
909 case IRQT_IPI:
910 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 911 [ipi_from_irq(irq)] = -1;
d68d82af 912 break;
e46cdb66
JF
913 default:
914 break;
915 }
916
917 /* Closed ports are implicitly re-bound to VCPU0. */
918 bind_evtchn_to_cpu(evtchn, 0);
919
920 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
921 }
922
923 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 924 irq_info[irq] = mk_unbound_info();
e46cdb66 925
c9df1ce5 926 xen_free_irq(irq);
e46cdb66
JF
927 }
928
929 spin_unlock(&irq_mapping_update_lock);
930}
931
932int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 933 irq_handler_t handler,
e46cdb66
JF
934 unsigned long irqflags,
935 const char *devname, void *dev_id)
936{
937 unsigned int irq;
938 int retval;
939
940 irq = bind_evtchn_to_irq(evtchn);
941 retval = request_irq(irq, handler, irqflags, devname, dev_id);
942 if (retval != 0) {
943 unbind_from_irq(irq);
944 return retval;
945 }
946
947 return irq;
948}
949EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
950
951int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 952 irq_handler_t handler,
e46cdb66
JF
953 unsigned long irqflags, const char *devname, void *dev_id)
954{
955 unsigned int irq;
956 int retval;
957
958 irq = bind_virq_to_irq(virq, cpu);
959 retval = request_irq(irq, handler, irqflags, devname, dev_id);
960 if (retval != 0) {
961 unbind_from_irq(irq);
962 return retval;
963 }
964
965 return irq;
966}
967EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
968
f87e4cac
JF
969int bind_ipi_to_irqhandler(enum ipi_vector ipi,
970 unsigned int cpu,
971 irq_handler_t handler,
972 unsigned long irqflags,
973 const char *devname,
974 void *dev_id)
975{
976 int irq, retval;
977
978 irq = bind_ipi_to_irq(ipi, cpu);
979 if (irq < 0)
980 return irq;
981
676dc3cf 982 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
983 retval = request_irq(irq, handler, irqflags, devname, dev_id);
984 if (retval != 0) {
985 unbind_from_irq(irq);
986 return retval;
987 }
988
989 return irq;
990}
991
e46cdb66
JF
992void unbind_from_irqhandler(unsigned int irq, void *dev_id)
993{
994 free_irq(irq, dev_id);
995 unbind_from_irq(irq);
996}
997EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
998
f87e4cac
JF
999void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1000{
1001 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1002 BUG_ON(irq < 0);
1003 notify_remote_via_irq(irq);
1004}
1005
ee523ca1
JF
1006irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1007{
1008 struct shared_info *sh = HYPERVISOR_shared_info;
1009 int cpu = smp_processor_id();
cb52e6d9 1010 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
1011 int i;
1012 unsigned long flags;
1013 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1014 struct vcpu_info *v;
ee523ca1
JF
1015
1016 spin_lock_irqsave(&debug_lock, flags);
1017
cb52e6d9 1018 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1019
1020 for_each_online_cpu(i) {
cb52e6d9
IC
1021 int pending;
1022 v = per_cpu(xen_vcpu, i);
1023 pending = (get_irq_regs() && i == cpu)
1024 ? xen_irqs_disabled(get_irq_regs())
1025 : v->evtchn_upcall_mask;
1026 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1027 pending, v->evtchn_upcall_pending,
1028 (int)(sizeof(v->evtchn_pending_sel)*2),
1029 v->evtchn_pending_sel);
1030 }
1031 v = per_cpu(xen_vcpu, cpu);
1032
1033 printk("\npending:\n ");
1034 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1035 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1036 sh->evtchn_pending[i],
1037 i % 8 == 0 ? "\n " : " ");
1038 printk("\nglobal mask:\n ");
1039 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1040 printk("%0*lx%s",
1041 (int)(sizeof(sh->evtchn_mask[0])*2),
1042 sh->evtchn_mask[i],
1043 i % 8 == 0 ? "\n " : " ");
1044
1045 printk("\nglobally unmasked:\n ");
1046 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1047 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1048 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1049 i % 8 == 0 ? "\n " : " ");
1050
1051 printk("\nlocal cpu%d mask:\n ", cpu);
1052 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1053 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1054 cpu_evtchn[i],
1055 i % 8 == 0 ? "\n " : " ");
1056
1057 printk("\nlocally unmasked:\n ");
1058 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1059 unsigned long pending = sh->evtchn_pending[i]
1060 & ~sh->evtchn_mask[i]
1061 & cpu_evtchn[i];
1062 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1063 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1064 }
ee523ca1
JF
1065
1066 printk("\npending list:\n");
cb52e6d9 1067 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1068 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1069 int word_idx = i / BITS_PER_LONG;
1070 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1071 cpu_from_evtchn(i), i,
cb52e6d9
IC
1072 evtchn_to_irq[i],
1073 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1074 ? "" : " l2-clear",
1075 !sync_test_bit(i, sh->evtchn_mask)
1076 ? "" : " globally-masked",
1077 sync_test_bit(i, cpu_evtchn)
1078 ? "" : " locally-masked");
ee523ca1
JF
1079 }
1080 }
1081
1082 spin_unlock_irqrestore(&debug_lock, flags);
1083
1084 return IRQ_HANDLED;
1085}
1086
245b2e70
TH
1087static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1088
e46cdb66
JF
1089/*
1090 * Search the CPUs pending events bitmasks. For each one found, map
1091 * the event number to an irq, and feed it into do_IRQ() for
1092 * handling.
1093 *
1094 * Xen uses a two-level bitmap to speed searching. The first level is
1095 * a bitset of words which contain pending event bits. The second
1096 * level is a bitset of pending events themselves.
1097 */
38e20b07 1098static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1099{
1100 int cpu = get_cpu();
1101 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1102 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1103 unsigned count;
e46cdb66 1104
229664be
JF
1105 do {
1106 unsigned long pending_words;
e46cdb66 1107
229664be 1108 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1109
b2e4ae69 1110 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1111 goto out;
e46cdb66 1112
e849c3e9
IY
1113#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1114 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1115 wmb();
e849c3e9 1116#endif
229664be
JF
1117 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1118 while (pending_words != 0) {
1119 unsigned long pending_bits;
1120 int word_idx = __ffs(pending_words);
1121 pending_words &= ~(1UL << word_idx);
1122
1123 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1124 int bit_idx = __ffs(pending_bits);
1125 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1126 int irq = evtchn_to_irq[port];
ca4dbc66 1127 struct irq_desc *desc;
229664be 1128
3588fe2e
JF
1129 mask_evtchn(port);
1130 clear_evtchn(port);
1131
ca4dbc66
EB
1132 if (irq != -1) {
1133 desc = irq_to_desc(irq);
1134 if (desc)
1135 generic_handle_irq_desc(irq, desc);
1136 }
e46cdb66
JF
1137 }
1138 }
e46cdb66 1139
229664be
JF
1140 BUG_ON(!irqs_disabled());
1141
780f36d8
CL
1142 count = __this_cpu_read(xed_nesting_count);
1143 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1144 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1145
1146out:
38e20b07
SY
1147
1148 put_cpu();
1149}
1150
1151void xen_evtchn_do_upcall(struct pt_regs *regs)
1152{
1153 struct pt_regs *old_regs = set_irq_regs(regs);
1154
1155 exit_idle();
1156 irq_enter();
1157
1158 __xen_evtchn_do_upcall();
1159
3445a8fd
JF
1160 irq_exit();
1161 set_irq_regs(old_regs);
38e20b07 1162}
3445a8fd 1163
38e20b07
SY
1164void xen_hvm_evtchn_do_upcall(void)
1165{
1166 __xen_evtchn_do_upcall();
e46cdb66 1167}
183d03cc 1168EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1169
eb1e305f
JF
1170/* Rebind a new event channel to an existing irq. */
1171void rebind_evtchn_irq(int evtchn, int irq)
1172{
d77bbd4d
JF
1173 struct irq_info *info = info_for_irq(irq);
1174
eb1e305f
JF
1175 /* Make sure the irq is masked, since the new event channel
1176 will also be masked. */
1177 disable_irq(irq);
1178
1179 spin_lock(&irq_mapping_update_lock);
1180
1181 /* After resume the irq<->evtchn mappings are all cleared out */
1182 BUG_ON(evtchn_to_irq[evtchn] != -1);
1183 /* Expect irq to have been bound before,
d77bbd4d
JF
1184 so there should be a proper type */
1185 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1186
1187 evtchn_to_irq[evtchn] = irq;
ced40d0f 1188 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1189
1190 spin_unlock(&irq_mapping_update_lock);
1191
1192 /* new event channels are always bound to cpu 0 */
0de26520 1193 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1194
1195 /* Unmask the event channel. */
1196 enable_irq(irq);
1197}
1198
e46cdb66 1199/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1200static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1201{
1202 struct evtchn_bind_vcpu bind_vcpu;
1203 int evtchn = evtchn_from_irq(irq);
1204
183d03cc
SS
1205 /* events delivered via platform PCI interrupts are always
1206 * routed to vcpu 0 */
1207 if (!VALID_EVTCHN(evtchn) ||
1208 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1209 return -1;
e46cdb66
JF
1210
1211 /* Send future instances of this interrupt to other vcpu. */
1212 bind_vcpu.port = evtchn;
1213 bind_vcpu.vcpu = tcpu;
1214
1215 /*
1216 * If this fails, it usually just indicates that we're dealing with a
1217 * virq or IPI channel, which don't actually need to be rebound. Ignore
1218 * it, but don't do the xenlinux-level rebind in that case.
1219 */
1220 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1221 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1222
d5dedd45
YL
1223 return 0;
1224}
e46cdb66 1225
c9e265e0
TG
1226static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1227 bool force)
e46cdb66 1228{
0de26520 1229 unsigned tcpu = cpumask_first(dest);
d5dedd45 1230
c9e265e0 1231 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1232}
1233
642e0c88
IY
1234int resend_irq_on_evtchn(unsigned int irq)
1235{
1236 int masked, evtchn = evtchn_from_irq(irq);
1237 struct shared_info *s = HYPERVISOR_shared_info;
1238
1239 if (!VALID_EVTCHN(evtchn))
1240 return 1;
1241
1242 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1243 sync_set_bit(evtchn, s->evtchn_pending);
1244 if (!masked)
1245 unmask_evtchn(evtchn);
1246
1247 return 1;
1248}
1249
c9e265e0 1250static void enable_dynirq(struct irq_data *data)
e46cdb66 1251{
c9e265e0 1252 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1253
1254 if (VALID_EVTCHN(evtchn))
1255 unmask_evtchn(evtchn);
1256}
1257
c9e265e0 1258static void disable_dynirq(struct irq_data *data)
e46cdb66 1259{
c9e265e0 1260 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1261
1262 if (VALID_EVTCHN(evtchn))
1263 mask_evtchn(evtchn);
1264}
1265
c9e265e0 1266static void ack_dynirq(struct irq_data *data)
e46cdb66 1267{
c9e265e0 1268 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1269
c9e265e0 1270 move_masked_irq(data->irq);
e46cdb66
JF
1271
1272 if (VALID_EVTCHN(evtchn))
3588fe2e 1273 unmask_evtchn(evtchn);
e46cdb66
JF
1274}
1275
c9e265e0 1276static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1277{
c9e265e0 1278 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1279 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1280 int ret = 0;
1281
1282 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1283 int masked;
1284
1285 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1286 sync_set_bit(evtchn, sh->evtchn_pending);
1287 if (!masked)
1288 unmask_evtchn(evtchn);
e46cdb66
JF
1289 ret = 1;
1290 }
1291
1292 return ret;
1293}
1294
9a069c33
SS
1295static void restore_cpu_pirqs(void)
1296{
1297 int pirq, rc, irq, gsi;
1298 struct physdev_map_pirq map_irq;
1299
1300 for (pirq = 0; pirq < nr_irqs; pirq++) {
1301 irq = pirq_to_irq[pirq];
1302 if (irq == -1)
1303 continue;
1304
1305 /* save/restore of PT devices doesn't work, so at this point the
1306 * only devices present are GSI based emulated devices */
1307 gsi = gsi_from_irq(irq);
1308 if (!gsi)
1309 continue;
1310
1311 map_irq.domid = DOMID_SELF;
1312 map_irq.type = MAP_PIRQ_TYPE_GSI;
1313 map_irq.index = gsi;
1314 map_irq.pirq = pirq;
1315
1316 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1317 if (rc) {
1318 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1319 gsi, irq, pirq, rc);
1320 irq_info[irq] = mk_unbound_info();
1321 pirq_to_irq[pirq] = -1;
1322 continue;
1323 }
1324
1325 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1326
c9e265e0 1327 __startup_pirq(irq);
9a069c33
SS
1328 }
1329}
1330
0e91398f
JF
1331static void restore_cpu_virqs(unsigned int cpu)
1332{
1333 struct evtchn_bind_virq bind_virq;
1334 int virq, irq, evtchn;
1335
1336 for (virq = 0; virq < NR_VIRQS; virq++) {
1337 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1338 continue;
1339
ced40d0f 1340 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1341
1342 /* Get a new binding from Xen. */
1343 bind_virq.virq = virq;
1344 bind_virq.vcpu = cpu;
1345 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1346 &bind_virq) != 0)
1347 BUG();
1348 evtchn = bind_virq.port;
1349
1350 /* Record the new mapping. */
1351 evtchn_to_irq[evtchn] = irq;
ced40d0f 1352 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1353 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1354 }
1355}
1356
1357static void restore_cpu_ipis(unsigned int cpu)
1358{
1359 struct evtchn_bind_ipi bind_ipi;
1360 int ipi, irq, evtchn;
1361
1362 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1363 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1364 continue;
1365
ced40d0f 1366 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1367
1368 /* Get a new binding from Xen. */
1369 bind_ipi.vcpu = cpu;
1370 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1371 &bind_ipi) != 0)
1372 BUG();
1373 evtchn = bind_ipi.port;
1374
1375 /* Record the new mapping. */
1376 evtchn_to_irq[evtchn] = irq;
ced40d0f 1377 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1378 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1379 }
1380}
1381
2d9e1e2f
JF
1382/* Clear an irq's pending state, in preparation for polling on it */
1383void xen_clear_irq_pending(int irq)
1384{
1385 int evtchn = evtchn_from_irq(irq);
1386
1387 if (VALID_EVTCHN(evtchn))
1388 clear_evtchn(evtchn);
1389}
d9a8814f 1390EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1391void xen_set_irq_pending(int irq)
1392{
1393 int evtchn = evtchn_from_irq(irq);
1394
1395 if (VALID_EVTCHN(evtchn))
1396 set_evtchn(evtchn);
1397}
1398
1399bool xen_test_irq_pending(int irq)
1400{
1401 int evtchn = evtchn_from_irq(irq);
1402 bool ret = false;
1403
1404 if (VALID_EVTCHN(evtchn))
1405 ret = test_evtchn(evtchn);
1406
1407 return ret;
1408}
1409
d9a8814f
KRW
1410/* Poll waiting for an irq to become pending with timeout. In the usual case,
1411 * the irq will be disabled so it won't deliver an interrupt. */
1412void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1413{
1414 evtchn_port_t evtchn = evtchn_from_irq(irq);
1415
1416 if (VALID_EVTCHN(evtchn)) {
1417 struct sched_poll poll;
1418
1419 poll.nr_ports = 1;
d9a8814f 1420 poll.timeout = timeout;
ff3c5362 1421 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1422
1423 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1424 BUG();
1425 }
1426}
d9a8814f
KRW
1427EXPORT_SYMBOL(xen_poll_irq_timeout);
1428/* Poll waiting for an irq to become pending. In the usual case, the
1429 * irq will be disabled so it won't deliver an interrupt. */
1430void xen_poll_irq(int irq)
1431{
1432 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1433}
2d9e1e2f 1434
0e91398f
JF
1435void xen_irq_resume(void)
1436{
1437 unsigned int cpu, irq, evtchn;
1438
1439 init_evtchn_cpu_bindings();
1440
1441 /* New event-channel space is not 'live' yet. */
1442 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1443 mask_evtchn(evtchn);
1444
1445 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1446 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1447 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1448
1449 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1450 evtchn_to_irq[evtchn] = -1;
1451
1452 for_each_possible_cpu(cpu) {
1453 restore_cpu_virqs(cpu);
1454 restore_cpu_ipis(cpu);
1455 }
6903591f 1456
9a069c33 1457 restore_cpu_pirqs();
0e91398f
JF
1458}
1459
e46cdb66 1460static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1461 .name = "xen-dyn",
54a353a0 1462
c9e265e0
TG
1463 .irq_disable = disable_dynirq,
1464 .irq_mask = disable_dynirq,
1465 .irq_unmask = enable_dynirq,
54a353a0 1466
c9e265e0
TG
1467 .irq_eoi = ack_dynirq,
1468 .irq_set_affinity = set_affinity_irq,
1469 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1470};
1471
d46a78b0 1472static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1473 .name = "xen-pirq",
d46a78b0 1474
c9e265e0
TG
1475 .irq_startup = startup_pirq,
1476 .irq_shutdown = shutdown_pirq,
d46a78b0 1477
c9e265e0
TG
1478 .irq_enable = enable_pirq,
1479 .irq_unmask = enable_pirq,
d46a78b0 1480
c9e265e0
TG
1481 .irq_disable = disable_pirq,
1482 .irq_mask = disable_pirq,
d46a78b0 1483
c9e265e0 1484 .irq_ack = ack_pirq,
d46a78b0 1485
c9e265e0 1486 .irq_set_affinity = set_affinity_irq,
d46a78b0 1487
c9e265e0 1488 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1489};
1490
aaca4964 1491static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1492 .name = "xen-percpu",
aaca4964 1493
c9e265e0
TG
1494 .irq_disable = disable_dynirq,
1495 .irq_mask = disable_dynirq,
1496 .irq_unmask = enable_dynirq,
aaca4964 1497
c9e265e0 1498 .irq_ack = ack_dynirq,
aaca4964
JF
1499};
1500
38e20b07
SY
1501int xen_set_callback_via(uint64_t via)
1502{
1503 struct xen_hvm_param a;
1504 a.domid = DOMID_SELF;
1505 a.index = HVM_PARAM_CALLBACK_IRQ;
1506 a.value = via;
1507 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1508}
1509EXPORT_SYMBOL_GPL(xen_set_callback_via);
1510
ca65f9fc 1511#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1512/* Vector callbacks are better than PCI interrupts to receive event
1513 * channel notifications because we can receive vector callbacks on any
1514 * vcpu and we don't need PCI support or APIC interactions. */
1515void xen_callback_vector(void)
1516{
1517 int rc;
1518 uint64_t callback_via;
1519 if (xen_have_vector_callback) {
1520 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1521 rc = xen_set_callback_via(callback_via);
1522 if (rc) {
1523 printk(KERN_ERR "Request for Xen HVM callback vector"
1524 " failed.\n");
1525 xen_have_vector_callback = 0;
1526 return;
1527 }
1528 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1529 "enabled\n");
1530 /* in the restore case the vector has already been allocated */
1531 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1532 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1533 }
1534}
ca65f9fc
SS
1535#else
1536void xen_callback_vector(void) {}
1537#endif
38e20b07 1538
e46cdb66
JF
1539void __init xen_init_IRQ(void)
1540{
e5fc7345 1541 int i;
c7a3589e 1542
a70c352a
PE
1543 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1544 GFP_KERNEL);
b21ddbf5
JF
1545 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1546
e5fc7345
SS
1547 /* We are using nr_irqs as the maximum number of pirq available but
1548 * that number is actually chosen by Xen and we don't know exactly
1549 * what it is. Be careful choosing high pirq numbers. */
1550 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1551 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1552 pirq_to_irq[i] = -1;
1553
b21ddbf5
JF
1554 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1555 GFP_KERNEL);
1556 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1557 evtchn_to_irq[i] = -1;
e46cdb66
JF
1558
1559 init_evtchn_cpu_bindings();
1560
1561 /* No event channels are 'live' right now. */
1562 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1563 mask_evtchn(i);
1564
38e20b07
SY
1565 if (xen_hvm_domain()) {
1566 xen_callback_vector();
1567 native_init_IRQ();
3942b740
SS
1568 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1569 * __acpi_register_gsi can point at the right function */
1570 pci_xen_hvm_init();
38e20b07
SY
1571 } else {
1572 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1573 if (xen_initial_domain())
1574 xen_setup_pirqs();
38e20b07 1575 }
e46cdb66 1576}