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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
e46cdb66 | 32 | |
38e20b07 | 33 | #include <asm/desc.h> |
e46cdb66 JF |
34 | #include <asm/ptrace.h> |
35 | #include <asm/irq.h> | |
792dc4f6 | 36 | #include <asm/idle.h> |
0794bfc7 | 37 | #include <asm/io_apic.h> |
e46cdb66 | 38 | #include <asm/sync_bitops.h> |
42a1de56 | 39 | #include <asm/xen/pci.h> |
e46cdb66 | 40 | #include <asm/xen/hypercall.h> |
8d1b8753 | 41 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 42 | |
38e20b07 SY |
43 | #include <xen/xen.h> |
44 | #include <xen/hvm.h> | |
e04d0d07 | 45 | #include <xen/xen-ops.h> |
e46cdb66 JF |
46 | #include <xen/events.h> |
47 | #include <xen/interface/xen.h> | |
48 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
49 | #include <xen/interface/hvm/hvm_op.h> |
50 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 51 | |
e46cdb66 JF |
52 | /* |
53 | * This lock protects updates to the following mapping and reference-count | |
54 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
55 | */ | |
56 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
57 | ||
58 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 59 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 60 | |
f87e4cac | 61 | /* IRQ <-> IPI mapping */ |
204fba4a | 62 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 63 | |
ced40d0f JF |
64 | /* Interrupt types. */ |
65 | enum xen_irq_type { | |
d77bbd4d | 66 | IRQT_UNBOUND = 0, |
f87e4cac JF |
67 | IRQT_PIRQ, |
68 | IRQT_VIRQ, | |
69 | IRQT_IPI, | |
70 | IRQT_EVTCHN | |
71 | }; | |
e46cdb66 | 72 | |
ced40d0f JF |
73 | /* |
74 | * Packed IRQ information: | |
75 | * type - enum xen_irq_type | |
76 | * event channel - irq->event channel mapping | |
77 | * cpu - cpu this event channel is bound to | |
78 | * index - type-specific information: | |
42a1de56 SS |
79 | * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM |
80 | * guest, or GSI (real passthrough IRQ) of the device. | |
ced40d0f JF |
81 | * VIRQ - virq number |
82 | * IPI - IPI vector | |
83 | * EVTCHN - | |
84 | */ | |
85 | struct irq_info | |
86 | { | |
87 | enum xen_irq_type type; /* type */ | |
88 | unsigned short evtchn; /* event channel */ | |
89 | unsigned short cpu; /* cpu bound */ | |
90 | ||
91 | union { | |
92 | unsigned short virq; | |
93 | enum ipi_vector ipi; | |
94 | struct { | |
7a043f11 | 95 | unsigned short pirq; |
ced40d0f | 96 | unsigned short gsi; |
d46a78b0 JF |
97 | unsigned char vector; |
98 | unsigned char flags; | |
ced40d0f JF |
99 | } pirq; |
100 | } u; | |
101 | }; | |
d46a78b0 | 102 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 103 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 104 | |
b21ddbf5 | 105 | static struct irq_info *irq_info; |
7a043f11 | 106 | static int *pirq_to_irq; |
01557baf | 107 | static int nr_pirqs; |
e46cdb66 | 108 | |
b21ddbf5 | 109 | static int *evtchn_to_irq; |
c7a3589e MT |
110 | struct cpu_evtchn_s { |
111 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
112 | }; | |
3b32f574 JF |
113 | |
114 | static __initdata struct cpu_evtchn_s init_evtchn_mask = { | |
115 | .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul, | |
116 | }; | |
117 | static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask; | |
118 | ||
c7a3589e MT |
119 | static inline unsigned long *cpu_evtchn_mask(int cpu) |
120 | { | |
121 | return cpu_evtchn_mask_p[cpu].bits; | |
122 | } | |
e46cdb66 | 123 | |
e46cdb66 JF |
124 | /* Xen will never allocate port zero for any purpose. */ |
125 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
126 | ||
e46cdb66 | 127 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 128 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 129 | static struct irq_chip xen_pirq_chip; |
e46cdb66 JF |
130 | |
131 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
132 | static struct irq_info mk_unbound_info(void) |
133 | { | |
134 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
135 | } | |
136 | ||
137 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
138 | { | |
90af9514 IC |
139 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn, |
140 | .cpu = 0 }; | |
ced40d0f JF |
141 | } |
142 | ||
143 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 144 | { |
ced40d0f | 145 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
90af9514 | 146 | .cpu = 0, .u.ipi = ipi }; |
ced40d0f JF |
147 | } |
148 | ||
149 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
150 | { | |
151 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
90af9514 | 152 | .cpu = 0, .u.virq = virq }; |
ced40d0f JF |
153 | } |
154 | ||
7a043f11 | 155 | static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq, |
ced40d0f JF |
156 | unsigned short gsi, unsigned short vector) |
157 | { | |
158 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
7a043f11 SS |
159 | .cpu = 0, |
160 | .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } }; | |
e46cdb66 JF |
161 | } |
162 | ||
163 | /* | |
164 | * Accessors for packed IRQ information. | |
165 | */ | |
ced40d0f | 166 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 167 | { |
ced40d0f | 168 | return &irq_info[irq]; |
e46cdb66 JF |
169 | } |
170 | ||
ced40d0f | 171 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 172 | { |
ced40d0f | 173 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
174 | } |
175 | ||
d4c04536 IC |
176 | unsigned irq_from_evtchn(unsigned int evtchn) |
177 | { | |
178 | return evtchn_to_irq[evtchn]; | |
179 | } | |
180 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
181 | ||
ced40d0f | 182 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 183 | { |
ced40d0f JF |
184 | struct irq_info *info = info_for_irq(irq); |
185 | ||
186 | BUG_ON(info == NULL); | |
187 | BUG_ON(info->type != IRQT_IPI); | |
188 | ||
189 | return info->u.ipi; | |
190 | } | |
191 | ||
192 | static unsigned virq_from_irq(unsigned irq) | |
193 | { | |
194 | struct irq_info *info = info_for_irq(irq); | |
195 | ||
196 | BUG_ON(info == NULL); | |
197 | BUG_ON(info->type != IRQT_VIRQ); | |
198 | ||
199 | return info->u.virq; | |
200 | } | |
201 | ||
7a043f11 SS |
202 | static unsigned pirq_from_irq(unsigned irq) |
203 | { | |
204 | struct irq_info *info = info_for_irq(irq); | |
205 | ||
206 | BUG_ON(info == NULL); | |
207 | BUG_ON(info->type != IRQT_PIRQ); | |
208 | ||
209 | return info->u.pirq.pirq; | |
210 | } | |
211 | ||
ced40d0f JF |
212 | static unsigned gsi_from_irq(unsigned irq) |
213 | { | |
214 | struct irq_info *info = info_for_irq(irq); | |
215 | ||
216 | BUG_ON(info == NULL); | |
217 | BUG_ON(info->type != IRQT_PIRQ); | |
218 | ||
219 | return info->u.pirq.gsi; | |
220 | } | |
221 | ||
222 | static unsigned vector_from_irq(unsigned irq) | |
223 | { | |
224 | struct irq_info *info = info_for_irq(irq); | |
225 | ||
226 | BUG_ON(info == NULL); | |
227 | BUG_ON(info->type != IRQT_PIRQ); | |
228 | ||
229 | return info->u.pirq.vector; | |
230 | } | |
231 | ||
232 | static enum xen_irq_type type_from_irq(unsigned irq) | |
233 | { | |
234 | return info_for_irq(irq)->type; | |
235 | } | |
236 | ||
237 | static unsigned cpu_from_irq(unsigned irq) | |
238 | { | |
239 | return info_for_irq(irq)->cpu; | |
240 | } | |
241 | ||
242 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
243 | { | |
244 | int irq = evtchn_to_irq[evtchn]; | |
245 | unsigned ret = 0; | |
246 | ||
247 | if (irq != -1) | |
248 | ret = cpu_from_irq(irq); | |
249 | ||
250 | return ret; | |
e46cdb66 JF |
251 | } |
252 | ||
d46a78b0 JF |
253 | static bool pirq_needs_eoi(unsigned irq) |
254 | { | |
255 | struct irq_info *info = info_for_irq(irq); | |
256 | ||
257 | BUG_ON(info->type != IRQT_PIRQ); | |
258 | ||
259 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
260 | } | |
261 | ||
e46cdb66 JF |
262 | static inline unsigned long active_evtchns(unsigned int cpu, |
263 | struct shared_info *sh, | |
264 | unsigned int idx) | |
265 | { | |
266 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 267 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
268 | ~sh->evtchn_mask[idx]); |
269 | } | |
270 | ||
271 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
272 | { | |
273 | int irq = evtchn_to_irq[chn]; | |
274 | ||
275 | BUG_ON(irq == -1); | |
276 | #ifdef CONFIG_SMP | |
7f7ace0c | 277 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
278 | #endif |
279 | ||
ced40d0f | 280 | __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
c7a3589e | 281 | __set_bit(chn, cpu_evtchn_mask(cpu)); |
e46cdb66 | 282 | |
ced40d0f | 283 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
284 | } |
285 | ||
286 | static void init_evtchn_cpu_bindings(void) | |
287 | { | |
288 | #ifdef CONFIG_SMP | |
10e58084 | 289 | struct irq_desc *desc; |
e46cdb66 | 290 | int i; |
10e58084 | 291 | |
e46cdb66 | 292 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 293 | for_each_irq_desc(i, desc) { |
7f7ace0c | 294 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 295 | } |
e46cdb66 JF |
296 | #endif |
297 | ||
c7a3589e | 298 | memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0))); |
e46cdb66 JF |
299 | } |
300 | ||
e46cdb66 JF |
301 | static inline void clear_evtchn(int port) |
302 | { | |
303 | struct shared_info *s = HYPERVISOR_shared_info; | |
304 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
305 | } | |
306 | ||
307 | static inline void set_evtchn(int port) | |
308 | { | |
309 | struct shared_info *s = HYPERVISOR_shared_info; | |
310 | sync_set_bit(port, &s->evtchn_pending[0]); | |
311 | } | |
312 | ||
168d2f46 JF |
313 | static inline int test_evtchn(int port) |
314 | { | |
315 | struct shared_info *s = HYPERVISOR_shared_info; | |
316 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
317 | } | |
318 | ||
e46cdb66 JF |
319 | |
320 | /** | |
321 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
322 | * @irq: irq of event channel to send event to | |
323 | * | |
324 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
325 | * save/restore. Notifications on a broken connection are silently | |
326 | * dropped. | |
327 | */ | |
328 | void notify_remote_via_irq(int irq) | |
329 | { | |
330 | int evtchn = evtchn_from_irq(irq); | |
331 | ||
332 | if (VALID_EVTCHN(evtchn)) | |
333 | notify_remote_via_evtchn(evtchn); | |
334 | } | |
335 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
336 | ||
337 | static void mask_evtchn(int port) | |
338 | { | |
339 | struct shared_info *s = HYPERVISOR_shared_info; | |
340 | sync_set_bit(port, &s->evtchn_mask[0]); | |
341 | } | |
342 | ||
343 | static void unmask_evtchn(int port) | |
344 | { | |
345 | struct shared_info *s = HYPERVISOR_shared_info; | |
346 | unsigned int cpu = get_cpu(); | |
347 | ||
348 | BUG_ON(!irqs_disabled()); | |
349 | ||
350 | /* Slow path (hypercall) if this is a non-local port. */ | |
351 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
352 | struct evtchn_unmask unmask = { .port = port }; | |
353 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
354 | } else { | |
355 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
356 | ||
357 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
358 | ||
359 | /* | |
360 | * The following is basically the equivalent of | |
361 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
362 | * the interrupt edge' if the channel is masked. | |
363 | */ | |
364 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
365 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
366 | &vcpu_info->evtchn_pending_sel)) | |
367 | vcpu_info->evtchn_upcall_pending = 1; | |
368 | } | |
369 | ||
370 | put_cpu(); | |
371 | } | |
372 | ||
0794bfc7 KRW |
373 | static int get_nr_hw_irqs(void) |
374 | { | |
375 | int ret = 1; | |
376 | ||
377 | #ifdef CONFIG_X86_IO_APIC | |
378 | ret = get_nr_irqs_gsi(); | |
379 | #endif | |
380 | ||
381 | return ret; | |
382 | } | |
383 | ||
01557baf SS |
384 | /* callers of this function should make sure that PHYSDEVOP_get_nr_pirqs |
385 | * succeeded otherwise nr_pirqs won't hold the right value */ | |
7a043f11 SS |
386 | static int find_unbound_pirq(void) |
387 | { | |
388 | int i; | |
01557baf | 389 | for (i = nr_pirqs-1; i >= 0; i--) { |
7a043f11 SS |
390 | if (pirq_to_irq[i] < 0) |
391 | return i; | |
392 | } | |
393 | return -1; | |
394 | } | |
395 | ||
e46cdb66 JF |
396 | static int find_unbound_irq(void) |
397 | { | |
77dff1c7 TG |
398 | struct irq_data *data; |
399 | int irq, res; | |
3a69e916 | 400 | int start = get_nr_hw_irqs(); |
e46cdb66 | 401 | |
3a69e916 KRW |
402 | if (start == nr_irqs) |
403 | goto no_irqs; | |
404 | ||
405 | /* nr_irqs is a magic value. Must not use it.*/ | |
406 | for (irq = nr_irqs-1; irq > start; irq--) { | |
77dff1c7 | 407 | data = irq_get_irq_data(irq); |
99ad198c | 408 | /* only 0->15 have init'd desc; handle irq > 16 */ |
77dff1c7 | 409 | if (!data) |
99ad198c | 410 | break; |
77dff1c7 | 411 | if (data->chip == &no_irq_chip) |
99ad198c | 412 | break; |
77dff1c7 | 413 | if (data->chip != &xen_dynamic_chip) |
99ad198c | 414 | continue; |
d77bbd4d | 415 | if (irq_info[irq].type == IRQT_UNBOUND) |
77dff1c7 | 416 | return irq; |
99ad198c | 417 | } |
e46cdb66 | 418 | |
3a69e916 KRW |
419 | if (irq == start) |
420 | goto no_irqs; | |
e46cdb66 | 421 | |
77dff1c7 | 422 | res = irq_alloc_desc_at(irq, 0); |
6f8a0ed4 | 423 | |
77dff1c7 TG |
424 | if (WARN_ON(res != irq)) |
425 | return -1; | |
ced40d0f | 426 | |
e46cdb66 | 427 | return irq; |
3a69e916 KRW |
428 | |
429 | no_irqs: | |
430 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 JF |
431 | } |
432 | ||
d46a78b0 JF |
433 | static bool identity_mapped_irq(unsigned irq) |
434 | { | |
0794bfc7 KRW |
435 | /* identity map all the hardware irqs */ |
436 | return irq < get_nr_hw_irqs(); | |
d46a78b0 JF |
437 | } |
438 | ||
439 | static void pirq_unmask_notify(int irq) | |
440 | { | |
7a043f11 | 441 | struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) }; |
d46a78b0 JF |
442 | |
443 | if (unlikely(pirq_needs_eoi(irq))) { | |
444 | int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
445 | WARN_ON(rc); | |
446 | } | |
447 | } | |
448 | ||
449 | static void pirq_query_unmask(int irq) | |
450 | { | |
451 | struct physdev_irq_status_query irq_status; | |
452 | struct irq_info *info = info_for_irq(irq); | |
453 | ||
454 | BUG_ON(info->type != IRQT_PIRQ); | |
455 | ||
7a043f11 | 456 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
457 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
458 | irq_status.flags = 0; | |
459 | ||
460 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
461 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
462 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
463 | } | |
464 | ||
465 | static bool probing_irq(int irq) | |
466 | { | |
467 | struct irq_desc *desc = irq_to_desc(irq); | |
468 | ||
469 | return desc && desc->action == NULL; | |
470 | } | |
471 | ||
472 | static unsigned int startup_pirq(unsigned int irq) | |
473 | { | |
474 | struct evtchn_bind_pirq bind_pirq; | |
475 | struct irq_info *info = info_for_irq(irq); | |
476 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 477 | int rc; |
d46a78b0 JF |
478 | |
479 | BUG_ON(info->type != IRQT_PIRQ); | |
480 | ||
481 | if (VALID_EVTCHN(evtchn)) | |
482 | goto out; | |
483 | ||
7a043f11 | 484 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 485 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
486 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
487 | BIND_PIRQ__WILL_SHARE : 0; | |
488 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
489 | if (rc != 0) { | |
d46a78b0 JF |
490 | if (!probing_irq(irq)) |
491 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
492 | irq); | |
493 | return 0; | |
494 | } | |
495 | evtchn = bind_pirq.port; | |
496 | ||
497 | pirq_query_unmask(irq); | |
498 | ||
499 | evtchn_to_irq[evtchn] = irq; | |
500 | bind_evtchn_to_cpu(evtchn, 0); | |
501 | info->evtchn = evtchn; | |
502 | ||
503 | out: | |
504 | unmask_evtchn(evtchn); | |
505 | pirq_unmask_notify(irq); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static void shutdown_pirq(unsigned int irq) | |
511 | { | |
512 | struct evtchn_close close; | |
513 | struct irq_info *info = info_for_irq(irq); | |
514 | int evtchn = evtchn_from_irq(irq); | |
515 | ||
516 | BUG_ON(info->type != IRQT_PIRQ); | |
517 | ||
518 | if (!VALID_EVTCHN(evtchn)) | |
519 | return; | |
520 | ||
521 | mask_evtchn(evtchn); | |
522 | ||
523 | close.port = evtchn; | |
524 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
525 | BUG(); | |
526 | ||
527 | bind_evtchn_to_cpu(evtchn, 0); | |
528 | evtchn_to_irq[evtchn] = -1; | |
529 | info->evtchn = 0; | |
530 | } | |
531 | ||
532 | static void enable_pirq(unsigned int irq) | |
533 | { | |
534 | startup_pirq(irq); | |
535 | } | |
536 | ||
537 | static void disable_pirq(unsigned int irq) | |
538 | { | |
539 | } | |
540 | ||
541 | static void ack_pirq(unsigned int irq) | |
542 | { | |
543 | int evtchn = evtchn_from_irq(irq); | |
544 | ||
545 | move_native_irq(irq); | |
546 | ||
547 | if (VALID_EVTCHN(evtchn)) { | |
548 | mask_evtchn(evtchn); | |
549 | clear_evtchn(evtchn); | |
550 | } | |
551 | } | |
552 | ||
553 | static void end_pirq(unsigned int irq) | |
554 | { | |
555 | int evtchn = evtchn_from_irq(irq); | |
556 | struct irq_desc *desc = irq_to_desc(irq); | |
557 | ||
558 | if (WARN_ON(!desc)) | |
559 | return; | |
560 | ||
561 | if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) == | |
562 | (IRQ_DISABLED|IRQ_PENDING)) { | |
563 | shutdown_pirq(irq); | |
564 | } else if (VALID_EVTCHN(evtchn)) { | |
565 | unmask_evtchn(evtchn); | |
566 | pirq_unmask_notify(irq); | |
567 | } | |
568 | } | |
569 | ||
570 | static int find_irq_by_gsi(unsigned gsi) | |
571 | { | |
572 | int irq; | |
573 | ||
b21ddbf5 | 574 | for (irq = 0; irq < nr_irqs; irq++) { |
d46a78b0 JF |
575 | struct irq_info *info = info_for_irq(irq); |
576 | ||
577 | if (info == NULL || info->type != IRQT_PIRQ) | |
578 | continue; | |
579 | ||
580 | if (gsi_from_irq(irq) == gsi) | |
581 | return irq; | |
582 | } | |
583 | ||
584 | return -1; | |
585 | } | |
586 | ||
7a043f11 SS |
587 | int xen_allocate_pirq(unsigned gsi, int shareable, char *name) |
588 | { | |
589 | return xen_map_pirq_gsi(gsi, gsi, shareable, name); | |
590 | } | |
591 | ||
592 | /* xen_map_pirq_gsi might allocate irqs from the top down, as a | |
3a69e916 KRW |
593 | * consequence don't assume that the irq number returned has a low value |
594 | * or can be used as a pirq number unless you know otherwise. | |
595 | * | |
7a043f11 | 596 | * One notable exception is when xen_map_pirq_gsi is called passing an |
3a69e916 | 597 | * hardware gsi as argument, in that case the irq number returned |
7a043f11 SS |
598 | * matches the gsi number passed as second argument. |
599 | * | |
600 | * Note: We don't assign an event channel until the irq actually started | |
601 | * up. Return an existing irq if we've already got one for the gsi. | |
d46a78b0 | 602 | */ |
7a043f11 | 603 | int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name) |
d46a78b0 | 604 | { |
7a043f11 | 605 | int irq = 0; |
d46a78b0 JF |
606 | struct physdev_irq irq_op; |
607 | ||
608 | spin_lock(&irq_mapping_update_lock); | |
609 | ||
01557baf SS |
610 | if ((pirq > nr_pirqs) || (gsi > nr_irqs)) { |
611 | printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n", | |
612 | pirq > nr_pirqs ? "nr_pirqs" :"", | |
613 | gsi > nr_irqs ? "nr_irqs" : ""); | |
614 | goto out; | |
615 | } | |
616 | ||
d46a78b0 JF |
617 | irq = find_irq_by_gsi(gsi); |
618 | if (irq != -1) { | |
7a043f11 | 619 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 JF |
620 | irq, gsi); |
621 | goto out; /* XXX need refcount? */ | |
622 | } | |
623 | ||
b5401a96 AN |
624 | /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore |
625 | * we are using the !xen_initial_domain() to drop in the function.*/ | |
3942b740 SS |
626 | if (identity_mapped_irq(gsi) || (!xen_initial_domain() && |
627 | xen_pv_domain())) { | |
d46a78b0 | 628 | irq = gsi; |
2c52f8d3 | 629 | irq_alloc_desc_at(irq, 0); |
d46a78b0 JF |
630 | } else |
631 | irq = find_unbound_irq(); | |
632 | ||
633 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
1a60d05f | 634 | handle_level_irq, name); |
d46a78b0 JF |
635 | |
636 | irq_op.irq = irq; | |
b5401a96 AN |
637 | irq_op.vector = 0; |
638 | ||
639 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
640 | * driver provides a PCI bus that does the call to do exactly | |
641 | * this in the priv domain. */ | |
642 | if (xen_initial_domain() && | |
643 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
2c52f8d3 | 644 | irq_free_desc(irq); |
d46a78b0 JF |
645 | irq = -ENOSPC; |
646 | goto out; | |
647 | } | |
648 | ||
7a043f11 | 649 | irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector); |
15ebbb82 | 650 | irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0; |
7a043f11 | 651 | pirq_to_irq[pirq] = irq; |
d46a78b0 JF |
652 | |
653 | out: | |
654 | spin_unlock(&irq_mapping_update_lock); | |
655 | ||
656 | return irq; | |
657 | } | |
658 | ||
809f9267 SS |
659 | void xen_allocate_pirq_msi(char *name, int *irq, int *pirq) |
660 | { | |
661 | spin_lock(&irq_mapping_update_lock); | |
662 | ||
663 | *irq = find_unbound_irq(); | |
664 | if (*irq == -1) | |
665 | goto out; | |
666 | ||
667 | *pirq = find_unbound_pirq(); | |
668 | if (*pirq == -1) | |
669 | goto out; | |
670 | ||
671 | set_irq_chip_and_handler_name(*irq, &xen_pirq_chip, | |
672 | handle_level_irq, name); | |
673 | ||
674 | irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0); | |
675 | pirq_to_irq[*pirq] = *irq; | |
676 | ||
677 | out: | |
678 | spin_unlock(&irq_mapping_update_lock); | |
679 | } | |
680 | ||
b5401a96 AN |
681 | int xen_destroy_irq(int irq) |
682 | { | |
683 | struct irq_desc *desc; | |
684 | int rc = -ENOENT; | |
685 | ||
686 | spin_lock(&irq_mapping_update_lock); | |
687 | ||
688 | desc = irq_to_desc(irq); | |
689 | if (!desc) | |
690 | goto out; | |
691 | ||
692 | irq_info[irq] = mk_unbound_info(); | |
693 | ||
2c52f8d3 | 694 | irq_free_desc(irq); |
b5401a96 AN |
695 | |
696 | out: | |
697 | spin_unlock(&irq_mapping_update_lock); | |
698 | return rc; | |
699 | } | |
700 | ||
d46a78b0 JF |
701 | int xen_vector_from_irq(unsigned irq) |
702 | { | |
703 | return vector_from_irq(irq); | |
704 | } | |
705 | ||
706 | int xen_gsi_from_irq(unsigned irq) | |
707 | { | |
708 | return gsi_from_irq(irq); | |
709 | } | |
710 | ||
b536b4b9 | 711 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
712 | { |
713 | int irq; | |
714 | ||
715 | spin_lock(&irq_mapping_update_lock); | |
716 | ||
717 | irq = evtchn_to_irq[evtchn]; | |
718 | ||
719 | if (irq == -1) { | |
720 | irq = find_unbound_irq(); | |
721 | ||
e46cdb66 | 722 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
dffe2e1e | 723 | handle_edge_irq, "event"); |
e46cdb66 JF |
724 | |
725 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 726 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
727 | } |
728 | ||
e46cdb66 JF |
729 | spin_unlock(&irq_mapping_update_lock); |
730 | ||
731 | return irq; | |
732 | } | |
b536b4b9 | 733 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 734 | |
f87e4cac JF |
735 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
736 | { | |
737 | struct evtchn_bind_ipi bind_ipi; | |
738 | int evtchn, irq; | |
739 | ||
740 | spin_lock(&irq_mapping_update_lock); | |
741 | ||
742 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 743 | |
f87e4cac JF |
744 | if (irq == -1) { |
745 | irq = find_unbound_irq(); | |
746 | if (irq < 0) | |
747 | goto out; | |
748 | ||
aaca4964 JF |
749 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
750 | handle_percpu_irq, "ipi"); | |
f87e4cac JF |
751 | |
752 | bind_ipi.vcpu = cpu; | |
753 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
754 | &bind_ipi) != 0) | |
755 | BUG(); | |
756 | evtchn = bind_ipi.port; | |
757 | ||
758 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 759 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
760 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
761 | ||
762 | bind_evtchn_to_cpu(evtchn, cpu); | |
763 | } | |
764 | ||
f87e4cac JF |
765 | out: |
766 | spin_unlock(&irq_mapping_update_lock); | |
767 | return irq; | |
768 | } | |
769 | ||
770 | ||
e46cdb66 JF |
771 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
772 | { | |
773 | struct evtchn_bind_virq bind_virq; | |
774 | int evtchn, irq; | |
775 | ||
776 | spin_lock(&irq_mapping_update_lock); | |
777 | ||
778 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
779 | ||
780 | if (irq == -1) { | |
781 | bind_virq.virq = virq; | |
782 | bind_virq.vcpu = cpu; | |
783 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
784 | &bind_virq) != 0) | |
785 | BUG(); | |
786 | evtchn = bind_virq.port; | |
787 | ||
788 | irq = find_unbound_irq(); | |
789 | ||
aaca4964 JF |
790 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
791 | handle_percpu_irq, "virq"); | |
e46cdb66 JF |
792 | |
793 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 794 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
795 | |
796 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
797 | ||
798 | bind_evtchn_to_cpu(evtchn, cpu); | |
799 | } | |
800 | ||
e46cdb66 JF |
801 | spin_unlock(&irq_mapping_update_lock); |
802 | ||
803 | return irq; | |
804 | } | |
805 | ||
806 | static void unbind_from_irq(unsigned int irq) | |
807 | { | |
808 | struct evtchn_close close; | |
809 | int evtchn = evtchn_from_irq(irq); | |
810 | ||
811 | spin_lock(&irq_mapping_update_lock); | |
812 | ||
d77bbd4d | 813 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
814 | close.port = evtchn; |
815 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
816 | BUG(); | |
817 | ||
818 | switch (type_from_irq(irq)) { | |
819 | case IRQT_VIRQ: | |
820 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 821 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 822 | break; |
d68d82af AN |
823 | case IRQT_IPI: |
824 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 825 | [ipi_from_irq(irq)] = -1; |
d68d82af | 826 | break; |
e46cdb66 JF |
827 | default: |
828 | break; | |
829 | } | |
830 | ||
831 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
832 | bind_evtchn_to_cpu(evtchn, 0); | |
833 | ||
834 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
835 | } |
836 | ||
837 | if (irq_info[irq].type != IRQT_UNBOUND) { | |
ced40d0f | 838 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 839 | |
77dff1c7 | 840 | irq_free_desc(irq); |
e46cdb66 JF |
841 | } |
842 | ||
843 | spin_unlock(&irq_mapping_update_lock); | |
844 | } | |
845 | ||
846 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 847 | irq_handler_t handler, |
e46cdb66 JF |
848 | unsigned long irqflags, |
849 | const char *devname, void *dev_id) | |
850 | { | |
851 | unsigned int irq; | |
852 | int retval; | |
853 | ||
854 | irq = bind_evtchn_to_irq(evtchn); | |
855 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
856 | if (retval != 0) { | |
857 | unbind_from_irq(irq); | |
858 | return retval; | |
859 | } | |
860 | ||
861 | return irq; | |
862 | } | |
863 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
864 | ||
865 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 866 | irq_handler_t handler, |
e46cdb66 JF |
867 | unsigned long irqflags, const char *devname, void *dev_id) |
868 | { | |
869 | unsigned int irq; | |
870 | int retval; | |
871 | ||
872 | irq = bind_virq_to_irq(virq, cpu); | |
873 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
874 | if (retval != 0) { | |
875 | unbind_from_irq(irq); | |
876 | return retval; | |
877 | } | |
878 | ||
879 | return irq; | |
880 | } | |
881 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
882 | ||
f87e4cac JF |
883 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
884 | unsigned int cpu, | |
885 | irq_handler_t handler, | |
886 | unsigned long irqflags, | |
887 | const char *devname, | |
888 | void *dev_id) | |
889 | { | |
890 | int irq, retval; | |
891 | ||
892 | irq = bind_ipi_to_irq(ipi, cpu); | |
893 | if (irq < 0) | |
894 | return irq; | |
895 | ||
4877c737 | 896 | irqflags |= IRQF_NO_SUSPEND; |
f87e4cac JF |
897 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
898 | if (retval != 0) { | |
899 | unbind_from_irq(irq); | |
900 | return retval; | |
901 | } | |
902 | ||
903 | return irq; | |
904 | } | |
905 | ||
e46cdb66 JF |
906 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
907 | { | |
908 | free_irq(irq, dev_id); | |
909 | unbind_from_irq(irq); | |
910 | } | |
911 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
912 | ||
f87e4cac JF |
913 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
914 | { | |
915 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
916 | BUG_ON(irq < 0); | |
917 | notify_remote_via_irq(irq); | |
918 | } | |
919 | ||
ee523ca1 JF |
920 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
921 | { | |
922 | struct shared_info *sh = HYPERVISOR_shared_info; | |
923 | int cpu = smp_processor_id(); | |
924 | int i; | |
925 | unsigned long flags; | |
926 | static DEFINE_SPINLOCK(debug_lock); | |
927 | ||
928 | spin_lock_irqsave(&debug_lock, flags); | |
929 | ||
930 | printk("vcpu %d\n ", cpu); | |
931 | ||
932 | for_each_online_cpu(i) { | |
933 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
934 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 935 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
936 | v->evtchn_upcall_pending, |
937 | v->evtchn_pending_sel); | |
938 | } | |
939 | printk("pending:\n "); | |
940 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
941 | printk("%08lx%s", sh->evtchn_pending[i], | |
942 | i % 8 == 0 ? "\n " : " "); | |
943 | printk("\nmasks:\n "); | |
944 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
945 | printk("%08lx%s", sh->evtchn_mask[i], | |
946 | i % 8 == 0 ? "\n " : " "); | |
947 | ||
948 | printk("\nunmasked:\n "); | |
949 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
950 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
951 | i % 8 == 0 ? "\n " : " "); | |
952 | ||
953 | printk("\npending list:\n"); | |
954 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
955 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
956 | printk(" %d: event %d -> irq %d\n", | |
ced40d0f JF |
957 | cpu_from_evtchn(i), i, |
958 | evtchn_to_irq[i]); | |
ee523ca1 JF |
959 | } |
960 | } | |
961 | ||
962 | spin_unlock_irqrestore(&debug_lock, flags); | |
963 | ||
964 | return IRQ_HANDLED; | |
965 | } | |
966 | ||
245b2e70 TH |
967 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
968 | ||
e46cdb66 JF |
969 | /* |
970 | * Search the CPUs pending events bitmasks. For each one found, map | |
971 | * the event number to an irq, and feed it into do_IRQ() for | |
972 | * handling. | |
973 | * | |
974 | * Xen uses a two-level bitmap to speed searching. The first level is | |
975 | * a bitset of words which contain pending event bits. The second | |
976 | * level is a bitset of pending events themselves. | |
977 | */ | |
38e20b07 | 978 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
979 | { |
980 | int cpu = get_cpu(); | |
981 | struct shared_info *s = HYPERVISOR_shared_info; | |
982 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be | 983 | unsigned count; |
e46cdb66 | 984 | |
229664be JF |
985 | do { |
986 | unsigned long pending_words; | |
e46cdb66 | 987 | |
229664be | 988 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 989 | |
245b2e70 | 990 | if (__get_cpu_var(xed_nesting_count)++) |
229664be | 991 | goto out; |
e46cdb66 | 992 | |
e849c3e9 IY |
993 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
994 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 995 | wmb(); |
e849c3e9 | 996 | #endif |
229664be JF |
997 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
998 | while (pending_words != 0) { | |
999 | unsigned long pending_bits; | |
1000 | int word_idx = __ffs(pending_words); | |
1001 | pending_words &= ~(1UL << word_idx); | |
1002 | ||
1003 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
1004 | int bit_idx = __ffs(pending_bits); | |
1005 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
1006 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 1007 | struct irq_desc *desc; |
229664be | 1008 | |
ca4dbc66 EB |
1009 | if (irq != -1) { |
1010 | desc = irq_to_desc(irq); | |
1011 | if (desc) | |
1012 | generic_handle_irq_desc(irq, desc); | |
1013 | } | |
e46cdb66 JF |
1014 | } |
1015 | } | |
e46cdb66 | 1016 | |
229664be JF |
1017 | BUG_ON(!irqs_disabled()); |
1018 | ||
245b2e70 TH |
1019 | count = __get_cpu_var(xed_nesting_count); |
1020 | __get_cpu_var(xed_nesting_count) = 0; | |
183d03cc | 1021 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1022 | |
1023 | out: | |
38e20b07 SY |
1024 | |
1025 | put_cpu(); | |
1026 | } | |
1027 | ||
1028 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1029 | { | |
1030 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1031 | ||
1032 | exit_idle(); | |
1033 | irq_enter(); | |
1034 | ||
1035 | __xen_evtchn_do_upcall(); | |
1036 | ||
3445a8fd JF |
1037 | irq_exit(); |
1038 | set_irq_regs(old_regs); | |
38e20b07 | 1039 | } |
3445a8fd | 1040 | |
38e20b07 SY |
1041 | void xen_hvm_evtchn_do_upcall(void) |
1042 | { | |
1043 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1044 | } |
183d03cc | 1045 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1046 | |
eb1e305f JF |
1047 | /* Rebind a new event channel to an existing irq. */ |
1048 | void rebind_evtchn_irq(int evtchn, int irq) | |
1049 | { | |
d77bbd4d JF |
1050 | struct irq_info *info = info_for_irq(irq); |
1051 | ||
eb1e305f JF |
1052 | /* Make sure the irq is masked, since the new event channel |
1053 | will also be masked. */ | |
1054 | disable_irq(irq); | |
1055 | ||
1056 | spin_lock(&irq_mapping_update_lock); | |
1057 | ||
1058 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1059 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1060 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1061 | so there should be a proper type */ |
1062 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
1063 | |
1064 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1065 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
1066 | |
1067 | spin_unlock(&irq_mapping_update_lock); | |
1068 | ||
1069 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1070 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1071 | |
1072 | /* Unmask the event channel. */ | |
1073 | enable_irq(irq); | |
1074 | } | |
1075 | ||
e46cdb66 | 1076 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1077 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1078 | { |
1079 | struct evtchn_bind_vcpu bind_vcpu; | |
1080 | int evtchn = evtchn_from_irq(irq); | |
1081 | ||
183d03cc SS |
1082 | /* events delivered via platform PCI interrupts are always |
1083 | * routed to vcpu 0 */ | |
1084 | if (!VALID_EVTCHN(evtchn) || | |
1085 | (xen_hvm_domain() && !xen_have_vector_callback)) | |
d5dedd45 | 1086 | return -1; |
e46cdb66 JF |
1087 | |
1088 | /* Send future instances of this interrupt to other vcpu. */ | |
1089 | bind_vcpu.port = evtchn; | |
1090 | bind_vcpu.vcpu = tcpu; | |
1091 | ||
1092 | /* | |
1093 | * If this fails, it usually just indicates that we're dealing with a | |
1094 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1095 | * it, but don't do the xenlinux-level rebind in that case. | |
1096 | */ | |
1097 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1098 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1099 | |
d5dedd45 YL |
1100 | return 0; |
1101 | } | |
e46cdb66 | 1102 | |
d5dedd45 | 1103 | static int set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 1104 | { |
0de26520 | 1105 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 YL |
1106 | |
1107 | return rebind_irq_to_cpu(irq, tcpu); | |
e46cdb66 JF |
1108 | } |
1109 | ||
642e0c88 IY |
1110 | int resend_irq_on_evtchn(unsigned int irq) |
1111 | { | |
1112 | int masked, evtchn = evtchn_from_irq(irq); | |
1113 | struct shared_info *s = HYPERVISOR_shared_info; | |
1114 | ||
1115 | if (!VALID_EVTCHN(evtchn)) | |
1116 | return 1; | |
1117 | ||
1118 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1119 | sync_set_bit(evtchn, s->evtchn_pending); | |
1120 | if (!masked) | |
1121 | unmask_evtchn(evtchn); | |
1122 | ||
1123 | return 1; | |
1124 | } | |
1125 | ||
e46cdb66 JF |
1126 | static void enable_dynirq(unsigned int irq) |
1127 | { | |
1128 | int evtchn = evtchn_from_irq(irq); | |
1129 | ||
1130 | if (VALID_EVTCHN(evtchn)) | |
1131 | unmask_evtchn(evtchn); | |
1132 | } | |
1133 | ||
1134 | static void disable_dynirq(unsigned int irq) | |
1135 | { | |
1136 | int evtchn = evtchn_from_irq(irq); | |
1137 | ||
1138 | if (VALID_EVTCHN(evtchn)) | |
1139 | mask_evtchn(evtchn); | |
1140 | } | |
1141 | ||
1142 | static void ack_dynirq(unsigned int irq) | |
1143 | { | |
1144 | int evtchn = evtchn_from_irq(irq); | |
1145 | ||
1146 | move_native_irq(irq); | |
1147 | ||
1148 | if (VALID_EVTCHN(evtchn)) | |
1149 | clear_evtchn(evtchn); | |
1150 | } | |
1151 | ||
1152 | static int retrigger_dynirq(unsigned int irq) | |
1153 | { | |
1154 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 1155 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1156 | int ret = 0; |
1157 | ||
1158 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1159 | int masked; |
1160 | ||
1161 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1162 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1163 | if (!masked) | |
1164 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1165 | ret = 1; |
1166 | } | |
1167 | ||
1168 | return ret; | |
1169 | } | |
1170 | ||
0e91398f JF |
1171 | static void restore_cpu_virqs(unsigned int cpu) |
1172 | { | |
1173 | struct evtchn_bind_virq bind_virq; | |
1174 | int virq, irq, evtchn; | |
1175 | ||
1176 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1177 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1178 | continue; | |
1179 | ||
ced40d0f | 1180 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1181 | |
1182 | /* Get a new binding from Xen. */ | |
1183 | bind_virq.virq = virq; | |
1184 | bind_virq.vcpu = cpu; | |
1185 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1186 | &bind_virq) != 0) | |
1187 | BUG(); | |
1188 | evtchn = bind_virq.port; | |
1189 | ||
1190 | /* Record the new mapping. */ | |
1191 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1192 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f JF |
1193 | bind_evtchn_to_cpu(evtchn, cpu); |
1194 | ||
1195 | /* Ready for use. */ | |
1196 | unmask_evtchn(evtchn); | |
1197 | } | |
1198 | } | |
1199 | ||
1200 | static void restore_cpu_ipis(unsigned int cpu) | |
1201 | { | |
1202 | struct evtchn_bind_ipi bind_ipi; | |
1203 | int ipi, irq, evtchn; | |
1204 | ||
1205 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1206 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1207 | continue; | |
1208 | ||
ced40d0f | 1209 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1210 | |
1211 | /* Get a new binding from Xen. */ | |
1212 | bind_ipi.vcpu = cpu; | |
1213 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1214 | &bind_ipi) != 0) | |
1215 | BUG(); | |
1216 | evtchn = bind_ipi.port; | |
1217 | ||
1218 | /* Record the new mapping. */ | |
1219 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1220 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f JF |
1221 | bind_evtchn_to_cpu(evtchn, cpu); |
1222 | ||
1223 | /* Ready for use. */ | |
1224 | unmask_evtchn(evtchn); | |
1225 | ||
1226 | } | |
1227 | } | |
1228 | ||
2d9e1e2f JF |
1229 | /* Clear an irq's pending state, in preparation for polling on it */ |
1230 | void xen_clear_irq_pending(int irq) | |
1231 | { | |
1232 | int evtchn = evtchn_from_irq(irq); | |
1233 | ||
1234 | if (VALID_EVTCHN(evtchn)) | |
1235 | clear_evtchn(evtchn); | |
1236 | } | |
d9a8814f | 1237 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1238 | void xen_set_irq_pending(int irq) |
1239 | { | |
1240 | int evtchn = evtchn_from_irq(irq); | |
1241 | ||
1242 | if (VALID_EVTCHN(evtchn)) | |
1243 | set_evtchn(evtchn); | |
1244 | } | |
1245 | ||
1246 | bool xen_test_irq_pending(int irq) | |
1247 | { | |
1248 | int evtchn = evtchn_from_irq(irq); | |
1249 | bool ret = false; | |
1250 | ||
1251 | if (VALID_EVTCHN(evtchn)) | |
1252 | ret = test_evtchn(evtchn); | |
1253 | ||
1254 | return ret; | |
1255 | } | |
1256 | ||
d9a8814f KRW |
1257 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1258 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1259 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1260 | { |
1261 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1262 | ||
1263 | if (VALID_EVTCHN(evtchn)) { | |
1264 | struct sched_poll poll; | |
1265 | ||
1266 | poll.nr_ports = 1; | |
d9a8814f | 1267 | poll.timeout = timeout; |
ff3c5362 | 1268 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1269 | |
1270 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1271 | BUG(); | |
1272 | } | |
1273 | } | |
d9a8814f KRW |
1274 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1275 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1276 | * irq will be disabled so it won't deliver an interrupt. */ | |
1277 | void xen_poll_irq(int irq) | |
1278 | { | |
1279 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1280 | } | |
2d9e1e2f | 1281 | |
0e91398f JF |
1282 | void xen_irq_resume(void) |
1283 | { | |
1284 | unsigned int cpu, irq, evtchn; | |
1285 | ||
1286 | init_evtchn_cpu_bindings(); | |
1287 | ||
1288 | /* New event-channel space is not 'live' yet. */ | |
1289 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1290 | mask_evtchn(evtchn); | |
1291 | ||
1292 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 1293 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
1294 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
1295 | ||
1296 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1297 | evtchn_to_irq[evtchn] = -1; | |
1298 | ||
1299 | for_each_possible_cpu(cpu) { | |
1300 | restore_cpu_virqs(cpu); | |
1301 | restore_cpu_ipis(cpu); | |
1302 | } | |
1303 | } | |
1304 | ||
e46cdb66 JF |
1305 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
1306 | .name = "xen-dyn", | |
54a353a0 JF |
1307 | |
1308 | .disable = disable_dynirq, | |
e46cdb66 JF |
1309 | .mask = disable_dynirq, |
1310 | .unmask = enable_dynirq, | |
54a353a0 | 1311 | |
e46cdb66 JF |
1312 | .ack = ack_dynirq, |
1313 | .set_affinity = set_affinity_irq, | |
1314 | .retrigger = retrigger_dynirq, | |
1315 | }; | |
1316 | ||
d46a78b0 JF |
1317 | static struct irq_chip xen_pirq_chip __read_mostly = { |
1318 | .name = "xen-pirq", | |
1319 | ||
1320 | .startup = startup_pirq, | |
1321 | .shutdown = shutdown_pirq, | |
1322 | ||
1323 | .enable = enable_pirq, | |
1324 | .unmask = enable_pirq, | |
1325 | ||
1326 | .disable = disable_pirq, | |
1327 | .mask = disable_pirq, | |
1328 | ||
1329 | .ack = ack_pirq, | |
1330 | .end = end_pirq, | |
1331 | ||
1332 | .set_affinity = set_affinity_irq, | |
1333 | ||
1334 | .retrigger = retrigger_dynirq, | |
1335 | }; | |
1336 | ||
aaca4964 JF |
1337 | static struct irq_chip xen_percpu_chip __read_mostly = { |
1338 | .name = "xen-percpu", | |
1339 | ||
1340 | .disable = disable_dynirq, | |
1341 | .mask = disable_dynirq, | |
1342 | .unmask = enable_dynirq, | |
1343 | ||
1344 | .ack = ack_dynirq, | |
1345 | }; | |
1346 | ||
38e20b07 SY |
1347 | int xen_set_callback_via(uint64_t via) |
1348 | { | |
1349 | struct xen_hvm_param a; | |
1350 | a.domid = DOMID_SELF; | |
1351 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1352 | a.value = via; | |
1353 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1354 | } | |
1355 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1356 | ||
ca65f9fc | 1357 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1358 | /* Vector callbacks are better than PCI interrupts to receive event |
1359 | * channel notifications because we can receive vector callbacks on any | |
1360 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1361 | void xen_callback_vector(void) | |
1362 | { | |
1363 | int rc; | |
1364 | uint64_t callback_via; | |
1365 | if (xen_have_vector_callback) { | |
1366 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1367 | rc = xen_set_callback_via(callback_via); | |
1368 | if (rc) { | |
1369 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1370 | " failed.\n"); | |
1371 | xen_have_vector_callback = 0; | |
1372 | return; | |
1373 | } | |
1374 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1375 | "enabled\n"); | |
1376 | /* in the restore case the vector has already been allocated */ | |
1377 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1378 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1379 | } | |
1380 | } | |
ca65f9fc SS |
1381 | #else |
1382 | void xen_callback_vector(void) {} | |
1383 | #endif | |
38e20b07 | 1384 | |
e46cdb66 JF |
1385 | void __init xen_init_IRQ(void) |
1386 | { | |
01557baf SS |
1387 | int i, rc; |
1388 | struct physdev_nr_pirqs op_nr_pirqs; | |
c7a3589e | 1389 | |
a70c352a PE |
1390 | cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s), |
1391 | GFP_KERNEL); | |
b21ddbf5 JF |
1392 | irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL); |
1393 | ||
01557baf SS |
1394 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_nr_pirqs, &op_nr_pirqs); |
1395 | if (rc < 0) { | |
1396 | nr_pirqs = nr_irqs; | |
1397 | if (rc != -ENOSYS) | |
1398 | printk(KERN_WARNING "PHYSDEVOP_get_nr_pirqs returned rc=%d\n", rc); | |
1399 | } else { | |
1400 | if (xen_pv_domain() && !xen_initial_domain()) | |
1401 | nr_pirqs = max((int)op_nr_pirqs.nr_pirqs, nr_irqs); | |
1402 | else | |
1403 | nr_pirqs = op_nr_pirqs.nr_pirqs; | |
1404 | } | |
1405 | pirq_to_irq = kcalloc(nr_pirqs, sizeof(*pirq_to_irq), GFP_KERNEL); | |
1406 | for (i = 0; i < nr_pirqs; i++) | |
7a043f11 SS |
1407 | pirq_to_irq[i] = -1; |
1408 | ||
b21ddbf5 JF |
1409 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1410 | GFP_KERNEL); | |
1411 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1412 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1413 | |
1414 | init_evtchn_cpu_bindings(); | |
1415 | ||
1416 | /* No event channels are 'live' right now. */ | |
1417 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1418 | mask_evtchn(i); | |
1419 | ||
38e20b07 SY |
1420 | if (xen_hvm_domain()) { |
1421 | xen_callback_vector(); | |
1422 | native_init_IRQ(); | |
3942b740 SS |
1423 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1424 | * __acpi_register_gsi can point at the right function */ | |
1425 | pci_xen_hvm_init(); | |
38e20b07 SY |
1426 | } else { |
1427 | irq_ctx_init(smp_processor_id()); | |
1428 | } | |
e46cdb66 | 1429 | } |