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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
19 | * 4. Hardware interrupts. Not supported at present. | |
20 | * | |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
29 | ||
30 | #include <asm/ptrace.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/sync_bitops.h> | |
33 | #include <asm/xen/hypercall.h> | |
8d1b8753 | 34 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 35 | |
e04d0d07 | 36 | #include <xen/xen-ops.h> |
e46cdb66 JF |
37 | #include <xen/events.h> |
38 | #include <xen/interface/xen.h> | |
39 | #include <xen/interface/event_channel.h> | |
40 | ||
e46cdb66 JF |
41 | /* |
42 | * This lock protects updates to the following mapping and reference-count | |
43 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
44 | */ | |
45 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
46 | ||
47 | /* IRQ <-> VIRQ mapping. */ | |
48 | static DEFINE_PER_CPU(int, virq_to_irq[NR_VIRQS]) = {[0 ... NR_VIRQS-1] = -1}; | |
49 | ||
f87e4cac JF |
50 | /* IRQ <-> IPI mapping */ |
51 | static DEFINE_PER_CPU(int, ipi_to_irq[XEN_NR_IPIS]) = {[0 ... XEN_NR_IPIS-1] = -1}; | |
52 | ||
e46cdb66 JF |
53 | /* Packed IRQ information: binding type, sub-type index, and event channel. */ |
54 | struct packed_irq | |
55 | { | |
56 | unsigned short evtchn; | |
57 | unsigned char index; | |
58 | unsigned char type; | |
59 | }; | |
60 | ||
61 | static struct packed_irq irq_info[NR_IRQS]; | |
62 | ||
63 | /* Binding types. */ | |
f87e4cac JF |
64 | enum { |
65 | IRQT_UNBOUND, | |
66 | IRQT_PIRQ, | |
67 | IRQT_VIRQ, | |
68 | IRQT_IPI, | |
69 | IRQT_EVTCHN | |
70 | }; | |
e46cdb66 JF |
71 | |
72 | /* Convenient shorthand for packed representation of an unbound IRQ. */ | |
73 | #define IRQ_UNBOUND mk_irq_info(IRQT_UNBOUND, 0, 0) | |
74 | ||
75 | static int evtchn_to_irq[NR_EVENT_CHANNELS] = { | |
76 | [0 ... NR_EVENT_CHANNELS-1] = -1 | |
77 | }; | |
78 | static unsigned long cpu_evtchn_mask[NR_CPUS][NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
79 | static u8 cpu_evtchn[NR_EVENT_CHANNELS]; | |
80 | ||
81 | /* Reference counts for bindings to IRQs. */ | |
82 | static int irq_bindcount[NR_IRQS]; | |
83 | ||
84 | /* Xen will never allocate port zero for any purpose. */ | |
85 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
86 | ||
e46cdb66 JF |
87 | static struct irq_chip xen_dynamic_chip; |
88 | ||
89 | /* Constructor for packed IRQ information. */ | |
90 | static inline struct packed_irq mk_irq_info(u32 type, u32 index, u32 evtchn) | |
91 | { | |
92 | return (struct packed_irq) { evtchn, index, type }; | |
93 | } | |
94 | ||
95 | /* | |
96 | * Accessors for packed IRQ information. | |
97 | */ | |
98 | static inline unsigned int evtchn_from_irq(int irq) | |
99 | { | |
100 | return irq_info[irq].evtchn; | |
101 | } | |
102 | ||
103 | static inline unsigned int index_from_irq(int irq) | |
104 | { | |
105 | return irq_info[irq].index; | |
106 | } | |
107 | ||
108 | static inline unsigned int type_from_irq(int irq) | |
109 | { | |
110 | return irq_info[irq].type; | |
111 | } | |
112 | ||
113 | static inline unsigned long active_evtchns(unsigned int cpu, | |
114 | struct shared_info *sh, | |
115 | unsigned int idx) | |
116 | { | |
117 | return (sh->evtchn_pending[idx] & | |
118 | cpu_evtchn_mask[cpu][idx] & | |
119 | ~sh->evtchn_mask[idx]); | |
120 | } | |
121 | ||
122 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
123 | { | |
124 | int irq = evtchn_to_irq[chn]; | |
125 | ||
126 | BUG_ON(irq == -1); | |
127 | #ifdef CONFIG_SMP | |
128 | irq_desc[irq].affinity = cpumask_of_cpu(cpu); | |
129 | #endif | |
130 | ||
131 | __clear_bit(chn, cpu_evtchn_mask[cpu_evtchn[chn]]); | |
132 | __set_bit(chn, cpu_evtchn_mask[cpu]); | |
133 | ||
134 | cpu_evtchn[chn] = cpu; | |
135 | } | |
136 | ||
137 | static void init_evtchn_cpu_bindings(void) | |
138 | { | |
139 | #ifdef CONFIG_SMP | |
140 | int i; | |
141 | /* By default all event channels notify CPU#0. */ | |
142 | for (i = 0; i < NR_IRQS; i++) | |
143 | irq_desc[i].affinity = cpumask_of_cpu(0); | |
144 | #endif | |
145 | ||
146 | memset(cpu_evtchn, 0, sizeof(cpu_evtchn)); | |
147 | memset(cpu_evtchn_mask[0], ~0, sizeof(cpu_evtchn_mask[0])); | |
148 | } | |
149 | ||
150 | static inline unsigned int cpu_from_evtchn(unsigned int evtchn) | |
151 | { | |
152 | return cpu_evtchn[evtchn]; | |
153 | } | |
154 | ||
155 | static inline void clear_evtchn(int port) | |
156 | { | |
157 | struct shared_info *s = HYPERVISOR_shared_info; | |
158 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
159 | } | |
160 | ||
161 | static inline void set_evtchn(int port) | |
162 | { | |
163 | struct shared_info *s = HYPERVISOR_shared_info; | |
164 | sync_set_bit(port, &s->evtchn_pending[0]); | |
165 | } | |
166 | ||
167 | ||
168 | /** | |
169 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
170 | * @irq: irq of event channel to send event to | |
171 | * | |
172 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
173 | * save/restore. Notifications on a broken connection are silently | |
174 | * dropped. | |
175 | */ | |
176 | void notify_remote_via_irq(int irq) | |
177 | { | |
178 | int evtchn = evtchn_from_irq(irq); | |
179 | ||
180 | if (VALID_EVTCHN(evtchn)) | |
181 | notify_remote_via_evtchn(evtchn); | |
182 | } | |
183 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
184 | ||
185 | static void mask_evtchn(int port) | |
186 | { | |
187 | struct shared_info *s = HYPERVISOR_shared_info; | |
188 | sync_set_bit(port, &s->evtchn_mask[0]); | |
189 | } | |
190 | ||
191 | static void unmask_evtchn(int port) | |
192 | { | |
193 | struct shared_info *s = HYPERVISOR_shared_info; | |
194 | unsigned int cpu = get_cpu(); | |
195 | ||
196 | BUG_ON(!irqs_disabled()); | |
197 | ||
198 | /* Slow path (hypercall) if this is a non-local port. */ | |
199 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
200 | struct evtchn_unmask unmask = { .port = port }; | |
201 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
202 | } else { | |
203 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
204 | ||
205 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
206 | ||
207 | /* | |
208 | * The following is basically the equivalent of | |
209 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
210 | * the interrupt edge' if the channel is masked. | |
211 | */ | |
212 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
213 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
214 | &vcpu_info->evtchn_pending_sel)) | |
215 | vcpu_info->evtchn_upcall_pending = 1; | |
216 | } | |
217 | ||
218 | put_cpu(); | |
219 | } | |
220 | ||
221 | static int find_unbound_irq(void) | |
222 | { | |
223 | int irq; | |
224 | ||
225 | /* Only allocate from dynirq range */ | |
226 | for (irq = 0; irq < NR_IRQS; irq++) | |
227 | if (irq_bindcount[irq] == 0) | |
228 | break; | |
229 | ||
230 | if (irq == NR_IRQS) | |
231 | panic("No available IRQ to bind to: increase NR_IRQS!\n"); | |
232 | ||
233 | return irq; | |
234 | } | |
235 | ||
b536b4b9 | 236 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
237 | { |
238 | int irq; | |
239 | ||
240 | spin_lock(&irq_mapping_update_lock); | |
241 | ||
242 | irq = evtchn_to_irq[evtchn]; | |
243 | ||
244 | if (irq == -1) { | |
245 | irq = find_unbound_irq(); | |
246 | ||
247 | dynamic_irq_init(irq); | |
248 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, | |
249 | handle_level_irq, "event"); | |
250 | ||
251 | evtchn_to_irq[evtchn] = irq; | |
252 | irq_info[irq] = mk_irq_info(IRQT_EVTCHN, 0, evtchn); | |
253 | } | |
254 | ||
255 | irq_bindcount[irq]++; | |
256 | ||
257 | spin_unlock(&irq_mapping_update_lock); | |
258 | ||
259 | return irq; | |
260 | } | |
b536b4b9 | 261 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 262 | |
f87e4cac JF |
263 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
264 | { | |
265 | struct evtchn_bind_ipi bind_ipi; | |
266 | int evtchn, irq; | |
267 | ||
268 | spin_lock(&irq_mapping_update_lock); | |
269 | ||
270 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
271 | if (irq == -1) { | |
272 | irq = find_unbound_irq(); | |
273 | if (irq < 0) | |
274 | goto out; | |
275 | ||
276 | dynamic_irq_init(irq); | |
277 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, | |
278 | handle_level_irq, "ipi"); | |
279 | ||
280 | bind_ipi.vcpu = cpu; | |
281 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
282 | &bind_ipi) != 0) | |
283 | BUG(); | |
284 | evtchn = bind_ipi.port; | |
285 | ||
286 | evtchn_to_irq[evtchn] = irq; | |
287 | irq_info[irq] = mk_irq_info(IRQT_IPI, ipi, evtchn); | |
288 | ||
289 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
290 | ||
291 | bind_evtchn_to_cpu(evtchn, cpu); | |
292 | } | |
293 | ||
294 | irq_bindcount[irq]++; | |
295 | ||
296 | out: | |
297 | spin_unlock(&irq_mapping_update_lock); | |
298 | return irq; | |
299 | } | |
300 | ||
301 | ||
e46cdb66 JF |
302 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
303 | { | |
304 | struct evtchn_bind_virq bind_virq; | |
305 | int evtchn, irq; | |
306 | ||
307 | spin_lock(&irq_mapping_update_lock); | |
308 | ||
309 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
310 | ||
311 | if (irq == -1) { | |
312 | bind_virq.virq = virq; | |
313 | bind_virq.vcpu = cpu; | |
314 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
315 | &bind_virq) != 0) | |
316 | BUG(); | |
317 | evtchn = bind_virq.port; | |
318 | ||
319 | irq = find_unbound_irq(); | |
320 | ||
321 | dynamic_irq_init(irq); | |
322 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, | |
323 | handle_level_irq, "virq"); | |
324 | ||
325 | evtchn_to_irq[evtchn] = irq; | |
326 | irq_info[irq] = mk_irq_info(IRQT_VIRQ, virq, evtchn); | |
327 | ||
328 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
329 | ||
330 | bind_evtchn_to_cpu(evtchn, cpu); | |
331 | } | |
332 | ||
333 | irq_bindcount[irq]++; | |
334 | ||
335 | spin_unlock(&irq_mapping_update_lock); | |
336 | ||
337 | return irq; | |
338 | } | |
339 | ||
340 | static void unbind_from_irq(unsigned int irq) | |
341 | { | |
342 | struct evtchn_close close; | |
343 | int evtchn = evtchn_from_irq(irq); | |
344 | ||
345 | spin_lock(&irq_mapping_update_lock); | |
346 | ||
0f2287ad | 347 | if ((--irq_bindcount[irq] == 0) && VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
348 | close.port = evtchn; |
349 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
350 | BUG(); | |
351 | ||
352 | switch (type_from_irq(irq)) { | |
353 | case IRQT_VIRQ: | |
354 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
355 | [index_from_irq(irq)] = -1; | |
356 | break; | |
357 | default: | |
358 | break; | |
359 | } | |
360 | ||
361 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
362 | bind_evtchn_to_cpu(evtchn, 0); | |
363 | ||
364 | evtchn_to_irq[evtchn] = -1; | |
365 | irq_info[irq] = IRQ_UNBOUND; | |
366 | ||
0f2287ad | 367 | dynamic_irq_cleanup(irq); |
e46cdb66 JF |
368 | } |
369 | ||
370 | spin_unlock(&irq_mapping_update_lock); | |
371 | } | |
372 | ||
373 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 374 | irq_handler_t handler, |
e46cdb66 JF |
375 | unsigned long irqflags, |
376 | const char *devname, void *dev_id) | |
377 | { | |
378 | unsigned int irq; | |
379 | int retval; | |
380 | ||
381 | irq = bind_evtchn_to_irq(evtchn); | |
382 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
383 | if (retval != 0) { | |
384 | unbind_from_irq(irq); | |
385 | return retval; | |
386 | } | |
387 | ||
388 | return irq; | |
389 | } | |
390 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
391 | ||
392 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 393 | irq_handler_t handler, |
e46cdb66 JF |
394 | unsigned long irqflags, const char *devname, void *dev_id) |
395 | { | |
396 | unsigned int irq; | |
397 | int retval; | |
398 | ||
399 | irq = bind_virq_to_irq(virq, cpu); | |
400 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
401 | if (retval != 0) { | |
402 | unbind_from_irq(irq); | |
403 | return retval; | |
404 | } | |
405 | ||
406 | return irq; | |
407 | } | |
408 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
409 | ||
f87e4cac JF |
410 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
411 | unsigned int cpu, | |
412 | irq_handler_t handler, | |
413 | unsigned long irqflags, | |
414 | const char *devname, | |
415 | void *dev_id) | |
416 | { | |
417 | int irq, retval; | |
418 | ||
419 | irq = bind_ipi_to_irq(ipi, cpu); | |
420 | if (irq < 0) | |
421 | return irq; | |
422 | ||
423 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
424 | if (retval != 0) { | |
425 | unbind_from_irq(irq); | |
426 | return retval; | |
427 | } | |
428 | ||
429 | return irq; | |
430 | } | |
431 | ||
e46cdb66 JF |
432 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
433 | { | |
434 | free_irq(irq, dev_id); | |
435 | unbind_from_irq(irq); | |
436 | } | |
437 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
438 | ||
f87e4cac JF |
439 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
440 | { | |
441 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
442 | BUG_ON(irq < 0); | |
443 | notify_remote_via_irq(irq); | |
444 | } | |
445 | ||
ee523ca1 JF |
446 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
447 | { | |
448 | struct shared_info *sh = HYPERVISOR_shared_info; | |
449 | int cpu = smp_processor_id(); | |
450 | int i; | |
451 | unsigned long flags; | |
452 | static DEFINE_SPINLOCK(debug_lock); | |
453 | ||
454 | spin_lock_irqsave(&debug_lock, flags); | |
455 | ||
456 | printk("vcpu %d\n ", cpu); | |
457 | ||
458 | for_each_online_cpu(i) { | |
459 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
460 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 461 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
462 | v->evtchn_upcall_pending, |
463 | v->evtchn_pending_sel); | |
464 | } | |
465 | printk("pending:\n "); | |
466 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
467 | printk("%08lx%s", sh->evtchn_pending[i], | |
468 | i % 8 == 0 ? "\n " : " "); | |
469 | printk("\nmasks:\n "); | |
470 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
471 | printk("%08lx%s", sh->evtchn_mask[i], | |
472 | i % 8 == 0 ? "\n " : " "); | |
473 | ||
474 | printk("\nunmasked:\n "); | |
475 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
476 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
477 | i % 8 == 0 ? "\n " : " "); | |
478 | ||
479 | printk("\npending list:\n"); | |
480 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
481 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
482 | printk(" %d: event %d -> irq %d\n", | |
483 | cpu_evtchn[i], i, | |
484 | evtchn_to_irq[i]); | |
485 | } | |
486 | } | |
487 | ||
488 | spin_unlock_irqrestore(&debug_lock, flags); | |
489 | ||
490 | return IRQ_HANDLED; | |
491 | } | |
492 | ||
f87e4cac | 493 | |
e46cdb66 JF |
494 | /* |
495 | * Search the CPUs pending events bitmasks. For each one found, map | |
496 | * the event number to an irq, and feed it into do_IRQ() for | |
497 | * handling. | |
498 | * | |
499 | * Xen uses a two-level bitmap to speed searching. The first level is | |
500 | * a bitset of words which contain pending event bits. The second | |
501 | * level is a bitset of pending events themselves. | |
502 | */ | |
75604d7f | 503 | void xen_evtchn_do_upcall(struct pt_regs *regs) |
e46cdb66 JF |
504 | { |
505 | int cpu = get_cpu(); | |
506 | struct shared_info *s = HYPERVISOR_shared_info; | |
507 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be JF |
508 | static DEFINE_PER_CPU(unsigned, nesting_count); |
509 | unsigned count; | |
e46cdb66 | 510 | |
229664be JF |
511 | do { |
512 | unsigned long pending_words; | |
e46cdb66 | 513 | |
229664be | 514 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 515 | |
229664be JF |
516 | if (__get_cpu_var(nesting_count)++) |
517 | goto out; | |
e46cdb66 | 518 | |
e849c3e9 IY |
519 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
520 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 521 | wmb(); |
e849c3e9 | 522 | #endif |
229664be JF |
523 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
524 | while (pending_words != 0) { | |
525 | unsigned long pending_bits; | |
526 | int word_idx = __ffs(pending_words); | |
527 | pending_words &= ~(1UL << word_idx); | |
528 | ||
529 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
530 | int bit_idx = __ffs(pending_bits); | |
531 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
532 | int irq = evtchn_to_irq[port]; | |
533 | ||
e849c3e9 IY |
534 | if (irq != -1) |
535 | xen_do_IRQ(irq, regs); | |
e46cdb66 JF |
536 | } |
537 | } | |
e46cdb66 | 538 | |
229664be JF |
539 | BUG_ON(!irqs_disabled()); |
540 | ||
541 | count = __get_cpu_var(nesting_count); | |
542 | __get_cpu_var(nesting_count) = 0; | |
543 | } while(count != 1); | |
544 | ||
545 | out: | |
e46cdb66 JF |
546 | put_cpu(); |
547 | } | |
548 | ||
eb1e305f JF |
549 | /* Rebind a new event channel to an existing irq. */ |
550 | void rebind_evtchn_irq(int evtchn, int irq) | |
551 | { | |
552 | /* Make sure the irq is masked, since the new event channel | |
553 | will also be masked. */ | |
554 | disable_irq(irq); | |
555 | ||
556 | spin_lock(&irq_mapping_update_lock); | |
557 | ||
558 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
559 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
560 | /* Expect irq to have been bound before, | |
561 | so the bindcount should be non-0 */ | |
562 | BUG_ON(irq_bindcount[irq] == 0); | |
563 | ||
564 | evtchn_to_irq[evtchn] = irq; | |
565 | irq_info[irq] = mk_irq_info(IRQT_EVTCHN, 0, evtchn); | |
566 | ||
567 | spin_unlock(&irq_mapping_update_lock); | |
568 | ||
569 | /* new event channels are always bound to cpu 0 */ | |
570 | irq_set_affinity(irq, cpumask_of_cpu(0)); | |
571 | ||
572 | /* Unmask the event channel. */ | |
573 | enable_irq(irq); | |
574 | } | |
575 | ||
e46cdb66 JF |
576 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
577 | static void rebind_irq_to_cpu(unsigned irq, unsigned tcpu) | |
578 | { | |
579 | struct evtchn_bind_vcpu bind_vcpu; | |
580 | int evtchn = evtchn_from_irq(irq); | |
581 | ||
582 | if (!VALID_EVTCHN(evtchn)) | |
583 | return; | |
584 | ||
585 | /* Send future instances of this interrupt to other vcpu. */ | |
586 | bind_vcpu.port = evtchn; | |
587 | bind_vcpu.vcpu = tcpu; | |
588 | ||
589 | /* | |
590 | * If this fails, it usually just indicates that we're dealing with a | |
591 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
592 | * it, but don't do the xenlinux-level rebind in that case. | |
593 | */ | |
594 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
595 | bind_evtchn_to_cpu(evtchn, tcpu); | |
596 | } | |
597 | ||
598 | ||
599 | static void set_affinity_irq(unsigned irq, cpumask_t dest) | |
600 | { | |
601 | unsigned tcpu = first_cpu(dest); | |
602 | rebind_irq_to_cpu(irq, tcpu); | |
603 | } | |
604 | ||
642e0c88 IY |
605 | int resend_irq_on_evtchn(unsigned int irq) |
606 | { | |
607 | int masked, evtchn = evtchn_from_irq(irq); | |
608 | struct shared_info *s = HYPERVISOR_shared_info; | |
609 | ||
610 | if (!VALID_EVTCHN(evtchn)) | |
611 | return 1; | |
612 | ||
613 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
614 | sync_set_bit(evtchn, s->evtchn_pending); | |
615 | if (!masked) | |
616 | unmask_evtchn(evtchn); | |
617 | ||
618 | return 1; | |
619 | } | |
620 | ||
e46cdb66 JF |
621 | static void enable_dynirq(unsigned int irq) |
622 | { | |
623 | int evtchn = evtchn_from_irq(irq); | |
624 | ||
625 | if (VALID_EVTCHN(evtchn)) | |
626 | unmask_evtchn(evtchn); | |
627 | } | |
628 | ||
629 | static void disable_dynirq(unsigned int irq) | |
630 | { | |
631 | int evtchn = evtchn_from_irq(irq); | |
632 | ||
633 | if (VALID_EVTCHN(evtchn)) | |
634 | mask_evtchn(evtchn); | |
635 | } | |
636 | ||
637 | static void ack_dynirq(unsigned int irq) | |
638 | { | |
639 | int evtchn = evtchn_from_irq(irq); | |
640 | ||
641 | move_native_irq(irq); | |
642 | ||
643 | if (VALID_EVTCHN(evtchn)) | |
644 | clear_evtchn(evtchn); | |
645 | } | |
646 | ||
647 | static int retrigger_dynirq(unsigned int irq) | |
648 | { | |
649 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 650 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
651 | int ret = 0; |
652 | ||
653 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
654 | int masked; |
655 | ||
656 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
657 | sync_set_bit(evtchn, sh->evtchn_pending); | |
658 | if (!masked) | |
659 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
660 | ret = 1; |
661 | } | |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
0e91398f JF |
666 | static void restore_cpu_virqs(unsigned int cpu) |
667 | { | |
668 | struct evtchn_bind_virq bind_virq; | |
669 | int virq, irq, evtchn; | |
670 | ||
671 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
672 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
673 | continue; | |
674 | ||
675 | BUG_ON(irq_info[irq].type != IRQT_VIRQ); | |
676 | BUG_ON(irq_info[irq].index != virq); | |
677 | ||
678 | /* Get a new binding from Xen. */ | |
679 | bind_virq.virq = virq; | |
680 | bind_virq.vcpu = cpu; | |
681 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
682 | &bind_virq) != 0) | |
683 | BUG(); | |
684 | evtchn = bind_virq.port; | |
685 | ||
686 | /* Record the new mapping. */ | |
687 | evtchn_to_irq[evtchn] = irq; | |
688 | irq_info[irq] = mk_irq_info(IRQT_VIRQ, virq, evtchn); | |
689 | bind_evtchn_to_cpu(evtchn, cpu); | |
690 | ||
691 | /* Ready for use. */ | |
692 | unmask_evtchn(evtchn); | |
693 | } | |
694 | } | |
695 | ||
696 | static void restore_cpu_ipis(unsigned int cpu) | |
697 | { | |
698 | struct evtchn_bind_ipi bind_ipi; | |
699 | int ipi, irq, evtchn; | |
700 | ||
701 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
702 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
703 | continue; | |
704 | ||
705 | BUG_ON(irq_info[irq].type != IRQT_IPI); | |
706 | BUG_ON(irq_info[irq].index != ipi); | |
707 | ||
708 | /* Get a new binding from Xen. */ | |
709 | bind_ipi.vcpu = cpu; | |
710 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
711 | &bind_ipi) != 0) | |
712 | BUG(); | |
713 | evtchn = bind_ipi.port; | |
714 | ||
715 | /* Record the new mapping. */ | |
716 | evtchn_to_irq[evtchn] = irq; | |
717 | irq_info[irq] = mk_irq_info(IRQT_IPI, ipi, evtchn); | |
718 | bind_evtchn_to_cpu(evtchn, cpu); | |
719 | ||
720 | /* Ready for use. */ | |
721 | unmask_evtchn(evtchn); | |
722 | ||
723 | } | |
724 | } | |
725 | ||
2d9e1e2f JF |
726 | /* Clear an irq's pending state, in preparation for polling on it */ |
727 | void xen_clear_irq_pending(int irq) | |
728 | { | |
729 | int evtchn = evtchn_from_irq(irq); | |
730 | ||
731 | if (VALID_EVTCHN(evtchn)) | |
732 | clear_evtchn(evtchn); | |
733 | } | |
734 | ||
735 | /* Poll waiting for an irq to become pending. In the usual case, the | |
736 | irq will be disabled so it won't deliver an interrupt. */ | |
737 | void xen_poll_irq(int irq) | |
738 | { | |
739 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
740 | ||
741 | if (VALID_EVTCHN(evtchn)) { | |
742 | struct sched_poll poll; | |
743 | ||
744 | poll.nr_ports = 1; | |
745 | poll.timeout = 0; | |
746 | poll.ports = &evtchn; | |
747 | ||
748 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
749 | BUG(); | |
750 | } | |
751 | } | |
752 | ||
0e91398f JF |
753 | void xen_irq_resume(void) |
754 | { | |
755 | unsigned int cpu, irq, evtchn; | |
756 | ||
757 | init_evtchn_cpu_bindings(); | |
758 | ||
759 | /* New event-channel space is not 'live' yet. */ | |
760 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
761 | mask_evtchn(evtchn); | |
762 | ||
763 | /* No IRQ <-> event-channel mappings. */ | |
764 | for (irq = 0; irq < NR_IRQS; irq++) | |
765 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ | |
766 | ||
767 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
768 | evtchn_to_irq[evtchn] = -1; | |
769 | ||
770 | for_each_possible_cpu(cpu) { | |
771 | restore_cpu_virqs(cpu); | |
772 | restore_cpu_ipis(cpu); | |
773 | } | |
774 | } | |
775 | ||
e46cdb66 JF |
776 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
777 | .name = "xen-dyn", | |
778 | .mask = disable_dynirq, | |
779 | .unmask = enable_dynirq, | |
780 | .ack = ack_dynirq, | |
781 | .set_affinity = set_affinity_irq, | |
782 | .retrigger = retrigger_dynirq, | |
783 | }; | |
784 | ||
785 | void __init xen_init_IRQ(void) | |
786 | { | |
787 | int i; | |
788 | ||
789 | init_evtchn_cpu_bindings(); | |
790 | ||
791 | /* No event channels are 'live' right now. */ | |
792 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
793 | mask_evtchn(i); | |
794 | ||
795 | /* Dynamic IRQ space is currently unbound. Zero the refcnts. */ | |
796 | for (i = 0; i < NR_IRQS; i++) | |
797 | irq_bindcount[i] = 0; | |
798 | ||
799 | irq_ctx_init(smp_processor_id()); | |
800 | } |