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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
25985edc | 8 | * chip. When an event is received, it is mapped to an irq and sent |
e46cdb66 JF |
9 | * through the normal interrupt processing path. |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
f731e3ef | 32 | #include <linux/pci.h> |
e46cdb66 | 33 | |
0ec53ecf | 34 | #ifdef CONFIG_X86 |
38e20b07 | 35 | #include <asm/desc.h> |
e46cdb66 JF |
36 | #include <asm/ptrace.h> |
37 | #include <asm/irq.h> | |
792dc4f6 | 38 | #include <asm/idle.h> |
0794bfc7 | 39 | #include <asm/io_apic.h> |
9846ff10 | 40 | #include <asm/xen/page.h> |
42a1de56 | 41 | #include <asm/xen/pci.h> |
0ec53ecf SS |
42 | #endif |
43 | #include <asm/sync_bitops.h> | |
e46cdb66 | 44 | #include <asm/xen/hypercall.h> |
8d1b8753 | 45 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 46 | |
38e20b07 SY |
47 | #include <xen/xen.h> |
48 | #include <xen/hvm.h> | |
e04d0d07 | 49 | #include <xen/xen-ops.h> |
e46cdb66 JF |
50 | #include <xen/events.h> |
51 | #include <xen/interface/xen.h> | |
52 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
53 | #include <xen/interface/hvm/hvm_op.h> |
54 | #include <xen/interface/hvm/params.h> | |
0ec53ecf SS |
55 | #include <xen/interface/physdev.h> |
56 | #include <xen/interface/sched.h> | |
57 | #include <asm/hw_irq.h> | |
e46cdb66 | 58 | |
e46cdb66 JF |
59 | /* |
60 | * This lock protects updates to the following mapping and reference-count | |
61 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
62 | */ | |
77365948 | 63 | static DEFINE_MUTEX(irq_mapping_update_lock); |
e46cdb66 | 64 | |
6cb6537d IC |
65 | static LIST_HEAD(xen_irq_list_head); |
66 | ||
e46cdb66 | 67 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 68 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 69 | |
f87e4cac | 70 | /* IRQ <-> IPI mapping */ |
204fba4a | 71 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 72 | |
ced40d0f JF |
73 | /* Interrupt types. */ |
74 | enum xen_irq_type { | |
d77bbd4d | 75 | IRQT_UNBOUND = 0, |
f87e4cac JF |
76 | IRQT_PIRQ, |
77 | IRQT_VIRQ, | |
78 | IRQT_IPI, | |
79 | IRQT_EVTCHN | |
80 | }; | |
e46cdb66 | 81 | |
ced40d0f JF |
82 | /* |
83 | * Packed IRQ information: | |
84 | * type - enum xen_irq_type | |
85 | * event channel - irq->event channel mapping | |
86 | * cpu - cpu this event channel is bound to | |
87 | * index - type-specific information: | |
dec02dea | 88 | * PIRQ - physical IRQ, GSI, flags, and owner domain |
ced40d0f JF |
89 | * VIRQ - virq number |
90 | * IPI - IPI vector | |
91 | * EVTCHN - | |
92 | */ | |
088c05a8 | 93 | struct irq_info { |
6cb6537d | 94 | struct list_head list; |
420eb554 | 95 | int refcnt; |
ced40d0f | 96 | enum xen_irq_type type; /* type */ |
6cb6537d | 97 | unsigned irq; |
ced40d0f JF |
98 | unsigned short evtchn; /* event channel */ |
99 | unsigned short cpu; /* cpu bound */ | |
100 | ||
101 | union { | |
102 | unsigned short virq; | |
103 | enum ipi_vector ipi; | |
104 | struct { | |
7a043f11 | 105 | unsigned short pirq; |
ced40d0f | 106 | unsigned short gsi; |
d46a78b0 | 107 | unsigned char flags; |
beafbdc1 | 108 | uint16_t domid; |
ced40d0f JF |
109 | } pirq; |
110 | } u; | |
111 | }; | |
d46a78b0 | 112 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 113 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 114 | |
b21ddbf5 | 115 | static int *evtchn_to_irq; |
bf86ad80 | 116 | #ifdef CONFIG_X86 |
9846ff10 | 117 | static unsigned long *pirq_eoi_map; |
bf86ad80 | 118 | #endif |
9846ff10 | 119 | static bool (*pirq_needs_eoi)(unsigned irq); |
3b32f574 | 120 | |
c81611c4 IC |
121 | /* |
122 | * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be | |
123 | * careful to only use bitops which allow for this (e.g | |
124 | * test_bit/find_first_bit and friends but not __ffs) and to pass | |
125 | * BITS_PER_EVTCHN_WORD as the bitmask length. | |
126 | */ | |
127 | #define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8) | |
128 | /* | |
129 | * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t | |
130 | * array. Primarily to avoid long lines (hence the terse name). | |
131 | */ | |
132 | #define BM(x) (unsigned long *)(x) | |
133 | /* Find the first set bit in a evtchn mask */ | |
134 | #define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD) | |
135 | ||
136 | static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD], | |
cb60d114 | 137 | cpu_evtchn_mask); |
e46cdb66 | 138 | |
e46cdb66 JF |
139 | /* Xen will never allocate port zero for any purpose. */ |
140 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
141 | ||
e46cdb66 | 142 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 143 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 144 | static struct irq_chip xen_pirq_chip; |
7e186bdd SS |
145 | static void enable_dynirq(struct irq_data *data); |
146 | static void disable_dynirq(struct irq_data *data); | |
e46cdb66 | 147 | |
9158c358 IC |
148 | /* Get info for IRQ */ |
149 | static struct irq_info *info_for_irq(unsigned irq) | |
ced40d0f | 150 | { |
c442b806 | 151 | return irq_get_handler_data(irq); |
ced40d0f JF |
152 | } |
153 | ||
9158c358 IC |
154 | /* Constructors for packed IRQ information. */ |
155 | static void xen_irq_info_common_init(struct irq_info *info, | |
3d4cfa37 | 156 | unsigned irq, |
9158c358 IC |
157 | enum xen_irq_type type, |
158 | unsigned short evtchn, | |
159 | unsigned short cpu) | |
ced40d0f | 160 | { |
9158c358 IC |
161 | |
162 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
163 | ||
164 | info->type = type; | |
6cb6537d | 165 | info->irq = irq; |
9158c358 IC |
166 | info->evtchn = evtchn; |
167 | info->cpu = cpu; | |
3d4cfa37 IC |
168 | |
169 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f JF |
170 | } |
171 | ||
9158c358 IC |
172 | static void xen_irq_info_evtchn_init(unsigned irq, |
173 | unsigned short evtchn) | |
ced40d0f | 174 | { |
9158c358 IC |
175 | struct irq_info *info = info_for_irq(irq); |
176 | ||
3d4cfa37 | 177 | xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
178 | } |
179 | ||
3d4cfa37 IC |
180 | static void xen_irq_info_ipi_init(unsigned cpu, |
181 | unsigned irq, | |
9158c358 IC |
182 | unsigned short evtchn, |
183 | enum ipi_vector ipi) | |
e46cdb66 | 184 | { |
9158c358 IC |
185 | struct irq_info *info = info_for_irq(irq); |
186 | ||
3d4cfa37 | 187 | xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0); |
9158c358 IC |
188 | |
189 | info->u.ipi = ipi; | |
3d4cfa37 IC |
190 | |
191 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
ced40d0f JF |
192 | } |
193 | ||
3d4cfa37 IC |
194 | static void xen_irq_info_virq_init(unsigned cpu, |
195 | unsigned irq, | |
9158c358 IC |
196 | unsigned short evtchn, |
197 | unsigned short virq) | |
ced40d0f | 198 | { |
9158c358 IC |
199 | struct irq_info *info = info_for_irq(irq); |
200 | ||
3d4cfa37 | 201 | xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0); |
9158c358 IC |
202 | |
203 | info->u.virq = virq; | |
3d4cfa37 IC |
204 | |
205 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
ced40d0f JF |
206 | } |
207 | ||
9158c358 IC |
208 | static void xen_irq_info_pirq_init(unsigned irq, |
209 | unsigned short evtchn, | |
210 | unsigned short pirq, | |
211 | unsigned short gsi, | |
beafbdc1 | 212 | uint16_t domid, |
9158c358 | 213 | unsigned char flags) |
ced40d0f | 214 | { |
9158c358 IC |
215 | struct irq_info *info = info_for_irq(irq); |
216 | ||
3d4cfa37 | 217 | xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0); |
9158c358 IC |
218 | |
219 | info->u.pirq.pirq = pirq; | |
220 | info->u.pirq.gsi = gsi; | |
beafbdc1 | 221 | info->u.pirq.domid = domid; |
9158c358 | 222 | info->u.pirq.flags = flags; |
e46cdb66 JF |
223 | } |
224 | ||
225 | /* | |
226 | * Accessors for packed IRQ information. | |
227 | */ | |
ced40d0f | 228 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 229 | { |
110e7c7e JJ |
230 | if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
231 | return 0; | |
232 | ||
ced40d0f | 233 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
234 | } |
235 | ||
d4c04536 IC |
236 | unsigned irq_from_evtchn(unsigned int evtchn) |
237 | { | |
238 | return evtchn_to_irq[evtchn]; | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
241 | ||
ced40d0f | 242 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 243 | { |
ced40d0f JF |
244 | struct irq_info *info = info_for_irq(irq); |
245 | ||
246 | BUG_ON(info == NULL); | |
247 | BUG_ON(info->type != IRQT_IPI); | |
248 | ||
249 | return info->u.ipi; | |
250 | } | |
251 | ||
252 | static unsigned virq_from_irq(unsigned irq) | |
253 | { | |
254 | struct irq_info *info = info_for_irq(irq); | |
255 | ||
256 | BUG_ON(info == NULL); | |
257 | BUG_ON(info->type != IRQT_VIRQ); | |
258 | ||
259 | return info->u.virq; | |
260 | } | |
261 | ||
7a043f11 SS |
262 | static unsigned pirq_from_irq(unsigned irq) |
263 | { | |
264 | struct irq_info *info = info_for_irq(irq); | |
265 | ||
266 | BUG_ON(info == NULL); | |
267 | BUG_ON(info->type != IRQT_PIRQ); | |
268 | ||
269 | return info->u.pirq.pirq; | |
270 | } | |
271 | ||
ced40d0f JF |
272 | static enum xen_irq_type type_from_irq(unsigned irq) |
273 | { | |
274 | return info_for_irq(irq)->type; | |
275 | } | |
276 | ||
277 | static unsigned cpu_from_irq(unsigned irq) | |
278 | { | |
279 | return info_for_irq(irq)->cpu; | |
280 | } | |
281 | ||
282 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
283 | { | |
284 | int irq = evtchn_to_irq[evtchn]; | |
285 | unsigned ret = 0; | |
286 | ||
287 | if (irq != -1) | |
288 | ret = cpu_from_irq(irq); | |
289 | ||
290 | return ret; | |
e46cdb66 JF |
291 | } |
292 | ||
bf86ad80 | 293 | #ifdef CONFIG_X86 |
9846ff10 | 294 | static bool pirq_check_eoi_map(unsigned irq) |
d46a78b0 | 295 | { |
521394e4 | 296 | return test_bit(pirq_from_irq(irq), pirq_eoi_map); |
9846ff10 | 297 | } |
bf86ad80 | 298 | #endif |
d46a78b0 | 299 | |
9846ff10 SS |
300 | static bool pirq_needs_eoi_flag(unsigned irq) |
301 | { | |
302 | struct irq_info *info = info_for_irq(irq); | |
d46a78b0 JF |
303 | BUG_ON(info->type != IRQT_PIRQ); |
304 | ||
305 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
306 | } | |
307 | ||
c81611c4 IC |
308 | static inline xen_ulong_t active_evtchns(unsigned int cpu, |
309 | struct shared_info *sh, | |
310 | unsigned int idx) | |
e46cdb66 | 311 | { |
088c05a8 | 312 | return sh->evtchn_pending[idx] & |
cb60d114 | 313 | per_cpu(cpu_evtchn_mask, cpu)[idx] & |
088c05a8 | 314 | ~sh->evtchn_mask[idx]; |
e46cdb66 JF |
315 | } |
316 | ||
317 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
318 | { | |
319 | int irq = evtchn_to_irq[chn]; | |
320 | ||
321 | BUG_ON(irq == -1); | |
322 | #ifdef CONFIG_SMP | |
c9e265e0 | 323 | cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu)); |
e46cdb66 JF |
324 | #endif |
325 | ||
c81611c4 IC |
326 | clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)))); |
327 | set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu))); | |
e46cdb66 | 328 | |
ca62ce8c | 329 | info_for_irq(irq)->cpu = cpu; |
e46cdb66 JF |
330 | } |
331 | ||
332 | static void init_evtchn_cpu_bindings(void) | |
333 | { | |
1c6969ec | 334 | int i; |
e46cdb66 | 335 | #ifdef CONFIG_SMP |
6cb6537d | 336 | struct irq_info *info; |
10e58084 | 337 | |
e46cdb66 | 338 | /* By default all event channels notify CPU#0. */ |
6cb6537d IC |
339 | list_for_each_entry(info, &xen_irq_list_head, list) { |
340 | struct irq_desc *desc = irq_to_desc(info->irq); | |
c9e265e0 | 341 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); |
0b8f1efa | 342 | } |
e46cdb66 JF |
343 | #endif |
344 | ||
1c6969ec | 345 | for_each_possible_cpu(i) |
cb60d114 IC |
346 | memset(per_cpu(cpu_evtchn_mask, i), |
347 | (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i))); | |
e46cdb66 JF |
348 | } |
349 | ||
e46cdb66 JF |
350 | static inline void clear_evtchn(int port) |
351 | { | |
352 | struct shared_info *s = HYPERVISOR_shared_info; | |
c81611c4 | 353 | sync_clear_bit(port, BM(&s->evtchn_pending[0])); |
e46cdb66 JF |
354 | } |
355 | ||
356 | static inline void set_evtchn(int port) | |
357 | { | |
358 | struct shared_info *s = HYPERVISOR_shared_info; | |
c81611c4 | 359 | sync_set_bit(port, BM(&s->evtchn_pending[0])); |
e46cdb66 JF |
360 | } |
361 | ||
168d2f46 JF |
362 | static inline int test_evtchn(int port) |
363 | { | |
364 | struct shared_info *s = HYPERVISOR_shared_info; | |
c81611c4 | 365 | return sync_test_bit(port, BM(&s->evtchn_pending[0])); |
168d2f46 JF |
366 | } |
367 | ||
e46cdb66 JF |
368 | |
369 | /** | |
370 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
371 | * @irq: irq of event channel to send event to | |
372 | * | |
373 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
374 | * save/restore. Notifications on a broken connection are silently | |
375 | * dropped. | |
376 | */ | |
377 | void notify_remote_via_irq(int irq) | |
378 | { | |
379 | int evtchn = evtchn_from_irq(irq); | |
380 | ||
381 | if (VALID_EVTCHN(evtchn)) | |
382 | notify_remote_via_evtchn(evtchn); | |
383 | } | |
384 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
385 | ||
386 | static void mask_evtchn(int port) | |
387 | { | |
388 | struct shared_info *s = HYPERVISOR_shared_info; | |
c81611c4 | 389 | sync_set_bit(port, BM(&s->evtchn_mask[0])); |
e46cdb66 JF |
390 | } |
391 | ||
392 | static void unmask_evtchn(int port) | |
393 | { | |
394 | struct shared_info *s = HYPERVISOR_shared_info; | |
395 | unsigned int cpu = get_cpu(); | |
b5e57923 | 396 | int do_hypercall = 0, evtchn_pending = 0; |
e46cdb66 JF |
397 | |
398 | BUG_ON(!irqs_disabled()); | |
399 | ||
b5e57923 SS |
400 | if (unlikely((cpu != cpu_from_evtchn(port)))) |
401 | do_hypercall = 1; | |
c26377e6 DV |
402 | else { |
403 | /* | |
404 | * Need to clear the mask before checking pending to | |
405 | * avoid a race with an event becoming pending. | |
406 | * | |
407 | * EVTCHNOP_unmask will only trigger an upcall if the | |
408 | * mask bit was set, so if a hypercall is needed | |
409 | * remask the event. | |
410 | */ | |
411 | sync_clear_bit(port, BM(&s->evtchn_mask[0])); | |
c81611c4 | 412 | evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0])); |
b5e57923 | 413 | |
c26377e6 DV |
414 | if (unlikely(evtchn_pending && xen_hvm_domain())) { |
415 | sync_set_bit(port, BM(&s->evtchn_mask[0])); | |
416 | do_hypercall = 1; | |
417 | } | |
418 | } | |
b5e57923 SS |
419 | |
420 | /* Slow path (hypercall) if this is a non-local port or if this is | |
421 | * an hvm domain and an event is pending (hvm domains don't have | |
422 | * their own implementation of irq_enable). */ | |
423 | if (do_hypercall) { | |
e46cdb66 JF |
424 | struct evtchn_unmask unmask = { .port = port }; |
425 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
426 | } else { | |
780f36d8 | 427 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
e46cdb66 | 428 | |
e46cdb66 JF |
429 | /* |
430 | * The following is basically the equivalent of | |
431 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
432 | * the interrupt edge' if the channel is masked. | |
433 | */ | |
b5e57923 | 434 | if (evtchn_pending && |
c81611c4 IC |
435 | !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD, |
436 | BM(&vcpu_info->evtchn_pending_sel))) | |
e46cdb66 JF |
437 | vcpu_info->evtchn_upcall_pending = 1; |
438 | } | |
439 | ||
440 | put_cpu(); | |
441 | } | |
442 | ||
6cb6537d IC |
443 | static void xen_irq_init(unsigned irq) |
444 | { | |
445 | struct irq_info *info; | |
b5328cd1 | 446 | #ifdef CONFIG_SMP |
6cb6537d IC |
447 | struct irq_desc *desc = irq_to_desc(irq); |
448 | ||
449 | /* By default all event channels notify CPU#0. */ | |
450 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); | |
44626e4a | 451 | #endif |
6cb6537d | 452 | |
ca62ce8c IC |
453 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
454 | if (info == NULL) | |
455 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
456 | |
457 | info->type = IRQT_UNBOUND; | |
420eb554 | 458 | info->refcnt = -1; |
6cb6537d | 459 | |
c442b806 | 460 | irq_set_handler_data(irq, info); |
ca62ce8c | 461 | |
6cb6537d IC |
462 | list_add_tail(&info->list, &xen_irq_list_head); |
463 | } | |
464 | ||
7bee9768 | 465 | static int __must_check xen_allocate_irq_dynamic(void) |
0794bfc7 | 466 | { |
89911501 IC |
467 | int first = 0; |
468 | int irq; | |
0794bfc7 KRW |
469 | |
470 | #ifdef CONFIG_X86_IO_APIC | |
89911501 IC |
471 | /* |
472 | * For an HVM guest or domain 0 which see "real" (emulated or | |
25985edc | 473 | * actual respectively) GSIs we allocate dynamic IRQs |
89911501 IC |
474 | * e.g. those corresponding to event channels or MSIs |
475 | * etc. from the range above those "real" GSIs to avoid | |
476 | * collisions. | |
477 | */ | |
478 | if (xen_initial_domain() || xen_hvm_domain()) | |
479 | first = get_nr_irqs_gsi(); | |
0794bfc7 KRW |
480 | #endif |
481 | ||
89911501 | 482 | irq = irq_alloc_desc_from(first, -1); |
3a69e916 | 483 | |
e6599225 KRW |
484 | if (irq >= 0) |
485 | xen_irq_init(irq); | |
ced40d0f | 486 | |
e46cdb66 | 487 | return irq; |
d46a78b0 JF |
488 | } |
489 | ||
7bee9768 | 490 | static int __must_check xen_allocate_irq_gsi(unsigned gsi) |
c9df1ce5 IC |
491 | { |
492 | int irq; | |
493 | ||
89911501 IC |
494 | /* |
495 | * A PV guest has no concept of a GSI (since it has no ACPI | |
496 | * nor access to/knowledge of the physical APICs). Therefore | |
497 | * all IRQs are dynamically allocated from the entire IRQ | |
498 | * space. | |
499 | */ | |
500 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
501 | return xen_allocate_irq_dynamic(); |
502 | ||
503 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
504 | if (gsi < NR_IRQS_LEGACY) | |
6cb6537d IC |
505 | irq = gsi; |
506 | else | |
507 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 508 | |
6cb6537d | 509 | xen_irq_init(irq); |
c9df1ce5 IC |
510 | |
511 | return irq; | |
512 | } | |
513 | ||
514 | static void xen_free_irq(unsigned irq) | |
515 | { | |
c442b806 | 516 | struct irq_info *info = irq_get_handler_data(irq); |
6cb6537d IC |
517 | |
518 | list_del(&info->list); | |
9158c358 | 519 | |
c442b806 | 520 | irq_set_handler_data(irq, NULL); |
ca62ce8c | 521 | |
420eb554 DDG |
522 | WARN_ON(info->refcnt > 0); |
523 | ||
ca62ce8c IC |
524 | kfree(info); |
525 | ||
72146104 IC |
526 | /* Legacy IRQ descriptors are managed by the arch. */ |
527 | if (irq < NR_IRQS_LEGACY) | |
528 | return; | |
529 | ||
c9df1ce5 IC |
530 | irq_free_desc(irq); |
531 | } | |
532 | ||
d46a78b0 JF |
533 | static void pirq_query_unmask(int irq) |
534 | { | |
535 | struct physdev_irq_status_query irq_status; | |
536 | struct irq_info *info = info_for_irq(irq); | |
537 | ||
538 | BUG_ON(info->type != IRQT_PIRQ); | |
539 | ||
7a043f11 | 540 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
541 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
542 | irq_status.flags = 0; | |
543 | ||
544 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
545 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
546 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
547 | } | |
548 | ||
549 | static bool probing_irq(int irq) | |
550 | { | |
551 | struct irq_desc *desc = irq_to_desc(irq); | |
552 | ||
553 | return desc && desc->action == NULL; | |
554 | } | |
555 | ||
7e186bdd SS |
556 | static void eoi_pirq(struct irq_data *data) |
557 | { | |
558 | int evtchn = evtchn_from_irq(data->irq); | |
559 | struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) }; | |
560 | int rc = 0; | |
561 | ||
562 | irq_move_irq(data); | |
563 | ||
564 | if (VALID_EVTCHN(evtchn)) | |
565 | clear_evtchn(evtchn); | |
566 | ||
567 | if (pirq_needs_eoi(data->irq)) { | |
568 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
569 | WARN_ON(rc); | |
570 | } | |
571 | } | |
572 | ||
573 | static void mask_ack_pirq(struct irq_data *data) | |
574 | { | |
575 | disable_dynirq(data); | |
576 | eoi_pirq(data); | |
577 | } | |
578 | ||
c9e265e0 | 579 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
580 | { |
581 | struct evtchn_bind_pirq bind_pirq; | |
582 | struct irq_info *info = info_for_irq(irq); | |
583 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 584 | int rc; |
d46a78b0 JF |
585 | |
586 | BUG_ON(info->type != IRQT_PIRQ); | |
587 | ||
588 | if (VALID_EVTCHN(evtchn)) | |
589 | goto out; | |
590 | ||
7a043f11 | 591 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 592 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
593 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
594 | BIND_PIRQ__WILL_SHARE : 0; | |
595 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
596 | if (rc != 0) { | |
d46a78b0 JF |
597 | if (!probing_irq(irq)) |
598 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
599 | irq); | |
600 | return 0; | |
601 | } | |
602 | evtchn = bind_pirq.port; | |
603 | ||
604 | pirq_query_unmask(irq); | |
605 | ||
606 | evtchn_to_irq[evtchn] = irq; | |
607 | bind_evtchn_to_cpu(evtchn, 0); | |
608 | info->evtchn = evtchn; | |
609 | ||
610 | out: | |
611 | unmask_evtchn(evtchn); | |
7e186bdd | 612 | eoi_pirq(irq_get_irq_data(irq)); |
d46a78b0 JF |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
c9e265e0 TG |
617 | static unsigned int startup_pirq(struct irq_data *data) |
618 | { | |
619 | return __startup_pirq(data->irq); | |
620 | } | |
621 | ||
622 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 JF |
623 | { |
624 | struct evtchn_close close; | |
c9e265e0 | 625 | unsigned int irq = data->irq; |
d46a78b0 JF |
626 | struct irq_info *info = info_for_irq(irq); |
627 | int evtchn = evtchn_from_irq(irq); | |
628 | ||
629 | BUG_ON(info->type != IRQT_PIRQ); | |
630 | ||
631 | if (!VALID_EVTCHN(evtchn)) | |
632 | return; | |
633 | ||
634 | mask_evtchn(evtchn); | |
635 | ||
636 | close.port = evtchn; | |
637 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
638 | BUG(); | |
639 | ||
640 | bind_evtchn_to_cpu(evtchn, 0); | |
641 | evtchn_to_irq[evtchn] = -1; | |
642 | info->evtchn = 0; | |
643 | } | |
644 | ||
c9e265e0 | 645 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 646 | { |
c9e265e0 | 647 | startup_pirq(data); |
d46a78b0 JF |
648 | } |
649 | ||
c9e265e0 | 650 | static void disable_pirq(struct irq_data *data) |
d46a78b0 | 651 | { |
7e186bdd | 652 | disable_dynirq(data); |
d46a78b0 JF |
653 | } |
654 | ||
68c2c39a | 655 | int xen_irq_from_gsi(unsigned gsi) |
d46a78b0 | 656 | { |
6cb6537d | 657 | struct irq_info *info; |
d46a78b0 | 658 | |
6cb6537d IC |
659 | list_for_each_entry(info, &xen_irq_list_head, list) { |
660 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
661 | continue; |
662 | ||
6cb6537d IC |
663 | if (info->u.pirq.gsi == gsi) |
664 | return info->irq; | |
d46a78b0 JF |
665 | } |
666 | ||
667 | return -1; | |
668 | } | |
68c2c39a | 669 | EXPORT_SYMBOL_GPL(xen_irq_from_gsi); |
d46a78b0 | 670 | |
653378ac IC |
671 | /* |
672 | * Do not make any assumptions regarding the relationship between the | |
673 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
674 | * |
675 | * Note: We don't assign an event channel until the irq actually started | |
676 | * up. Return an existing irq if we've already got one for the gsi. | |
e5ac0bda SS |
677 | * |
678 | * Shareable implies level triggered, not shareable implies edge | |
679 | * triggered here. | |
d46a78b0 | 680 | */ |
f4d0635b IC |
681 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
682 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 683 | { |
a0e18116 | 684 | int irq = -1; |
d46a78b0 JF |
685 | struct physdev_irq irq_op; |
686 | ||
77365948 | 687 | mutex_lock(&irq_mapping_update_lock); |
d46a78b0 | 688 | |
68c2c39a | 689 | irq = xen_irq_from_gsi(gsi); |
d46a78b0 | 690 | if (irq != -1) { |
7a043f11 | 691 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 | 692 | irq, gsi); |
420eb554 | 693 | goto out; |
d46a78b0 JF |
694 | } |
695 | ||
c9df1ce5 | 696 | irq = xen_allocate_irq_gsi(gsi); |
7bee9768 IC |
697 | if (irq < 0) |
698 | goto out; | |
d46a78b0 | 699 | |
d46a78b0 | 700 | irq_op.irq = irq; |
b5401a96 AN |
701 | irq_op.vector = 0; |
702 | ||
703 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
704 | * driver provides a PCI bus that does the call to do exactly | |
705 | * this in the priv domain. */ | |
706 | if (xen_initial_domain() && | |
707 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 708 | xen_free_irq(irq); |
d46a78b0 JF |
709 | irq = -ENOSPC; |
710 | goto out; | |
711 | } | |
712 | ||
dec02dea | 713 | xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF, |
9158c358 | 714 | shareable ? PIRQ_SHAREABLE : 0); |
d46a78b0 | 715 | |
7e186bdd SS |
716 | pirq_query_unmask(irq); |
717 | /* We try to use the handler with the appropriate semantic for the | |
e5ac0bda SS |
718 | * type of interrupt: if the interrupt is an edge triggered |
719 | * interrupt we use handle_edge_irq. | |
7e186bdd | 720 | * |
e5ac0bda SS |
721 | * On the other hand if the interrupt is level triggered we use |
722 | * handle_fasteoi_irq like the native code does for this kind of | |
7e186bdd | 723 | * interrupts. |
e5ac0bda | 724 | * |
7e186bdd SS |
725 | * Depending on the Xen version, pirq_needs_eoi might return true |
726 | * not only for level triggered interrupts but for edge triggered | |
727 | * interrupts too. In any case Xen always honors the eoi mechanism, | |
728 | * not injecting any more pirqs of the same kind if the first one | |
729 | * hasn't received an eoi yet. Therefore using the fasteoi handler | |
730 | * is the right choice either way. | |
731 | */ | |
e5ac0bda | 732 | if (shareable) |
7e186bdd SS |
733 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, |
734 | handle_fasteoi_irq, name); | |
735 | else | |
736 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, | |
737 | handle_edge_irq, name); | |
738 | ||
d46a78b0 | 739 | out: |
77365948 | 740 | mutex_unlock(&irq_mapping_update_lock); |
d46a78b0 JF |
741 | |
742 | return irq; | |
743 | } | |
744 | ||
f731e3ef | 745 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 746 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 747 | { |
5cad61a6 | 748 | int rc; |
cbf6aa89 | 749 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 750 | |
bf480d95 | 751 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 752 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 753 | |
5cad61a6 IC |
754 | WARN_ONCE(rc == -ENOSYS, |
755 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
756 | ||
757 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
758 | } |
759 | ||
bf480d95 | 760 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
dec02dea | 761 | int pirq, const char *name, domid_t domid) |
809f9267 | 762 | { |
bf480d95 | 763 | int irq, ret; |
4b41df7f | 764 | |
77365948 | 765 | mutex_lock(&irq_mapping_update_lock); |
809f9267 | 766 | |
4b41df7f | 767 | irq = xen_allocate_irq_dynamic(); |
e6599225 | 768 | if (irq < 0) |
bb5d079a | 769 | goto out; |
809f9267 | 770 | |
7e186bdd SS |
771 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq, |
772 | name); | |
809f9267 | 773 | |
dec02dea | 774 | xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0); |
5f6fb454 | 775 | ret = irq_set_msi_desc(irq, msidesc); |
bf480d95 IC |
776 | if (ret < 0) |
777 | goto error_irq; | |
809f9267 | 778 | out: |
77365948 | 779 | mutex_unlock(&irq_mapping_update_lock); |
4b41df7f | 780 | return irq; |
bf480d95 | 781 | error_irq: |
77365948 | 782 | mutex_unlock(&irq_mapping_update_lock); |
bf480d95 | 783 | xen_free_irq(irq); |
e6599225 | 784 | return ret; |
809f9267 | 785 | } |
f731e3ef QH |
786 | #endif |
787 | ||
b5401a96 AN |
788 | int xen_destroy_irq(int irq) |
789 | { | |
790 | struct irq_desc *desc; | |
38aa66fc JF |
791 | struct physdev_unmap_pirq unmap_irq; |
792 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
793 | int rc = -ENOENT; |
794 | ||
77365948 | 795 | mutex_lock(&irq_mapping_update_lock); |
b5401a96 AN |
796 | |
797 | desc = irq_to_desc(irq); | |
798 | if (!desc) | |
799 | goto out; | |
800 | ||
38aa66fc | 801 | if (xen_initial_domain()) { |
12334715 | 802 | unmap_irq.pirq = info->u.pirq.pirq; |
beafbdc1 | 803 | unmap_irq.domid = info->u.pirq.domid; |
38aa66fc | 804 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); |
1eff1ad0 KRW |
805 | /* If another domain quits without making the pci_disable_msix |
806 | * call, the Xen hypervisor takes care of freeing the PIRQs | |
807 | * (free_domain_pirqs). | |
808 | */ | |
809 | if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF)) | |
810 | printk(KERN_INFO "domain %d does not have %d anymore\n", | |
811 | info->u.pirq.domid, info->u.pirq.pirq); | |
812 | else if (rc) { | |
38aa66fc JF |
813 | printk(KERN_WARNING "unmap irq failed %d\n", rc); |
814 | goto out; | |
815 | } | |
816 | } | |
b5401a96 | 817 | |
c9df1ce5 | 818 | xen_free_irq(irq); |
b5401a96 AN |
819 | |
820 | out: | |
77365948 | 821 | mutex_unlock(&irq_mapping_update_lock); |
b5401a96 AN |
822 | return rc; |
823 | } | |
824 | ||
af42b8d1 | 825 | int xen_irq_from_pirq(unsigned pirq) |
d46a78b0 | 826 | { |
69c358ce | 827 | int irq; |
d46a78b0 | 828 | |
69c358ce | 829 | struct irq_info *info; |
e46cdb66 | 830 | |
77365948 | 831 | mutex_lock(&irq_mapping_update_lock); |
69c358ce IC |
832 | |
833 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
9bb9efe4 | 834 | if (info->type != IRQT_PIRQ) |
69c358ce IC |
835 | continue; |
836 | irq = info->irq; | |
837 | if (info->u.pirq.pirq == pirq) | |
838 | goto out; | |
839 | } | |
840 | irq = -1; | |
841 | out: | |
77365948 | 842 | mutex_unlock(&irq_mapping_update_lock); |
69c358ce IC |
843 | |
844 | return irq; | |
af42b8d1 SS |
845 | } |
846 | ||
e6197acc KRW |
847 | |
848 | int xen_pirq_from_irq(unsigned irq) | |
849 | { | |
850 | return pirq_from_irq(irq); | |
851 | } | |
852 | EXPORT_SYMBOL_GPL(xen_pirq_from_irq); | |
b536b4b9 | 853 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
854 | { |
855 | int irq; | |
856 | ||
77365948 | 857 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
858 | |
859 | irq = evtchn_to_irq[evtchn]; | |
860 | ||
861 | if (irq == -1) { | |
c9df1ce5 | 862 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 863 | if (irq < 0) |
7bee9768 | 864 | goto out; |
e46cdb66 | 865 | |
c442b806 | 866 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, |
7e186bdd | 867 | handle_edge_irq, "event"); |
e46cdb66 | 868 | |
9158c358 | 869 | xen_irq_info_evtchn_init(irq, evtchn); |
5e152e6c KRW |
870 | } else { |
871 | struct irq_info *info = info_for_irq(irq); | |
872 | WARN_ON(info == NULL || info->type != IRQT_EVTCHN); | |
e46cdb66 | 873 | } |
a8636c0b | 874 | irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN); |
e46cdb66 | 875 | |
7bee9768 | 876 | out: |
77365948 | 877 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
878 | |
879 | return irq; | |
880 | } | |
b536b4b9 | 881 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 882 | |
f87e4cac JF |
883 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
884 | { | |
885 | struct evtchn_bind_ipi bind_ipi; | |
886 | int evtchn, irq; | |
887 | ||
77365948 | 888 | mutex_lock(&irq_mapping_update_lock); |
f87e4cac JF |
889 | |
890 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 891 | |
f87e4cac | 892 | if (irq == -1) { |
c9df1ce5 | 893 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
894 | if (irq < 0) |
895 | goto out; | |
896 | ||
c442b806 | 897 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
aaca4964 | 898 | handle_percpu_irq, "ipi"); |
f87e4cac JF |
899 | |
900 | bind_ipi.vcpu = cpu; | |
901 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
902 | &bind_ipi) != 0) | |
903 | BUG(); | |
904 | evtchn = bind_ipi.port; | |
905 | ||
3d4cfa37 | 906 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
f87e4cac JF |
907 | |
908 | bind_evtchn_to_cpu(evtchn, cpu); | |
5e152e6c KRW |
909 | } else { |
910 | struct irq_info *info = info_for_irq(irq); | |
911 | WARN_ON(info == NULL || info->type != IRQT_IPI); | |
f87e4cac JF |
912 | } |
913 | ||
f87e4cac | 914 | out: |
77365948 | 915 | mutex_unlock(&irq_mapping_update_lock); |
f87e4cac JF |
916 | return irq; |
917 | } | |
918 | ||
2e820f58 IC |
919 | static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain, |
920 | unsigned int remote_port) | |
921 | { | |
922 | struct evtchn_bind_interdomain bind_interdomain; | |
923 | int err; | |
924 | ||
925 | bind_interdomain.remote_dom = remote_domain; | |
926 | bind_interdomain.remote_port = remote_port; | |
927 | ||
928 | err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, | |
929 | &bind_interdomain); | |
930 | ||
931 | return err ? : bind_evtchn_to_irq(bind_interdomain.local_port); | |
932 | } | |
933 | ||
62cc5fc7 OH |
934 | static int find_virq(unsigned int virq, unsigned int cpu) |
935 | { | |
936 | struct evtchn_status status; | |
937 | int port, rc = -ENOENT; | |
938 | ||
939 | memset(&status, 0, sizeof(status)); | |
940 | for (port = 0; port <= NR_EVENT_CHANNELS; port++) { | |
941 | status.dom = DOMID_SELF; | |
942 | status.port = port; | |
943 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status); | |
944 | if (rc < 0) | |
945 | continue; | |
946 | if (status.status != EVTCHNSTAT_virq) | |
947 | continue; | |
948 | if (status.u.virq == virq && status.vcpu == cpu) { | |
949 | rc = port; | |
950 | break; | |
951 | } | |
952 | } | |
953 | return rc; | |
954 | } | |
f87e4cac | 955 | |
4fe7d5a7 | 956 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
957 | { |
958 | struct evtchn_bind_virq bind_virq; | |
62cc5fc7 | 959 | int evtchn, irq, ret; |
e46cdb66 | 960 | |
77365948 | 961 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
962 | |
963 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
964 | ||
965 | if (irq == -1) { | |
c9df1ce5 | 966 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 967 | if (irq < 0) |
7bee9768 | 968 | goto out; |
a52521f1 | 969 | |
c442b806 | 970 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
a52521f1 JF |
971 | handle_percpu_irq, "virq"); |
972 | ||
e46cdb66 JF |
973 | bind_virq.virq = virq; |
974 | bind_virq.vcpu = cpu; | |
62cc5fc7 OH |
975 | ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
976 | &bind_virq); | |
977 | if (ret == 0) | |
978 | evtchn = bind_virq.port; | |
979 | else { | |
980 | if (ret == -EEXIST) | |
981 | ret = find_virq(virq, cpu); | |
982 | BUG_ON(ret < 0); | |
983 | evtchn = ret; | |
984 | } | |
e46cdb66 | 985 | |
3d4cfa37 | 986 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
e46cdb66 JF |
987 | |
988 | bind_evtchn_to_cpu(evtchn, cpu); | |
5e152e6c KRW |
989 | } else { |
990 | struct irq_info *info = info_for_irq(irq); | |
991 | WARN_ON(info == NULL || info->type != IRQT_VIRQ); | |
e46cdb66 JF |
992 | } |
993 | ||
7bee9768 | 994 | out: |
77365948 | 995 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
996 | |
997 | return irq; | |
998 | } | |
999 | ||
1000 | static void unbind_from_irq(unsigned int irq) | |
1001 | { | |
1002 | struct evtchn_close close; | |
1003 | int evtchn = evtchn_from_irq(irq); | |
420eb554 | 1004 | struct irq_info *info = irq_get_handler_data(irq); |
e46cdb66 | 1005 | |
77365948 | 1006 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 | 1007 | |
420eb554 DDG |
1008 | if (info->refcnt > 0) { |
1009 | info->refcnt--; | |
1010 | if (info->refcnt != 0) | |
1011 | goto done; | |
1012 | } | |
1013 | ||
d77bbd4d | 1014 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
1015 | close.port = evtchn; |
1016 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
1017 | BUG(); | |
1018 | ||
1019 | switch (type_from_irq(irq)) { | |
1020 | case IRQT_VIRQ: | |
1021 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 1022 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 1023 | break; |
d68d82af AN |
1024 | case IRQT_IPI: |
1025 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 1026 | [ipi_from_irq(irq)] = -1; |
d68d82af | 1027 | break; |
e46cdb66 JF |
1028 | default: |
1029 | break; | |
1030 | } | |
1031 | ||
1032 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
1033 | bind_evtchn_to_cpu(evtchn, 0); | |
1034 | ||
1035 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
1036 | } |
1037 | ||
ca62ce8c | 1038 | BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND); |
e46cdb66 | 1039 | |
9158c358 | 1040 | xen_free_irq(irq); |
e46cdb66 | 1041 | |
420eb554 | 1042 | done: |
77365948 | 1043 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1044 | } |
1045 | ||
1046 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 1047 | irq_handler_t handler, |
e46cdb66 JF |
1048 | unsigned long irqflags, |
1049 | const char *devname, void *dev_id) | |
1050 | { | |
361ae8cb | 1051 | int irq, retval; |
e46cdb66 JF |
1052 | |
1053 | irq = bind_evtchn_to_irq(evtchn); | |
7bee9768 IC |
1054 | if (irq < 0) |
1055 | return irq; | |
e46cdb66 JF |
1056 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1057 | if (retval != 0) { | |
1058 | unbind_from_irq(irq); | |
1059 | return retval; | |
1060 | } | |
1061 | ||
1062 | return irq; | |
1063 | } | |
1064 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
1065 | ||
2e820f58 IC |
1066 | int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain, |
1067 | unsigned int remote_port, | |
1068 | irq_handler_t handler, | |
1069 | unsigned long irqflags, | |
1070 | const char *devname, | |
1071 | void *dev_id) | |
1072 | { | |
1073 | int irq, retval; | |
1074 | ||
1075 | irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port); | |
1076 | if (irq < 0) | |
1077 | return irq; | |
1078 | ||
1079 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
1080 | if (retval != 0) { | |
1081 | unbind_from_irq(irq); | |
1082 | return retval; | |
1083 | } | |
1084 | ||
1085 | return irq; | |
1086 | } | |
1087 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler); | |
1088 | ||
e46cdb66 | 1089 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, |
7c239975 | 1090 | irq_handler_t handler, |
e46cdb66 JF |
1091 | unsigned long irqflags, const char *devname, void *dev_id) |
1092 | { | |
361ae8cb | 1093 | int irq, retval; |
e46cdb66 JF |
1094 | |
1095 | irq = bind_virq_to_irq(virq, cpu); | |
7bee9768 IC |
1096 | if (irq < 0) |
1097 | return irq; | |
e46cdb66 JF |
1098 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1099 | if (retval != 0) { | |
1100 | unbind_from_irq(irq); | |
1101 | return retval; | |
1102 | } | |
1103 | ||
1104 | return irq; | |
1105 | } | |
1106 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
1107 | ||
f87e4cac JF |
1108 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
1109 | unsigned int cpu, | |
1110 | irq_handler_t handler, | |
1111 | unsigned long irqflags, | |
1112 | const char *devname, | |
1113 | void *dev_id) | |
1114 | { | |
1115 | int irq, retval; | |
1116 | ||
1117 | irq = bind_ipi_to_irq(ipi, cpu); | |
1118 | if (irq < 0) | |
1119 | return irq; | |
1120 | ||
9bab0b7f | 1121 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME; |
f87e4cac JF |
1122 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1123 | if (retval != 0) { | |
1124 | unbind_from_irq(irq); | |
1125 | return retval; | |
1126 | } | |
1127 | ||
1128 | return irq; | |
1129 | } | |
1130 | ||
e46cdb66 JF |
1131 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
1132 | { | |
1133 | free_irq(irq, dev_id); | |
1134 | unbind_from_irq(irq); | |
1135 | } | |
1136 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1137 | ||
420eb554 DDG |
1138 | int evtchn_make_refcounted(unsigned int evtchn) |
1139 | { | |
1140 | int irq = evtchn_to_irq[evtchn]; | |
1141 | struct irq_info *info; | |
1142 | ||
1143 | if (irq == -1) | |
1144 | return -ENOENT; | |
1145 | ||
1146 | info = irq_get_handler_data(irq); | |
1147 | ||
1148 | if (!info) | |
1149 | return -ENOENT; | |
1150 | ||
1151 | WARN_ON(info->refcnt != -1); | |
1152 | ||
1153 | info->refcnt = 1; | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | EXPORT_SYMBOL_GPL(evtchn_make_refcounted); | |
1158 | ||
1159 | int evtchn_get(unsigned int evtchn) | |
1160 | { | |
1161 | int irq; | |
1162 | struct irq_info *info; | |
1163 | int err = -ENOENT; | |
1164 | ||
c3b3f16d DDG |
1165 | if (evtchn >= NR_EVENT_CHANNELS) |
1166 | return -EINVAL; | |
1167 | ||
420eb554 DDG |
1168 | mutex_lock(&irq_mapping_update_lock); |
1169 | ||
1170 | irq = evtchn_to_irq[evtchn]; | |
1171 | if (irq == -1) | |
1172 | goto done; | |
1173 | ||
1174 | info = irq_get_handler_data(irq); | |
1175 | ||
1176 | if (!info) | |
1177 | goto done; | |
1178 | ||
1179 | err = -EINVAL; | |
1180 | if (info->refcnt <= 0) | |
1181 | goto done; | |
1182 | ||
1183 | info->refcnt++; | |
1184 | err = 0; | |
1185 | done: | |
1186 | mutex_unlock(&irq_mapping_update_lock); | |
1187 | ||
1188 | return err; | |
1189 | } | |
1190 | EXPORT_SYMBOL_GPL(evtchn_get); | |
1191 | ||
1192 | void evtchn_put(unsigned int evtchn) | |
1193 | { | |
1194 | int irq = evtchn_to_irq[evtchn]; | |
1195 | if (WARN_ON(irq == -1)) | |
1196 | return; | |
1197 | unbind_from_irq(irq); | |
1198 | } | |
1199 | EXPORT_SYMBOL_GPL(evtchn_put); | |
1200 | ||
f87e4cac JF |
1201 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1202 | { | |
1203 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
1204 | BUG_ON(irq < 0); | |
1205 | notify_remote_via_irq(irq); | |
1206 | } | |
1207 | ||
ee523ca1 JF |
1208 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
1209 | { | |
1210 | struct shared_info *sh = HYPERVISOR_shared_info; | |
1211 | int cpu = smp_processor_id(); | |
c81611c4 | 1212 | xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu); |
ee523ca1 JF |
1213 | int i; |
1214 | unsigned long flags; | |
1215 | static DEFINE_SPINLOCK(debug_lock); | |
cb52e6d9 | 1216 | struct vcpu_info *v; |
ee523ca1 JF |
1217 | |
1218 | spin_lock_irqsave(&debug_lock, flags); | |
1219 | ||
cb52e6d9 | 1220 | printk("\nvcpu %d\n ", cpu); |
ee523ca1 JF |
1221 | |
1222 | for_each_online_cpu(i) { | |
cb52e6d9 IC |
1223 | int pending; |
1224 | v = per_cpu(xen_vcpu, i); | |
1225 | pending = (get_irq_regs() && i == cpu) | |
1226 | ? xen_irqs_disabled(get_irq_regs()) | |
1227 | : v->evtchn_upcall_mask; | |
c81611c4 | 1228 | printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i, |
cb52e6d9 IC |
1229 | pending, v->evtchn_upcall_pending, |
1230 | (int)(sizeof(v->evtchn_pending_sel)*2), | |
1231 | v->evtchn_pending_sel); | |
1232 | } | |
1233 | v = per_cpu(xen_vcpu, cpu); | |
1234 | ||
1235 | printk("\npending:\n "); | |
1236 | for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
c81611c4 IC |
1237 | printk("%0*"PRI_xen_ulong"%s", |
1238 | (int)sizeof(sh->evtchn_pending[0])*2, | |
cb52e6d9 IC |
1239 | sh->evtchn_pending[i], |
1240 | i % 8 == 0 ? "\n " : " "); | |
1241 | printk("\nglobal mask:\n "); | |
1242 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
c81611c4 | 1243 | printk("%0*"PRI_xen_ulong"%s", |
cb52e6d9 IC |
1244 | (int)(sizeof(sh->evtchn_mask[0])*2), |
1245 | sh->evtchn_mask[i], | |
1246 | i % 8 == 0 ? "\n " : " "); | |
1247 | ||
1248 | printk("\nglobally unmasked:\n "); | |
1249 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
c81611c4 IC |
1250 | printk("%0*"PRI_xen_ulong"%s", |
1251 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
cb52e6d9 IC |
1252 | sh->evtchn_pending[i] & ~sh->evtchn_mask[i], |
1253 | i % 8 == 0 ? "\n " : " "); | |
1254 | ||
1255 | printk("\nlocal cpu%d mask:\n ", cpu); | |
c81611c4 IC |
1256 | for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--) |
1257 | printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2), | |
cb52e6d9 IC |
1258 | cpu_evtchn[i], |
1259 | i % 8 == 0 ? "\n " : " "); | |
1260 | ||
1261 | printk("\nlocally unmasked:\n "); | |
1262 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) { | |
c81611c4 | 1263 | xen_ulong_t pending = sh->evtchn_pending[i] |
cb52e6d9 IC |
1264 | & ~sh->evtchn_mask[i] |
1265 | & cpu_evtchn[i]; | |
c81611c4 IC |
1266 | printk("%0*"PRI_xen_ulong"%s", |
1267 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
cb52e6d9 | 1268 | pending, i % 8 == 0 ? "\n " : " "); |
ee523ca1 | 1269 | } |
ee523ca1 JF |
1270 | |
1271 | printk("\npending list:\n"); | |
cb52e6d9 | 1272 | for (i = 0; i < NR_EVENT_CHANNELS; i++) { |
c81611c4 IC |
1273 | if (sync_test_bit(i, BM(sh->evtchn_pending))) { |
1274 | int word_idx = i / BITS_PER_EVTCHN_WORD; | |
cb52e6d9 | 1275 | printk(" %d: event %d -> irq %d%s%s%s\n", |
ced40d0f | 1276 | cpu_from_evtchn(i), i, |
cb52e6d9 | 1277 | evtchn_to_irq[i], |
c81611c4 | 1278 | sync_test_bit(word_idx, BM(&v->evtchn_pending_sel)) |
cb52e6d9 | 1279 | ? "" : " l2-clear", |
c81611c4 | 1280 | !sync_test_bit(i, BM(sh->evtchn_mask)) |
cb52e6d9 | 1281 | ? "" : " globally-masked", |
c81611c4 | 1282 | sync_test_bit(i, BM(cpu_evtchn)) |
cb52e6d9 | 1283 | ? "" : " locally-masked"); |
ee523ca1 JF |
1284 | } |
1285 | } | |
1286 | ||
1287 | spin_unlock_irqrestore(&debug_lock, flags); | |
1288 | ||
1289 | return IRQ_HANDLED; | |
1290 | } | |
1291 | ||
245b2e70 | 1292 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
ada6814c KF |
1293 | static DEFINE_PER_CPU(unsigned int, current_word_idx); |
1294 | static DEFINE_PER_CPU(unsigned int, current_bit_idx); | |
245b2e70 | 1295 | |
ab7f863e SR |
1296 | /* |
1297 | * Mask out the i least significant bits of w | |
1298 | */ | |
c81611c4 | 1299 | #define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i)) |
245b2e70 | 1300 | |
e46cdb66 JF |
1301 | /* |
1302 | * Search the CPUs pending events bitmasks. For each one found, map | |
1303 | * the event number to an irq, and feed it into do_IRQ() for | |
1304 | * handling. | |
1305 | * | |
1306 | * Xen uses a two-level bitmap to speed searching. The first level is | |
1307 | * a bitset of words which contain pending event bits. The second | |
1308 | * level is a bitset of pending events themselves. | |
1309 | */ | |
38e20b07 | 1310 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 | 1311 | { |
24b51c2f | 1312 | int start_word_idx, start_bit_idx; |
ab7f863e | 1313 | int word_idx, bit_idx; |
24b51c2f | 1314 | int i; |
e46cdb66 JF |
1315 | int cpu = get_cpu(); |
1316 | struct shared_info *s = HYPERVISOR_shared_info; | |
780f36d8 | 1317 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
088c05a8 | 1318 | unsigned count; |
e46cdb66 | 1319 | |
229664be | 1320 | do { |
c81611c4 | 1321 | xen_ulong_t pending_words; |
e46cdb66 | 1322 | |
229664be | 1323 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1324 | |
b2e4ae69 | 1325 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1326 | goto out; |
e46cdb66 | 1327 | |
c81611c4 IC |
1328 | /* |
1329 | * Master flag must be cleared /before/ clearing | |
1330 | * selector flag. xchg_xen_ulong must contain an | |
1331 | * appropriate barrier. | |
1332 | */ | |
1333 | pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0); | |
ab7f863e | 1334 | |
24b51c2f KF |
1335 | start_word_idx = __this_cpu_read(current_word_idx); |
1336 | start_bit_idx = __this_cpu_read(current_bit_idx); | |
1337 | ||
1338 | word_idx = start_word_idx; | |
ab7f863e | 1339 | |
24b51c2f | 1340 | for (i = 0; pending_words != 0; i++) { |
c81611c4 IC |
1341 | xen_ulong_t pending_bits; |
1342 | xen_ulong_t words; | |
229664be | 1343 | |
ab7f863e SR |
1344 | words = MASK_LSBS(pending_words, word_idx); |
1345 | ||
1346 | /* | |
ada6814c | 1347 | * If we masked out all events, wrap to beginning. |
ab7f863e SR |
1348 | */ |
1349 | if (words == 0) { | |
ada6814c KF |
1350 | word_idx = 0; |
1351 | bit_idx = 0; | |
ab7f863e SR |
1352 | continue; |
1353 | } | |
c81611c4 | 1354 | word_idx = EVTCHN_FIRST_BIT(words); |
229664be | 1355 | |
24b51c2f KF |
1356 | pending_bits = active_evtchns(cpu, s, word_idx); |
1357 | bit_idx = 0; /* usually scan entire word from start */ | |
1358 | if (word_idx == start_word_idx) { | |
1359 | /* We scan the starting word in two parts */ | |
1360 | if (i == 0) | |
1361 | /* 1st time: start in the middle */ | |
1362 | bit_idx = start_bit_idx; | |
1363 | else | |
1364 | /* 2nd time: mask bits done already */ | |
1365 | bit_idx &= (1UL << start_bit_idx) - 1; | |
1366 | } | |
1367 | ||
ab7f863e | 1368 | do { |
c81611c4 | 1369 | xen_ulong_t bits; |
ab7f863e | 1370 | int port, irq; |
ca4dbc66 | 1371 | struct irq_desc *desc; |
229664be | 1372 | |
ab7f863e SR |
1373 | bits = MASK_LSBS(pending_bits, bit_idx); |
1374 | ||
1375 | /* If we masked out all events, move on. */ | |
ada6814c | 1376 | if (bits == 0) |
ab7f863e | 1377 | break; |
ab7f863e | 1378 | |
c81611c4 | 1379 | bit_idx = EVTCHN_FIRST_BIT(bits); |
ab7f863e SR |
1380 | |
1381 | /* Process port. */ | |
c81611c4 | 1382 | port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; |
ab7f863e SR |
1383 | irq = evtchn_to_irq[port]; |
1384 | ||
ca4dbc66 EB |
1385 | if (irq != -1) { |
1386 | desc = irq_to_desc(irq); | |
1387 | if (desc) | |
1388 | generic_handle_irq_desc(irq, desc); | |
1389 | } | |
ab7f863e | 1390 | |
c81611c4 | 1391 | bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; |
ada6814c KF |
1392 | |
1393 | /* Next caller starts at last processed + 1 */ | |
1394 | __this_cpu_write(current_word_idx, | |
1395 | bit_idx ? word_idx : | |
c81611c4 | 1396 | (word_idx+1) % BITS_PER_EVTCHN_WORD); |
ada6814c KF |
1397 | __this_cpu_write(current_bit_idx, bit_idx); |
1398 | } while (bit_idx != 0); | |
ab7f863e | 1399 | |
24b51c2f KF |
1400 | /* Scan start_l1i twice; all others once. */ |
1401 | if ((word_idx != start_word_idx) || (i != 0)) | |
ab7f863e | 1402 | pending_words &= ~(1UL << word_idx); |
ada6814c | 1403 | |
c81611c4 | 1404 | word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD; |
e46cdb66 | 1405 | } |
e46cdb66 | 1406 | |
229664be JF |
1407 | BUG_ON(!irqs_disabled()); |
1408 | ||
780f36d8 CL |
1409 | count = __this_cpu_read(xed_nesting_count); |
1410 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1411 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1412 | |
1413 | out: | |
38e20b07 SY |
1414 | |
1415 | put_cpu(); | |
1416 | } | |
1417 | ||
1418 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1419 | { | |
1420 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1421 | ||
772aebce | 1422 | irq_enter(); |
0ec53ecf | 1423 | #ifdef CONFIG_X86 |
38e20b07 | 1424 | exit_idle(); |
0ec53ecf | 1425 | #endif |
38e20b07 SY |
1426 | |
1427 | __xen_evtchn_do_upcall(); | |
1428 | ||
3445a8fd JF |
1429 | irq_exit(); |
1430 | set_irq_regs(old_regs); | |
38e20b07 | 1431 | } |
3445a8fd | 1432 | |
38e20b07 SY |
1433 | void xen_hvm_evtchn_do_upcall(void) |
1434 | { | |
1435 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1436 | } |
183d03cc | 1437 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1438 | |
eb1e305f JF |
1439 | /* Rebind a new event channel to an existing irq. */ |
1440 | void rebind_evtchn_irq(int evtchn, int irq) | |
1441 | { | |
d77bbd4d JF |
1442 | struct irq_info *info = info_for_irq(irq); |
1443 | ||
eb1e305f JF |
1444 | /* Make sure the irq is masked, since the new event channel |
1445 | will also be masked. */ | |
1446 | disable_irq(irq); | |
1447 | ||
77365948 | 1448 | mutex_lock(&irq_mapping_update_lock); |
eb1e305f JF |
1449 | |
1450 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1451 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1452 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1453 | so there should be a proper type */ |
1454 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1455 | |
9158c358 | 1456 | xen_irq_info_evtchn_init(irq, evtchn); |
eb1e305f | 1457 | |
77365948 | 1458 | mutex_unlock(&irq_mapping_update_lock); |
eb1e305f JF |
1459 | |
1460 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1461 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1462 | |
1463 | /* Unmask the event channel. */ | |
1464 | enable_irq(irq); | |
1465 | } | |
1466 | ||
e46cdb66 | 1467 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1468 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1469 | { |
1470 | struct evtchn_bind_vcpu bind_vcpu; | |
1471 | int evtchn = evtchn_from_irq(irq); | |
1472 | ||
be49472f IC |
1473 | if (!VALID_EVTCHN(evtchn)) |
1474 | return -1; | |
1475 | ||
1476 | /* | |
1477 | * Events delivered via platform PCI interrupts are always | |
1478 | * routed to vcpu 0 and hence cannot be rebound. | |
1479 | */ | |
1480 | if (xen_hvm_domain() && !xen_have_vector_callback) | |
d5dedd45 | 1481 | return -1; |
e46cdb66 JF |
1482 | |
1483 | /* Send future instances of this interrupt to other vcpu. */ | |
1484 | bind_vcpu.port = evtchn; | |
1485 | bind_vcpu.vcpu = tcpu; | |
1486 | ||
1487 | /* | |
1488 | * If this fails, it usually just indicates that we're dealing with a | |
1489 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1490 | * it, but don't do the xenlinux-level rebind in that case. | |
1491 | */ | |
1492 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1493 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1494 | |
d5dedd45 YL |
1495 | return 0; |
1496 | } | |
e46cdb66 | 1497 | |
c9e265e0 TG |
1498 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1499 | bool force) | |
e46cdb66 | 1500 | { |
0de26520 | 1501 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 | 1502 | |
c9e265e0 | 1503 | return rebind_irq_to_cpu(data->irq, tcpu); |
e46cdb66 JF |
1504 | } |
1505 | ||
642e0c88 IY |
1506 | int resend_irq_on_evtchn(unsigned int irq) |
1507 | { | |
1508 | int masked, evtchn = evtchn_from_irq(irq); | |
1509 | struct shared_info *s = HYPERVISOR_shared_info; | |
1510 | ||
1511 | if (!VALID_EVTCHN(evtchn)) | |
1512 | return 1; | |
1513 | ||
c81611c4 IC |
1514 | masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask)); |
1515 | sync_set_bit(evtchn, BM(s->evtchn_pending)); | |
642e0c88 IY |
1516 | if (!masked) |
1517 | unmask_evtchn(evtchn); | |
1518 | ||
1519 | return 1; | |
1520 | } | |
1521 | ||
c9e265e0 | 1522 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1523 | { |
c9e265e0 | 1524 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1525 | |
1526 | if (VALID_EVTCHN(evtchn)) | |
1527 | unmask_evtchn(evtchn); | |
1528 | } | |
1529 | ||
c9e265e0 | 1530 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1531 | { |
c9e265e0 | 1532 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1533 | |
1534 | if (VALID_EVTCHN(evtchn)) | |
1535 | mask_evtchn(evtchn); | |
1536 | } | |
1537 | ||
c9e265e0 | 1538 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1539 | { |
c9e265e0 | 1540 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1541 | |
7e186bdd | 1542 | irq_move_irq(data); |
e46cdb66 JF |
1543 | |
1544 | if (VALID_EVTCHN(evtchn)) | |
7e186bdd SS |
1545 | clear_evtchn(evtchn); |
1546 | } | |
1547 | ||
1548 | static void mask_ack_dynirq(struct irq_data *data) | |
1549 | { | |
1550 | disable_dynirq(data); | |
1551 | ack_dynirq(data); | |
e46cdb66 JF |
1552 | } |
1553 | ||
c9e265e0 | 1554 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1555 | { |
c9e265e0 | 1556 | int evtchn = evtchn_from_irq(data->irq); |
ee8fa1c6 | 1557 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1558 | int ret = 0; |
1559 | ||
1560 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1561 | int masked; |
1562 | ||
c81611c4 IC |
1563 | masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask)); |
1564 | sync_set_bit(evtchn, BM(sh->evtchn_pending)); | |
ee8fa1c6 JF |
1565 | if (!masked) |
1566 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1567 | ret = 1; |
1568 | } | |
1569 | ||
1570 | return ret; | |
1571 | } | |
1572 | ||
0a85226f | 1573 | static void restore_pirqs(void) |
9a069c33 SS |
1574 | { |
1575 | int pirq, rc, irq, gsi; | |
1576 | struct physdev_map_pirq map_irq; | |
69c358ce | 1577 | struct irq_info *info; |
9a069c33 | 1578 | |
69c358ce IC |
1579 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1580 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1581 | continue; |
1582 | ||
69c358ce IC |
1583 | pirq = info->u.pirq.pirq; |
1584 | gsi = info->u.pirq.gsi; | |
1585 | irq = info->irq; | |
1586 | ||
9a069c33 SS |
1587 | /* save/restore of PT devices doesn't work, so at this point the |
1588 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1589 | if (!gsi) |
1590 | continue; | |
1591 | ||
1592 | map_irq.domid = DOMID_SELF; | |
1593 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1594 | map_irq.index = gsi; | |
1595 | map_irq.pirq = pirq; | |
1596 | ||
1597 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1598 | if (rc) { | |
1599 | printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", | |
1600 | gsi, irq, pirq, rc); | |
9158c358 | 1601 | xen_free_irq(irq); |
9a069c33 SS |
1602 | continue; |
1603 | } | |
1604 | ||
1605 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1606 | ||
c9e265e0 | 1607 | __startup_pirq(irq); |
9a069c33 SS |
1608 | } |
1609 | } | |
1610 | ||
0e91398f JF |
1611 | static void restore_cpu_virqs(unsigned int cpu) |
1612 | { | |
1613 | struct evtchn_bind_virq bind_virq; | |
1614 | int virq, irq, evtchn; | |
1615 | ||
1616 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1617 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1618 | continue; | |
1619 | ||
ced40d0f | 1620 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1621 | |
1622 | /* Get a new binding from Xen. */ | |
1623 | bind_virq.virq = virq; | |
1624 | bind_virq.vcpu = cpu; | |
1625 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1626 | &bind_virq) != 0) | |
1627 | BUG(); | |
1628 | evtchn = bind_virq.port; | |
1629 | ||
1630 | /* Record the new mapping. */ | |
3d4cfa37 | 1631 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
0e91398f | 1632 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1633 | } |
1634 | } | |
1635 | ||
1636 | static void restore_cpu_ipis(unsigned int cpu) | |
1637 | { | |
1638 | struct evtchn_bind_ipi bind_ipi; | |
1639 | int ipi, irq, evtchn; | |
1640 | ||
1641 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1642 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1643 | continue; | |
1644 | ||
ced40d0f | 1645 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1646 | |
1647 | /* Get a new binding from Xen. */ | |
1648 | bind_ipi.vcpu = cpu; | |
1649 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1650 | &bind_ipi) != 0) | |
1651 | BUG(); | |
1652 | evtchn = bind_ipi.port; | |
1653 | ||
1654 | /* Record the new mapping. */ | |
3d4cfa37 | 1655 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
0e91398f | 1656 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1657 | } |
1658 | } | |
1659 | ||
2d9e1e2f JF |
1660 | /* Clear an irq's pending state, in preparation for polling on it */ |
1661 | void xen_clear_irq_pending(int irq) | |
1662 | { | |
1663 | int evtchn = evtchn_from_irq(irq); | |
1664 | ||
1665 | if (VALID_EVTCHN(evtchn)) | |
1666 | clear_evtchn(evtchn); | |
1667 | } | |
d9a8814f | 1668 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1669 | void xen_set_irq_pending(int irq) |
1670 | { | |
1671 | int evtchn = evtchn_from_irq(irq); | |
1672 | ||
1673 | if (VALID_EVTCHN(evtchn)) | |
1674 | set_evtchn(evtchn); | |
1675 | } | |
1676 | ||
1677 | bool xen_test_irq_pending(int irq) | |
1678 | { | |
1679 | int evtchn = evtchn_from_irq(irq); | |
1680 | bool ret = false; | |
1681 | ||
1682 | if (VALID_EVTCHN(evtchn)) | |
1683 | ret = test_evtchn(evtchn); | |
1684 | ||
1685 | return ret; | |
1686 | } | |
1687 | ||
d9a8814f KRW |
1688 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1689 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1690 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1691 | { |
1692 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1693 | ||
1694 | if (VALID_EVTCHN(evtchn)) { | |
1695 | struct sched_poll poll; | |
1696 | ||
1697 | poll.nr_ports = 1; | |
d9a8814f | 1698 | poll.timeout = timeout; |
ff3c5362 | 1699 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1700 | |
1701 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1702 | BUG(); | |
1703 | } | |
1704 | } | |
d9a8814f KRW |
1705 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1706 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1707 | * irq will be disabled so it won't deliver an interrupt. */ | |
1708 | void xen_poll_irq(int irq) | |
1709 | { | |
1710 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1711 | } | |
2d9e1e2f | 1712 | |
c7c2c3a2 KRW |
1713 | /* Check whether the IRQ line is shared with other guests. */ |
1714 | int xen_test_irq_shared(int irq) | |
1715 | { | |
1716 | struct irq_info *info = info_for_irq(irq); | |
1717 | struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq }; | |
1718 | ||
1719 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) | |
1720 | return 0; | |
1721 | return !(irq_status.flags & XENIRQSTAT_shared); | |
1722 | } | |
1723 | EXPORT_SYMBOL_GPL(xen_test_irq_shared); | |
1724 | ||
0e91398f JF |
1725 | void xen_irq_resume(void) |
1726 | { | |
6cb6537d IC |
1727 | unsigned int cpu, evtchn; |
1728 | struct irq_info *info; | |
0e91398f JF |
1729 | |
1730 | init_evtchn_cpu_bindings(); | |
1731 | ||
1732 | /* New event-channel space is not 'live' yet. */ | |
1733 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1734 | mask_evtchn(evtchn); | |
1735 | ||
1736 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1737 | list_for_each_entry(info, &xen_irq_list_head, list) |
1738 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f JF |
1739 | |
1740 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1741 | evtchn_to_irq[evtchn] = -1; | |
1742 | ||
1743 | for_each_possible_cpu(cpu) { | |
1744 | restore_cpu_virqs(cpu); | |
1745 | restore_cpu_ipis(cpu); | |
1746 | } | |
6903591f | 1747 | |
0a85226f | 1748 | restore_pirqs(); |
0e91398f JF |
1749 | } |
1750 | ||
e46cdb66 | 1751 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1752 | .name = "xen-dyn", |
54a353a0 | 1753 | |
c9e265e0 TG |
1754 | .irq_disable = disable_dynirq, |
1755 | .irq_mask = disable_dynirq, | |
1756 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1757 | |
7e186bdd SS |
1758 | .irq_ack = ack_dynirq, |
1759 | .irq_mask_ack = mask_ack_dynirq, | |
1760 | ||
c9e265e0 TG |
1761 | .irq_set_affinity = set_affinity_irq, |
1762 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1763 | }; |
1764 | ||
d46a78b0 | 1765 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1766 | .name = "xen-pirq", |
d46a78b0 | 1767 | |
c9e265e0 TG |
1768 | .irq_startup = startup_pirq, |
1769 | .irq_shutdown = shutdown_pirq, | |
c9e265e0 | 1770 | .irq_enable = enable_pirq, |
c9e265e0 | 1771 | .irq_disable = disable_pirq, |
d46a78b0 | 1772 | |
7e186bdd SS |
1773 | .irq_mask = disable_dynirq, |
1774 | .irq_unmask = enable_dynirq, | |
1775 | ||
1776 | .irq_ack = eoi_pirq, | |
1777 | .irq_eoi = eoi_pirq, | |
1778 | .irq_mask_ack = mask_ack_pirq, | |
d46a78b0 | 1779 | |
c9e265e0 | 1780 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1781 | |
c9e265e0 | 1782 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1783 | }; |
1784 | ||
aaca4964 | 1785 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1786 | .name = "xen-percpu", |
aaca4964 | 1787 | |
c9e265e0 TG |
1788 | .irq_disable = disable_dynirq, |
1789 | .irq_mask = disable_dynirq, | |
1790 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1791 | |
c9e265e0 | 1792 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1793 | }; |
1794 | ||
38e20b07 SY |
1795 | int xen_set_callback_via(uint64_t via) |
1796 | { | |
1797 | struct xen_hvm_param a; | |
1798 | a.domid = DOMID_SELF; | |
1799 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1800 | a.value = via; | |
1801 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1802 | } | |
1803 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1804 | ||
ca65f9fc | 1805 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1806 | /* Vector callbacks are better than PCI interrupts to receive event |
1807 | * channel notifications because we can receive vector callbacks on any | |
1808 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1809 | void xen_callback_vector(void) | |
1810 | { | |
1811 | int rc; | |
1812 | uint64_t callback_via; | |
1813 | if (xen_have_vector_callback) { | |
bc2b0331 | 1814 | callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR); |
38e20b07 SY |
1815 | rc = xen_set_callback_via(callback_via); |
1816 | if (rc) { | |
1817 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1818 | " failed.\n"); | |
1819 | xen_have_vector_callback = 0; | |
1820 | return; | |
1821 | } | |
1822 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1823 | "enabled\n"); | |
1824 | /* in the restore case the vector has already been allocated */ | |
bc2b0331 S |
1825 | if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) |
1826 | alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, | |
1827 | xen_hvm_callback_vector); | |
38e20b07 SY |
1828 | } |
1829 | } | |
ca65f9fc SS |
1830 | #else |
1831 | void xen_callback_vector(void) {} | |
1832 | #endif | |
38e20b07 | 1833 | |
2e3d8860 | 1834 | void __init xen_init_IRQ(void) |
e46cdb66 | 1835 | { |
0ec53ecf | 1836 | int i; |
c7a3589e | 1837 | |
b21ddbf5 JF |
1838 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1839 | GFP_KERNEL); | |
9d093e29 | 1840 | BUG_ON(!evtchn_to_irq); |
b21ddbf5 JF |
1841 | for (i = 0; i < NR_EVENT_CHANNELS; i++) |
1842 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1843 | |
1844 | init_evtchn_cpu_bindings(); | |
1845 | ||
1846 | /* No event channels are 'live' right now. */ | |
1847 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1848 | mask_evtchn(i); | |
1849 | ||
9846ff10 SS |
1850 | pirq_needs_eoi = pirq_needs_eoi_flag; |
1851 | ||
0ec53ecf | 1852 | #ifdef CONFIG_X86 |
38e20b07 SY |
1853 | if (xen_hvm_domain()) { |
1854 | xen_callback_vector(); | |
1855 | native_init_IRQ(); | |
3942b740 SS |
1856 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1857 | * __acpi_register_gsi can point at the right function */ | |
1858 | pci_xen_hvm_init(); | |
38e20b07 | 1859 | } else { |
0ec53ecf | 1860 | int rc; |
9846ff10 SS |
1861 | struct physdev_pirq_eoi_gmfn eoi_gmfn; |
1862 | ||
38e20b07 | 1863 | irq_ctx_init(smp_processor_id()); |
38aa66fc | 1864 | if (xen_initial_domain()) |
a0ee0567 | 1865 | pci_xen_initial_domain(); |
9846ff10 SS |
1866 | |
1867 | pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO); | |
1868 | eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map); | |
1869 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn); | |
1870 | if (rc != 0) { | |
1871 | free_page((unsigned long) pirq_eoi_map); | |
1872 | pirq_eoi_map = NULL; | |
1873 | } else | |
1874 | pirq_needs_eoi = pirq_check_eoi_map; | |
38e20b07 | 1875 | } |
0ec53ecf | 1876 | #endif |
e46cdb66 | 1877 | } |