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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
f731e3ef | 32 | #include <linux/pci.h> |
e46cdb66 | 33 | |
38e20b07 | 34 | #include <asm/desc.h> |
e46cdb66 JF |
35 | #include <asm/ptrace.h> |
36 | #include <asm/irq.h> | |
792dc4f6 | 37 | #include <asm/idle.h> |
0794bfc7 | 38 | #include <asm/io_apic.h> |
e46cdb66 | 39 | #include <asm/sync_bitops.h> |
42a1de56 | 40 | #include <asm/xen/pci.h> |
e46cdb66 | 41 | #include <asm/xen/hypercall.h> |
8d1b8753 | 42 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 43 | |
38e20b07 SY |
44 | #include <xen/xen.h> |
45 | #include <xen/hvm.h> | |
e04d0d07 | 46 | #include <xen/xen-ops.h> |
e46cdb66 JF |
47 | #include <xen/events.h> |
48 | #include <xen/interface/xen.h> | |
49 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
50 | #include <xen/interface/hvm/hvm_op.h> |
51 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 52 | |
e46cdb66 JF |
53 | /* |
54 | * This lock protects updates to the following mapping and reference-count | |
55 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
56 | */ | |
57 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
58 | ||
59 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 60 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 61 | |
f87e4cac | 62 | /* IRQ <-> IPI mapping */ |
204fba4a | 63 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 64 | |
ced40d0f JF |
65 | /* Interrupt types. */ |
66 | enum xen_irq_type { | |
d77bbd4d | 67 | IRQT_UNBOUND = 0, |
f87e4cac JF |
68 | IRQT_PIRQ, |
69 | IRQT_VIRQ, | |
70 | IRQT_IPI, | |
71 | IRQT_EVTCHN | |
72 | }; | |
e46cdb66 | 73 | |
ced40d0f JF |
74 | /* |
75 | * Packed IRQ information: | |
76 | * type - enum xen_irq_type | |
77 | * event channel - irq->event channel mapping | |
78 | * cpu - cpu this event channel is bound to | |
79 | * index - type-specific information: | |
42a1de56 SS |
80 | * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM |
81 | * guest, or GSI (real passthrough IRQ) of the device. | |
ced40d0f JF |
82 | * VIRQ - virq number |
83 | * IPI - IPI vector | |
84 | * EVTCHN - | |
85 | */ | |
86 | struct irq_info | |
87 | { | |
88 | enum xen_irq_type type; /* type */ | |
89 | unsigned short evtchn; /* event channel */ | |
90 | unsigned short cpu; /* cpu bound */ | |
91 | ||
92 | union { | |
93 | unsigned short virq; | |
94 | enum ipi_vector ipi; | |
95 | struct { | |
7a043f11 | 96 | unsigned short pirq; |
ced40d0f | 97 | unsigned short gsi; |
d46a78b0 JF |
98 | unsigned char vector; |
99 | unsigned char flags; | |
ced40d0f JF |
100 | } pirq; |
101 | } u; | |
102 | }; | |
d46a78b0 | 103 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 104 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 105 | |
b21ddbf5 | 106 | static struct irq_info *irq_info; |
7a043f11 | 107 | static int *pirq_to_irq; |
e46cdb66 | 108 | |
b21ddbf5 | 109 | static int *evtchn_to_irq; |
3b32f574 | 110 | |
cb60d114 IC |
111 | static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG], |
112 | cpu_evtchn_mask); | |
e46cdb66 | 113 | |
e46cdb66 JF |
114 | /* Xen will never allocate port zero for any purpose. */ |
115 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
116 | ||
e46cdb66 | 117 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 118 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 119 | static struct irq_chip xen_pirq_chip; |
e46cdb66 | 120 | |
9158c358 IC |
121 | /* Get info for IRQ */ |
122 | static struct irq_info *info_for_irq(unsigned irq) | |
ced40d0f | 123 | { |
9158c358 | 124 | return &irq_info[irq]; |
ced40d0f JF |
125 | } |
126 | ||
9158c358 IC |
127 | /* Constructors for packed IRQ information. */ |
128 | static void xen_irq_info_common_init(struct irq_info *info, | |
129 | enum xen_irq_type type, | |
130 | unsigned short evtchn, | |
131 | unsigned short cpu) | |
ced40d0f | 132 | { |
9158c358 IC |
133 | |
134 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
135 | ||
136 | info->type = type; | |
137 | info->evtchn = evtchn; | |
138 | info->cpu = cpu; | |
ced40d0f JF |
139 | } |
140 | ||
9158c358 IC |
141 | static void xen_irq_info_evtchn_init(unsigned irq, |
142 | unsigned short evtchn) | |
e46cdb66 | 143 | { |
9158c358 IC |
144 | struct irq_info *info = info_for_irq(irq); |
145 | ||
146 | xen_irq_info_common_init(info, IRQT_EVTCHN, evtchn, 0); | |
ced40d0f JF |
147 | } |
148 | ||
9158c358 IC |
149 | static void xen_irq_info_ipi_init(unsigned irq, |
150 | unsigned short evtchn, | |
151 | enum ipi_vector ipi) | |
ced40d0f | 152 | { |
9158c358 IC |
153 | struct irq_info *info = info_for_irq(irq); |
154 | ||
155 | xen_irq_info_common_init(info, IRQT_IPI, evtchn, 0); | |
156 | ||
157 | info->u.ipi = ipi; | |
ced40d0f JF |
158 | } |
159 | ||
9158c358 IC |
160 | static void xen_irq_info_virq_init(unsigned irq, |
161 | unsigned short evtchn, | |
162 | unsigned short virq) | |
ced40d0f | 163 | { |
9158c358 IC |
164 | struct irq_info *info = info_for_irq(irq); |
165 | ||
166 | xen_irq_info_common_init(info, IRQT_VIRQ, evtchn, 0); | |
167 | ||
168 | info->u.virq = virq; | |
e46cdb66 JF |
169 | } |
170 | ||
9158c358 IC |
171 | static void xen_irq_info_pirq_init(unsigned irq, |
172 | unsigned short evtchn, | |
173 | unsigned short pirq, | |
174 | unsigned short gsi, | |
175 | unsigned short vector, | |
176 | unsigned char flags) | |
e46cdb66 | 177 | { |
9158c358 IC |
178 | struct irq_info *info = info_for_irq(irq); |
179 | ||
180 | xen_irq_info_common_init(info, IRQT_PIRQ, evtchn, 0); | |
181 | ||
182 | info->u.pirq.pirq = pirq; | |
183 | info->u.pirq.gsi = gsi; | |
184 | info->u.pirq.vector = vector; | |
185 | info->u.pirq.flags = flags; | |
e46cdb66 JF |
186 | } |
187 | ||
9158c358 IC |
188 | /* |
189 | * Accessors for packed IRQ information. | |
190 | */ | |
ced40d0f | 191 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 192 | { |
110e7c7e JJ |
193 | if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
194 | return 0; | |
195 | ||
ced40d0f | 196 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
197 | } |
198 | ||
d4c04536 IC |
199 | unsigned irq_from_evtchn(unsigned int evtchn) |
200 | { | |
201 | return evtchn_to_irq[evtchn]; | |
202 | } | |
203 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
204 | ||
ced40d0f | 205 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 206 | { |
ced40d0f JF |
207 | struct irq_info *info = info_for_irq(irq); |
208 | ||
209 | BUG_ON(info == NULL); | |
210 | BUG_ON(info->type != IRQT_IPI); | |
211 | ||
212 | return info->u.ipi; | |
213 | } | |
214 | ||
215 | static unsigned virq_from_irq(unsigned irq) | |
216 | { | |
217 | struct irq_info *info = info_for_irq(irq); | |
218 | ||
219 | BUG_ON(info == NULL); | |
220 | BUG_ON(info->type != IRQT_VIRQ); | |
221 | ||
222 | return info->u.virq; | |
223 | } | |
224 | ||
7a043f11 SS |
225 | static unsigned pirq_from_irq(unsigned irq) |
226 | { | |
227 | struct irq_info *info = info_for_irq(irq); | |
228 | ||
229 | BUG_ON(info == NULL); | |
230 | BUG_ON(info->type != IRQT_PIRQ); | |
231 | ||
232 | return info->u.pirq.pirq; | |
233 | } | |
234 | ||
ced40d0f JF |
235 | static unsigned gsi_from_irq(unsigned irq) |
236 | { | |
237 | struct irq_info *info = info_for_irq(irq); | |
238 | ||
239 | BUG_ON(info == NULL); | |
240 | BUG_ON(info->type != IRQT_PIRQ); | |
241 | ||
242 | return info->u.pirq.gsi; | |
243 | } | |
244 | ||
ced40d0f JF |
245 | static enum xen_irq_type type_from_irq(unsigned irq) |
246 | { | |
247 | return info_for_irq(irq)->type; | |
248 | } | |
249 | ||
250 | static unsigned cpu_from_irq(unsigned irq) | |
251 | { | |
252 | return info_for_irq(irq)->cpu; | |
253 | } | |
254 | ||
255 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
256 | { | |
257 | int irq = evtchn_to_irq[evtchn]; | |
258 | unsigned ret = 0; | |
259 | ||
260 | if (irq != -1) | |
261 | ret = cpu_from_irq(irq); | |
262 | ||
263 | return ret; | |
e46cdb66 JF |
264 | } |
265 | ||
d46a78b0 JF |
266 | static bool pirq_needs_eoi(unsigned irq) |
267 | { | |
268 | struct irq_info *info = info_for_irq(irq); | |
269 | ||
270 | BUG_ON(info->type != IRQT_PIRQ); | |
271 | ||
272 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
273 | } | |
274 | ||
e46cdb66 JF |
275 | static inline unsigned long active_evtchns(unsigned int cpu, |
276 | struct shared_info *sh, | |
277 | unsigned int idx) | |
278 | { | |
279 | return (sh->evtchn_pending[idx] & | |
cb60d114 | 280 | per_cpu(cpu_evtchn_mask, cpu)[idx] & |
e46cdb66 JF |
281 | ~sh->evtchn_mask[idx]); |
282 | } | |
283 | ||
284 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
285 | { | |
286 | int irq = evtchn_to_irq[chn]; | |
287 | ||
288 | BUG_ON(irq == -1); | |
289 | #ifdef CONFIG_SMP | |
c9e265e0 | 290 | cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu)); |
e46cdb66 JF |
291 | #endif |
292 | ||
cb60d114 IC |
293 | clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))); |
294 | set_bit(chn, per_cpu(cpu_evtchn_mask, cpu)); | |
e46cdb66 | 295 | |
ced40d0f | 296 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
297 | } |
298 | ||
299 | static void init_evtchn_cpu_bindings(void) | |
300 | { | |
1c6969ec | 301 | int i; |
e46cdb66 | 302 | #ifdef CONFIG_SMP |
10e58084 | 303 | struct irq_desc *desc; |
10e58084 | 304 | |
e46cdb66 | 305 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 306 | for_each_irq_desc(i, desc) { |
c9e265e0 | 307 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); |
0b8f1efa | 308 | } |
e46cdb66 JF |
309 | #endif |
310 | ||
1c6969ec | 311 | for_each_possible_cpu(i) |
cb60d114 IC |
312 | memset(per_cpu(cpu_evtchn_mask, i), |
313 | (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i))); | |
1c6969ec | 314 | |
e46cdb66 JF |
315 | } |
316 | ||
e46cdb66 JF |
317 | static inline void clear_evtchn(int port) |
318 | { | |
319 | struct shared_info *s = HYPERVISOR_shared_info; | |
320 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
321 | } | |
322 | ||
323 | static inline void set_evtchn(int port) | |
324 | { | |
325 | struct shared_info *s = HYPERVISOR_shared_info; | |
326 | sync_set_bit(port, &s->evtchn_pending[0]); | |
327 | } | |
328 | ||
168d2f46 JF |
329 | static inline int test_evtchn(int port) |
330 | { | |
331 | struct shared_info *s = HYPERVISOR_shared_info; | |
332 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
333 | } | |
334 | ||
e46cdb66 JF |
335 | |
336 | /** | |
337 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
338 | * @irq: irq of event channel to send event to | |
339 | * | |
340 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
341 | * save/restore. Notifications on a broken connection are silently | |
342 | * dropped. | |
343 | */ | |
344 | void notify_remote_via_irq(int irq) | |
345 | { | |
346 | int evtchn = evtchn_from_irq(irq); | |
347 | ||
348 | if (VALID_EVTCHN(evtchn)) | |
349 | notify_remote_via_evtchn(evtchn); | |
350 | } | |
351 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
352 | ||
353 | static void mask_evtchn(int port) | |
354 | { | |
355 | struct shared_info *s = HYPERVISOR_shared_info; | |
356 | sync_set_bit(port, &s->evtchn_mask[0]); | |
357 | } | |
358 | ||
359 | static void unmask_evtchn(int port) | |
360 | { | |
361 | struct shared_info *s = HYPERVISOR_shared_info; | |
362 | unsigned int cpu = get_cpu(); | |
363 | ||
364 | BUG_ON(!irqs_disabled()); | |
365 | ||
366 | /* Slow path (hypercall) if this is a non-local port. */ | |
367 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
368 | struct evtchn_unmask unmask = { .port = port }; | |
369 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
370 | } else { | |
780f36d8 | 371 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
e46cdb66 JF |
372 | |
373 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
374 | ||
375 | /* | |
376 | * The following is basically the equivalent of | |
377 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
378 | * the interrupt edge' if the channel is masked. | |
379 | */ | |
380 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
381 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
382 | &vcpu_info->evtchn_pending_sel)) | |
383 | vcpu_info->evtchn_upcall_pending = 1; | |
384 | } | |
385 | ||
386 | put_cpu(); | |
387 | } | |
388 | ||
89911501 | 389 | static int xen_allocate_irq_dynamic(void) |
0794bfc7 | 390 | { |
89911501 IC |
391 | int first = 0; |
392 | int irq; | |
0794bfc7 KRW |
393 | |
394 | #ifdef CONFIG_X86_IO_APIC | |
89911501 IC |
395 | /* |
396 | * For an HVM guest or domain 0 which see "real" (emulated or | |
397 | * actual repectively) GSIs we allocate dynamic IRQs | |
398 | * e.g. those corresponding to event channels or MSIs | |
399 | * etc. from the range above those "real" GSIs to avoid | |
400 | * collisions. | |
401 | */ | |
402 | if (xen_initial_domain() || xen_hvm_domain()) | |
403 | first = get_nr_irqs_gsi(); | |
0794bfc7 KRW |
404 | #endif |
405 | ||
89911501 IC |
406 | retry: |
407 | irq = irq_alloc_desc_from(first, -1); | |
3a69e916 | 408 | |
89911501 IC |
409 | if (irq == -ENOMEM && first > NR_IRQS_LEGACY) { |
410 | printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n"); | |
411 | first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY); | |
412 | goto retry; | |
99ad198c | 413 | } |
e46cdb66 | 414 | |
89911501 IC |
415 | if (irq < 0) |
416 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
ced40d0f | 417 | |
e46cdb66 | 418 | return irq; |
d46a78b0 JF |
419 | } |
420 | ||
c9df1ce5 IC |
421 | static int xen_allocate_irq_gsi(unsigned gsi) |
422 | { | |
423 | int irq; | |
424 | ||
89911501 IC |
425 | /* |
426 | * A PV guest has no concept of a GSI (since it has no ACPI | |
427 | * nor access to/knowledge of the physical APICs). Therefore | |
428 | * all IRQs are dynamically allocated from the entire IRQ | |
429 | * space. | |
430 | */ | |
431 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
432 | return xen_allocate_irq_dynamic(); |
433 | ||
434 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
435 | if (gsi < NR_IRQS_LEGACY) | |
436 | return gsi; | |
437 | ||
438 | irq = irq_alloc_desc_at(gsi, -1); | |
439 | if (irq < 0) | |
440 | panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq); | |
441 | ||
442 | return irq; | |
443 | } | |
444 | ||
445 | static void xen_free_irq(unsigned irq) | |
446 | { | |
9158c358 IC |
447 | irq_info[irq].type = IRQT_UNBOUND; |
448 | ||
72146104 IC |
449 | /* Legacy IRQ descriptors are managed by the arch. */ |
450 | if (irq < NR_IRQS_LEGACY) | |
451 | return; | |
452 | ||
c9df1ce5 IC |
453 | irq_free_desc(irq); |
454 | } | |
455 | ||
d46a78b0 JF |
456 | static void pirq_unmask_notify(int irq) |
457 | { | |
7a043f11 | 458 | struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) }; |
d46a78b0 JF |
459 | |
460 | if (unlikely(pirq_needs_eoi(irq))) { | |
461 | int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
462 | WARN_ON(rc); | |
463 | } | |
464 | } | |
465 | ||
466 | static void pirq_query_unmask(int irq) | |
467 | { | |
468 | struct physdev_irq_status_query irq_status; | |
469 | struct irq_info *info = info_for_irq(irq); | |
470 | ||
471 | BUG_ON(info->type != IRQT_PIRQ); | |
472 | ||
7a043f11 | 473 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
474 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
475 | irq_status.flags = 0; | |
476 | ||
477 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
478 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
479 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
480 | } | |
481 | ||
482 | static bool probing_irq(int irq) | |
483 | { | |
484 | struct irq_desc *desc = irq_to_desc(irq); | |
485 | ||
486 | return desc && desc->action == NULL; | |
487 | } | |
488 | ||
c9e265e0 | 489 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
490 | { |
491 | struct evtchn_bind_pirq bind_pirq; | |
492 | struct irq_info *info = info_for_irq(irq); | |
493 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 494 | int rc; |
d46a78b0 JF |
495 | |
496 | BUG_ON(info->type != IRQT_PIRQ); | |
497 | ||
498 | if (VALID_EVTCHN(evtchn)) | |
499 | goto out; | |
500 | ||
7a043f11 | 501 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 502 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
503 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
504 | BIND_PIRQ__WILL_SHARE : 0; | |
505 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
506 | if (rc != 0) { | |
d46a78b0 JF |
507 | if (!probing_irq(irq)) |
508 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
509 | irq); | |
510 | return 0; | |
511 | } | |
512 | evtchn = bind_pirq.port; | |
513 | ||
514 | pirq_query_unmask(irq); | |
515 | ||
516 | evtchn_to_irq[evtchn] = irq; | |
517 | bind_evtchn_to_cpu(evtchn, 0); | |
518 | info->evtchn = evtchn; | |
519 | ||
520 | out: | |
521 | unmask_evtchn(evtchn); | |
522 | pirq_unmask_notify(irq); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
c9e265e0 TG |
527 | static unsigned int startup_pirq(struct irq_data *data) |
528 | { | |
529 | return __startup_pirq(data->irq); | |
530 | } | |
531 | ||
532 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 JF |
533 | { |
534 | struct evtchn_close close; | |
c9e265e0 | 535 | unsigned int irq = data->irq; |
d46a78b0 JF |
536 | struct irq_info *info = info_for_irq(irq); |
537 | int evtchn = evtchn_from_irq(irq); | |
538 | ||
539 | BUG_ON(info->type != IRQT_PIRQ); | |
540 | ||
541 | if (!VALID_EVTCHN(evtchn)) | |
542 | return; | |
543 | ||
544 | mask_evtchn(evtchn); | |
545 | ||
546 | close.port = evtchn; | |
547 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
548 | BUG(); | |
549 | ||
550 | bind_evtchn_to_cpu(evtchn, 0); | |
551 | evtchn_to_irq[evtchn] = -1; | |
552 | info->evtchn = 0; | |
553 | } | |
554 | ||
c9e265e0 | 555 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 556 | { |
c9e265e0 | 557 | startup_pirq(data); |
d46a78b0 JF |
558 | } |
559 | ||
c9e265e0 | 560 | static void disable_pirq(struct irq_data *data) |
d46a78b0 JF |
561 | { |
562 | } | |
563 | ||
c9e265e0 | 564 | static void ack_pirq(struct irq_data *data) |
d46a78b0 | 565 | { |
c9e265e0 | 566 | int evtchn = evtchn_from_irq(data->irq); |
d46a78b0 | 567 | |
aa673c1c | 568 | move_native_irq(data->irq); |
d46a78b0 JF |
569 | |
570 | if (VALID_EVTCHN(evtchn)) { | |
571 | mask_evtchn(evtchn); | |
572 | clear_evtchn(evtchn); | |
573 | } | |
574 | } | |
575 | ||
d46a78b0 JF |
576 | static int find_irq_by_gsi(unsigned gsi) |
577 | { | |
578 | int irq; | |
579 | ||
b21ddbf5 | 580 | for (irq = 0; irq < nr_irqs; irq++) { |
d46a78b0 JF |
581 | struct irq_info *info = info_for_irq(irq); |
582 | ||
583 | if (info == NULL || info->type != IRQT_PIRQ) | |
584 | continue; | |
585 | ||
586 | if (gsi_from_irq(irq) == gsi) | |
587 | return irq; | |
588 | } | |
589 | ||
590 | return -1; | |
591 | } | |
592 | ||
f4d0635b | 593 | int xen_allocate_pirq_gsi(unsigned gsi) |
7a043f11 | 594 | { |
f4d0635b | 595 | return gsi; |
7a043f11 SS |
596 | } |
597 | ||
653378ac IC |
598 | /* |
599 | * Do not make any assumptions regarding the relationship between the | |
600 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
601 | * |
602 | * Note: We don't assign an event channel until the irq actually started | |
603 | * up. Return an existing irq if we've already got one for the gsi. | |
d46a78b0 | 604 | */ |
f4d0635b IC |
605 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
606 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 607 | { |
a0e18116 | 608 | int irq = -1; |
d46a78b0 JF |
609 | struct physdev_irq irq_op; |
610 | ||
611 | spin_lock(&irq_mapping_update_lock); | |
612 | ||
e5fc7345 | 613 | if ((pirq > nr_irqs) || (gsi > nr_irqs)) { |
01557baf | 614 | printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n", |
e5fc7345 SS |
615 | pirq > nr_irqs ? "pirq" :"", |
616 | gsi > nr_irqs ? "gsi" : ""); | |
01557baf SS |
617 | goto out; |
618 | } | |
619 | ||
d46a78b0 JF |
620 | irq = find_irq_by_gsi(gsi); |
621 | if (irq != -1) { | |
7a043f11 | 622 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 JF |
623 | irq, gsi); |
624 | goto out; /* XXX need refcount? */ | |
625 | } | |
626 | ||
c9df1ce5 | 627 | irq = xen_allocate_irq_gsi(gsi); |
d46a78b0 JF |
628 | |
629 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
1a60d05f | 630 | handle_level_irq, name); |
d46a78b0 JF |
631 | |
632 | irq_op.irq = irq; | |
b5401a96 AN |
633 | irq_op.vector = 0; |
634 | ||
635 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
636 | * driver provides a PCI bus that does the call to do exactly | |
637 | * this in the priv domain. */ | |
638 | if (xen_initial_domain() && | |
639 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 640 | xen_free_irq(irq); |
d46a78b0 JF |
641 | irq = -ENOSPC; |
642 | goto out; | |
643 | } | |
644 | ||
9158c358 IC |
645 | xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, |
646 | shareable ? PIRQ_SHAREABLE : 0); | |
7a043f11 | 647 | pirq_to_irq[pirq] = irq; |
d46a78b0 JF |
648 | |
649 | out: | |
650 | spin_unlock(&irq_mapping_update_lock); | |
651 | ||
652 | return irq; | |
653 | } | |
654 | ||
f731e3ef | 655 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 656 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 657 | { |
5cad61a6 | 658 | int rc; |
cbf6aa89 | 659 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 660 | |
bf480d95 | 661 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 662 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 663 | |
5cad61a6 IC |
664 | WARN_ONCE(rc == -ENOSYS, |
665 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
666 | ||
667 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
668 | } |
669 | ||
bf480d95 | 670 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
ca1d8fe9 | 671 | int pirq, int vector, const char *name) |
809f9267 | 672 | { |
bf480d95 | 673 | int irq, ret; |
4b41df7f | 674 | |
809f9267 SS |
675 | spin_lock(&irq_mapping_update_lock); |
676 | ||
4b41df7f IC |
677 | irq = xen_allocate_irq_dynamic(); |
678 | if (irq == -1) | |
bb5d079a | 679 | goto out; |
809f9267 | 680 | |
4b41df7f | 681 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, |
809f9267 SS |
682 | handle_level_irq, name); |
683 | ||
9158c358 | 684 | xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0); |
bf480d95 IC |
685 | pirq_to_irq[pirq] = irq; |
686 | ret = set_irq_msi(irq, msidesc); | |
687 | if (ret < 0) | |
688 | goto error_irq; | |
809f9267 SS |
689 | out: |
690 | spin_unlock(&irq_mapping_update_lock); | |
4b41df7f | 691 | return irq; |
bf480d95 IC |
692 | error_irq: |
693 | spin_unlock(&irq_mapping_update_lock); | |
694 | xen_free_irq(irq); | |
695 | return -1; | |
809f9267 | 696 | } |
f731e3ef QH |
697 | #endif |
698 | ||
b5401a96 AN |
699 | int xen_destroy_irq(int irq) |
700 | { | |
701 | struct irq_desc *desc; | |
38aa66fc JF |
702 | struct physdev_unmap_pirq unmap_irq; |
703 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
704 | int rc = -ENOENT; |
705 | ||
706 | spin_lock(&irq_mapping_update_lock); | |
707 | ||
708 | desc = irq_to_desc(irq); | |
709 | if (!desc) | |
710 | goto out; | |
711 | ||
38aa66fc | 712 | if (xen_initial_domain()) { |
12334715 | 713 | unmap_irq.pirq = info->u.pirq.pirq; |
38aa66fc JF |
714 | unmap_irq.domid = DOMID_SELF; |
715 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); | |
716 | if (rc) { | |
717 | printk(KERN_WARNING "unmap irq failed %d\n", rc); | |
718 | goto out; | |
719 | } | |
720 | } | |
1aa0b51a KRW |
721 | pirq_to_irq[info->u.pirq.pirq] = -1; |
722 | ||
c9df1ce5 | 723 | xen_free_irq(irq); |
b5401a96 AN |
724 | |
725 | out: | |
726 | spin_unlock(&irq_mapping_update_lock); | |
727 | return rc; | |
728 | } | |
729 | ||
af42b8d1 SS |
730 | int xen_irq_from_pirq(unsigned pirq) |
731 | { | |
732 | return pirq_to_irq[pirq]; | |
733 | } | |
734 | ||
b536b4b9 | 735 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
736 | { |
737 | int irq; | |
738 | ||
739 | spin_lock(&irq_mapping_update_lock); | |
740 | ||
741 | irq = evtchn_to_irq[evtchn]; | |
742 | ||
743 | if (irq == -1) { | |
c9df1ce5 | 744 | irq = xen_allocate_irq_dynamic(); |
e46cdb66 | 745 | |
e46cdb66 | 746 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
3588fe2e | 747 | handle_fasteoi_irq, "event"); |
e46cdb66 JF |
748 | |
749 | evtchn_to_irq[evtchn] = irq; | |
9158c358 | 750 | xen_irq_info_evtchn_init(irq, evtchn); |
e46cdb66 JF |
751 | } |
752 | ||
e46cdb66 JF |
753 | spin_unlock(&irq_mapping_update_lock); |
754 | ||
755 | return irq; | |
756 | } | |
b536b4b9 | 757 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 758 | |
f87e4cac JF |
759 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
760 | { | |
761 | struct evtchn_bind_ipi bind_ipi; | |
762 | int evtchn, irq; | |
763 | ||
764 | spin_lock(&irq_mapping_update_lock); | |
765 | ||
766 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 767 | |
f87e4cac | 768 | if (irq == -1) { |
c9df1ce5 | 769 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
770 | if (irq < 0) |
771 | goto out; | |
772 | ||
aaca4964 JF |
773 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
774 | handle_percpu_irq, "ipi"); | |
f87e4cac JF |
775 | |
776 | bind_ipi.vcpu = cpu; | |
777 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
778 | &bind_ipi) != 0) | |
779 | BUG(); | |
780 | evtchn = bind_ipi.port; | |
781 | ||
782 | evtchn_to_irq[evtchn] = irq; | |
9158c358 | 783 | xen_irq_info_ipi_init(irq, evtchn, ipi); |
f87e4cac JF |
784 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
785 | ||
786 | bind_evtchn_to_cpu(evtchn, cpu); | |
787 | } | |
788 | ||
f87e4cac JF |
789 | out: |
790 | spin_unlock(&irq_mapping_update_lock); | |
791 | return irq; | |
792 | } | |
793 | ||
794 | ||
4fe7d5a7 | 795 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
796 | { |
797 | struct evtchn_bind_virq bind_virq; | |
798 | int evtchn, irq; | |
799 | ||
800 | spin_lock(&irq_mapping_update_lock); | |
801 | ||
802 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
803 | ||
804 | if (irq == -1) { | |
c9df1ce5 | 805 | irq = xen_allocate_irq_dynamic(); |
a52521f1 JF |
806 | |
807 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, | |
808 | handle_percpu_irq, "virq"); | |
809 | ||
e46cdb66 JF |
810 | bind_virq.virq = virq; |
811 | bind_virq.vcpu = cpu; | |
812 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
813 | &bind_virq) != 0) | |
814 | BUG(); | |
815 | evtchn = bind_virq.port; | |
816 | ||
e46cdb66 | 817 | evtchn_to_irq[evtchn] = irq; |
9158c358 | 818 | xen_irq_info_virq_init(irq, evtchn, virq); |
e46cdb66 JF |
819 | |
820 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
821 | ||
822 | bind_evtchn_to_cpu(evtchn, cpu); | |
823 | } | |
824 | ||
e46cdb66 JF |
825 | spin_unlock(&irq_mapping_update_lock); |
826 | ||
827 | return irq; | |
828 | } | |
829 | ||
830 | static void unbind_from_irq(unsigned int irq) | |
831 | { | |
832 | struct evtchn_close close; | |
833 | int evtchn = evtchn_from_irq(irq); | |
834 | ||
835 | spin_lock(&irq_mapping_update_lock); | |
836 | ||
d77bbd4d | 837 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
838 | close.port = evtchn; |
839 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
840 | BUG(); | |
841 | ||
842 | switch (type_from_irq(irq)) { | |
843 | case IRQT_VIRQ: | |
844 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 845 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 846 | break; |
d68d82af AN |
847 | case IRQT_IPI: |
848 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 849 | [ipi_from_irq(irq)] = -1; |
d68d82af | 850 | break; |
e46cdb66 JF |
851 | default: |
852 | break; | |
853 | } | |
854 | ||
855 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
856 | bind_evtchn_to_cpu(evtchn, 0); | |
857 | ||
858 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
859 | } |
860 | ||
9158c358 | 861 | BUG_ON(irq_info[irq].type == IRQT_UNBOUND); |
e46cdb66 | 862 | |
9158c358 | 863 | xen_free_irq(irq); |
e46cdb66 JF |
864 | |
865 | spin_unlock(&irq_mapping_update_lock); | |
866 | } | |
867 | ||
868 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 869 | irq_handler_t handler, |
e46cdb66 JF |
870 | unsigned long irqflags, |
871 | const char *devname, void *dev_id) | |
872 | { | |
873 | unsigned int irq; | |
874 | int retval; | |
875 | ||
876 | irq = bind_evtchn_to_irq(evtchn); | |
877 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
878 | if (retval != 0) { | |
879 | unbind_from_irq(irq); | |
880 | return retval; | |
881 | } | |
882 | ||
883 | return irq; | |
884 | } | |
885 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
886 | ||
887 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 888 | irq_handler_t handler, |
e46cdb66 JF |
889 | unsigned long irqflags, const char *devname, void *dev_id) |
890 | { | |
891 | unsigned int irq; | |
892 | int retval; | |
893 | ||
894 | irq = bind_virq_to_irq(virq, cpu); | |
895 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
896 | if (retval != 0) { | |
897 | unbind_from_irq(irq); | |
898 | return retval; | |
899 | } | |
900 | ||
901 | return irq; | |
902 | } | |
903 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
904 | ||
f87e4cac JF |
905 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
906 | unsigned int cpu, | |
907 | irq_handler_t handler, | |
908 | unsigned long irqflags, | |
909 | const char *devname, | |
910 | void *dev_id) | |
911 | { | |
912 | int irq, retval; | |
913 | ||
914 | irq = bind_ipi_to_irq(ipi, cpu); | |
915 | if (irq < 0) | |
916 | return irq; | |
917 | ||
676dc3cf | 918 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME; |
f87e4cac JF |
919 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
920 | if (retval != 0) { | |
921 | unbind_from_irq(irq); | |
922 | return retval; | |
923 | } | |
924 | ||
925 | return irq; | |
926 | } | |
927 | ||
e46cdb66 JF |
928 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
929 | { | |
930 | free_irq(irq, dev_id); | |
931 | unbind_from_irq(irq); | |
932 | } | |
933 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
934 | ||
f87e4cac JF |
935 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
936 | { | |
937 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
938 | BUG_ON(irq < 0); | |
939 | notify_remote_via_irq(irq); | |
940 | } | |
941 | ||
ee523ca1 JF |
942 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
943 | { | |
944 | struct shared_info *sh = HYPERVISOR_shared_info; | |
945 | int cpu = smp_processor_id(); | |
cb60d114 | 946 | unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu); |
ee523ca1 JF |
947 | int i; |
948 | unsigned long flags; | |
949 | static DEFINE_SPINLOCK(debug_lock); | |
cb52e6d9 | 950 | struct vcpu_info *v; |
ee523ca1 JF |
951 | |
952 | spin_lock_irqsave(&debug_lock, flags); | |
953 | ||
cb52e6d9 | 954 | printk("\nvcpu %d\n ", cpu); |
ee523ca1 JF |
955 | |
956 | for_each_online_cpu(i) { | |
cb52e6d9 IC |
957 | int pending; |
958 | v = per_cpu(xen_vcpu, i); | |
959 | pending = (get_irq_regs() && i == cpu) | |
960 | ? xen_irqs_disabled(get_irq_regs()) | |
961 | : v->evtchn_upcall_mask; | |
962 | printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i, | |
963 | pending, v->evtchn_upcall_pending, | |
964 | (int)(sizeof(v->evtchn_pending_sel)*2), | |
965 | v->evtchn_pending_sel); | |
966 | } | |
967 | v = per_cpu(xen_vcpu, cpu); | |
968 | ||
969 | printk("\npending:\n "); | |
970 | for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
971 | printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2, | |
972 | sh->evtchn_pending[i], | |
973 | i % 8 == 0 ? "\n " : " "); | |
974 | printk("\nglobal mask:\n "); | |
975 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
976 | printk("%0*lx%s", | |
977 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
978 | sh->evtchn_mask[i], | |
979 | i % 8 == 0 ? "\n " : " "); | |
980 | ||
981 | printk("\nglobally unmasked:\n "); | |
982 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
983 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
984 | sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
985 | i % 8 == 0 ? "\n " : " "); | |
986 | ||
987 | printk("\nlocal cpu%d mask:\n ", cpu); | |
988 | for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--) | |
989 | printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2), | |
990 | cpu_evtchn[i], | |
991 | i % 8 == 0 ? "\n " : " "); | |
992 | ||
993 | printk("\nlocally unmasked:\n "); | |
994 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) { | |
995 | unsigned long pending = sh->evtchn_pending[i] | |
996 | & ~sh->evtchn_mask[i] | |
997 | & cpu_evtchn[i]; | |
998 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
999 | pending, i % 8 == 0 ? "\n " : " "); | |
ee523ca1 | 1000 | } |
ee523ca1 JF |
1001 | |
1002 | printk("\npending list:\n"); | |
cb52e6d9 | 1003 | for (i = 0; i < NR_EVENT_CHANNELS; i++) { |
ee523ca1 | 1004 | if (sync_test_bit(i, sh->evtchn_pending)) { |
cb52e6d9 IC |
1005 | int word_idx = i / BITS_PER_LONG; |
1006 | printk(" %d: event %d -> irq %d%s%s%s\n", | |
ced40d0f | 1007 | cpu_from_evtchn(i), i, |
cb52e6d9 IC |
1008 | evtchn_to_irq[i], |
1009 | sync_test_bit(word_idx, &v->evtchn_pending_sel) | |
1010 | ? "" : " l2-clear", | |
1011 | !sync_test_bit(i, sh->evtchn_mask) | |
1012 | ? "" : " globally-masked", | |
1013 | sync_test_bit(i, cpu_evtchn) | |
1014 | ? "" : " locally-masked"); | |
ee523ca1 JF |
1015 | } |
1016 | } | |
1017 | ||
1018 | spin_unlock_irqrestore(&debug_lock, flags); | |
1019 | ||
1020 | return IRQ_HANDLED; | |
1021 | } | |
1022 | ||
245b2e70 TH |
1023 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1024 | ||
e46cdb66 JF |
1025 | /* |
1026 | * Search the CPUs pending events bitmasks. For each one found, map | |
1027 | * the event number to an irq, and feed it into do_IRQ() for | |
1028 | * handling. | |
1029 | * | |
1030 | * Xen uses a two-level bitmap to speed searching. The first level is | |
1031 | * a bitset of words which contain pending event bits. The second | |
1032 | * level is a bitset of pending events themselves. | |
1033 | */ | |
38e20b07 | 1034 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
1035 | { |
1036 | int cpu = get_cpu(); | |
1037 | struct shared_info *s = HYPERVISOR_shared_info; | |
780f36d8 | 1038 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
229664be | 1039 | unsigned count; |
e46cdb66 | 1040 | |
229664be JF |
1041 | do { |
1042 | unsigned long pending_words; | |
e46cdb66 | 1043 | |
229664be | 1044 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1045 | |
b2e4ae69 | 1046 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1047 | goto out; |
e46cdb66 | 1048 | |
e849c3e9 IY |
1049 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
1050 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 1051 | wmb(); |
e849c3e9 | 1052 | #endif |
229664be JF |
1053 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
1054 | while (pending_words != 0) { | |
1055 | unsigned long pending_bits; | |
1056 | int word_idx = __ffs(pending_words); | |
1057 | pending_words &= ~(1UL << word_idx); | |
1058 | ||
1059 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
1060 | int bit_idx = __ffs(pending_bits); | |
1061 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
1062 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 1063 | struct irq_desc *desc; |
229664be | 1064 | |
3588fe2e JF |
1065 | mask_evtchn(port); |
1066 | clear_evtchn(port); | |
1067 | ||
ca4dbc66 EB |
1068 | if (irq != -1) { |
1069 | desc = irq_to_desc(irq); | |
1070 | if (desc) | |
1071 | generic_handle_irq_desc(irq, desc); | |
1072 | } | |
e46cdb66 JF |
1073 | } |
1074 | } | |
e46cdb66 | 1075 | |
229664be JF |
1076 | BUG_ON(!irqs_disabled()); |
1077 | ||
780f36d8 CL |
1078 | count = __this_cpu_read(xed_nesting_count); |
1079 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1080 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1081 | |
1082 | out: | |
38e20b07 SY |
1083 | |
1084 | put_cpu(); | |
1085 | } | |
1086 | ||
1087 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1088 | { | |
1089 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1090 | ||
1091 | exit_idle(); | |
1092 | irq_enter(); | |
1093 | ||
1094 | __xen_evtchn_do_upcall(); | |
1095 | ||
3445a8fd JF |
1096 | irq_exit(); |
1097 | set_irq_regs(old_regs); | |
38e20b07 | 1098 | } |
3445a8fd | 1099 | |
38e20b07 SY |
1100 | void xen_hvm_evtchn_do_upcall(void) |
1101 | { | |
1102 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1103 | } |
183d03cc | 1104 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1105 | |
eb1e305f JF |
1106 | /* Rebind a new event channel to an existing irq. */ |
1107 | void rebind_evtchn_irq(int evtchn, int irq) | |
1108 | { | |
d77bbd4d JF |
1109 | struct irq_info *info = info_for_irq(irq); |
1110 | ||
eb1e305f JF |
1111 | /* Make sure the irq is masked, since the new event channel |
1112 | will also be masked. */ | |
1113 | disable_irq(irq); | |
1114 | ||
1115 | spin_lock(&irq_mapping_update_lock); | |
1116 | ||
1117 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1118 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1119 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1120 | so there should be a proper type */ |
1121 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
1122 | |
1123 | evtchn_to_irq[evtchn] = irq; | |
9158c358 | 1124 | xen_irq_info_evtchn_init(irq, evtchn); |
eb1e305f JF |
1125 | |
1126 | spin_unlock(&irq_mapping_update_lock); | |
1127 | ||
1128 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1129 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1130 | |
1131 | /* Unmask the event channel. */ | |
1132 | enable_irq(irq); | |
1133 | } | |
1134 | ||
e46cdb66 | 1135 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1136 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1137 | { |
1138 | struct evtchn_bind_vcpu bind_vcpu; | |
1139 | int evtchn = evtchn_from_irq(irq); | |
1140 | ||
be49472f IC |
1141 | if (!VALID_EVTCHN(evtchn)) |
1142 | return -1; | |
1143 | ||
1144 | /* | |
1145 | * Events delivered via platform PCI interrupts are always | |
1146 | * routed to vcpu 0 and hence cannot be rebound. | |
1147 | */ | |
1148 | if (xen_hvm_domain() && !xen_have_vector_callback) | |
d5dedd45 | 1149 | return -1; |
e46cdb66 JF |
1150 | |
1151 | /* Send future instances of this interrupt to other vcpu. */ | |
1152 | bind_vcpu.port = evtchn; | |
1153 | bind_vcpu.vcpu = tcpu; | |
1154 | ||
1155 | /* | |
1156 | * If this fails, it usually just indicates that we're dealing with a | |
1157 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1158 | * it, but don't do the xenlinux-level rebind in that case. | |
1159 | */ | |
1160 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1161 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1162 | |
d5dedd45 YL |
1163 | return 0; |
1164 | } | |
e46cdb66 | 1165 | |
c9e265e0 TG |
1166 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1167 | bool force) | |
e46cdb66 | 1168 | { |
0de26520 | 1169 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 | 1170 | |
c9e265e0 | 1171 | return rebind_irq_to_cpu(data->irq, tcpu); |
e46cdb66 JF |
1172 | } |
1173 | ||
642e0c88 IY |
1174 | int resend_irq_on_evtchn(unsigned int irq) |
1175 | { | |
1176 | int masked, evtchn = evtchn_from_irq(irq); | |
1177 | struct shared_info *s = HYPERVISOR_shared_info; | |
1178 | ||
1179 | if (!VALID_EVTCHN(evtchn)) | |
1180 | return 1; | |
1181 | ||
1182 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1183 | sync_set_bit(evtchn, s->evtchn_pending); | |
1184 | if (!masked) | |
1185 | unmask_evtchn(evtchn); | |
1186 | ||
1187 | return 1; | |
1188 | } | |
1189 | ||
c9e265e0 | 1190 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1191 | { |
c9e265e0 | 1192 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1193 | |
1194 | if (VALID_EVTCHN(evtchn)) | |
1195 | unmask_evtchn(evtchn); | |
1196 | } | |
1197 | ||
c9e265e0 | 1198 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1199 | { |
c9e265e0 | 1200 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1201 | |
1202 | if (VALID_EVTCHN(evtchn)) | |
1203 | mask_evtchn(evtchn); | |
1204 | } | |
1205 | ||
c9e265e0 | 1206 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1207 | { |
c9e265e0 | 1208 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1209 | |
c9e265e0 | 1210 | move_masked_irq(data->irq); |
e46cdb66 JF |
1211 | |
1212 | if (VALID_EVTCHN(evtchn)) | |
3588fe2e | 1213 | unmask_evtchn(evtchn); |
e46cdb66 JF |
1214 | } |
1215 | ||
c9e265e0 | 1216 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1217 | { |
c9e265e0 | 1218 | int evtchn = evtchn_from_irq(data->irq); |
ee8fa1c6 | 1219 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1220 | int ret = 0; |
1221 | ||
1222 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1223 | int masked; |
1224 | ||
1225 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1226 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1227 | if (!masked) | |
1228 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1229 | ret = 1; |
1230 | } | |
1231 | ||
1232 | return ret; | |
1233 | } | |
1234 | ||
0a85226f | 1235 | static void restore_pirqs(void) |
9a069c33 SS |
1236 | { |
1237 | int pirq, rc, irq, gsi; | |
1238 | struct physdev_map_pirq map_irq; | |
1239 | ||
1240 | for (pirq = 0; pirq < nr_irqs; pirq++) { | |
1241 | irq = pirq_to_irq[pirq]; | |
1242 | if (irq == -1) | |
1243 | continue; | |
1244 | ||
1245 | /* save/restore of PT devices doesn't work, so at this point the | |
1246 | * only devices present are GSI based emulated devices */ | |
1247 | gsi = gsi_from_irq(irq); | |
1248 | if (!gsi) | |
1249 | continue; | |
1250 | ||
1251 | map_irq.domid = DOMID_SELF; | |
1252 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1253 | map_irq.index = gsi; | |
1254 | map_irq.pirq = pirq; | |
1255 | ||
1256 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1257 | if (rc) { | |
1258 | printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", | |
1259 | gsi, irq, pirq, rc); | |
9158c358 | 1260 | xen_free_irq(irq); |
9a069c33 SS |
1261 | pirq_to_irq[pirq] = -1; |
1262 | continue; | |
1263 | } | |
1264 | ||
1265 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1266 | ||
c9e265e0 | 1267 | __startup_pirq(irq); |
9a069c33 SS |
1268 | } |
1269 | } | |
1270 | ||
0e91398f JF |
1271 | static void restore_cpu_virqs(unsigned int cpu) |
1272 | { | |
1273 | struct evtchn_bind_virq bind_virq; | |
1274 | int virq, irq, evtchn; | |
1275 | ||
1276 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1277 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1278 | continue; | |
1279 | ||
ced40d0f | 1280 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1281 | |
1282 | /* Get a new binding from Xen. */ | |
1283 | bind_virq.virq = virq; | |
1284 | bind_virq.vcpu = cpu; | |
1285 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1286 | &bind_virq) != 0) | |
1287 | BUG(); | |
1288 | evtchn = bind_virq.port; | |
1289 | ||
1290 | /* Record the new mapping. */ | |
1291 | evtchn_to_irq[evtchn] = irq; | |
9158c358 | 1292 | xen_irq_info_virq_init(irq, evtchn, virq); |
0e91398f | 1293 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1294 | } |
1295 | } | |
1296 | ||
1297 | static void restore_cpu_ipis(unsigned int cpu) | |
1298 | { | |
1299 | struct evtchn_bind_ipi bind_ipi; | |
1300 | int ipi, irq, evtchn; | |
1301 | ||
1302 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1303 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1304 | continue; | |
1305 | ||
ced40d0f | 1306 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1307 | |
1308 | /* Get a new binding from Xen. */ | |
1309 | bind_ipi.vcpu = cpu; | |
1310 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1311 | &bind_ipi) != 0) | |
1312 | BUG(); | |
1313 | evtchn = bind_ipi.port; | |
1314 | ||
1315 | /* Record the new mapping. */ | |
1316 | evtchn_to_irq[evtchn] = irq; | |
9158c358 | 1317 | xen_irq_info_ipi_init(irq, evtchn, ipi); |
0e91398f | 1318 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1319 | } |
1320 | } | |
1321 | ||
2d9e1e2f JF |
1322 | /* Clear an irq's pending state, in preparation for polling on it */ |
1323 | void xen_clear_irq_pending(int irq) | |
1324 | { | |
1325 | int evtchn = evtchn_from_irq(irq); | |
1326 | ||
1327 | if (VALID_EVTCHN(evtchn)) | |
1328 | clear_evtchn(evtchn); | |
1329 | } | |
d9a8814f | 1330 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1331 | void xen_set_irq_pending(int irq) |
1332 | { | |
1333 | int evtchn = evtchn_from_irq(irq); | |
1334 | ||
1335 | if (VALID_EVTCHN(evtchn)) | |
1336 | set_evtchn(evtchn); | |
1337 | } | |
1338 | ||
1339 | bool xen_test_irq_pending(int irq) | |
1340 | { | |
1341 | int evtchn = evtchn_from_irq(irq); | |
1342 | bool ret = false; | |
1343 | ||
1344 | if (VALID_EVTCHN(evtchn)) | |
1345 | ret = test_evtchn(evtchn); | |
1346 | ||
1347 | return ret; | |
1348 | } | |
1349 | ||
d9a8814f KRW |
1350 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1351 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1352 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1353 | { |
1354 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1355 | ||
1356 | if (VALID_EVTCHN(evtchn)) { | |
1357 | struct sched_poll poll; | |
1358 | ||
1359 | poll.nr_ports = 1; | |
d9a8814f | 1360 | poll.timeout = timeout; |
ff3c5362 | 1361 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1362 | |
1363 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1364 | BUG(); | |
1365 | } | |
1366 | } | |
d9a8814f KRW |
1367 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1368 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1369 | * irq will be disabled so it won't deliver an interrupt. */ | |
1370 | void xen_poll_irq(int irq) | |
1371 | { | |
1372 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1373 | } | |
2d9e1e2f | 1374 | |
0e91398f JF |
1375 | void xen_irq_resume(void) |
1376 | { | |
1377 | unsigned int cpu, irq, evtchn; | |
1378 | ||
1379 | init_evtchn_cpu_bindings(); | |
1380 | ||
1381 | /* New event-channel space is not 'live' yet. */ | |
1382 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1383 | mask_evtchn(evtchn); | |
1384 | ||
1385 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 1386 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
1387 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
1388 | ||
1389 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1390 | evtchn_to_irq[evtchn] = -1; | |
1391 | ||
1392 | for_each_possible_cpu(cpu) { | |
1393 | restore_cpu_virqs(cpu); | |
1394 | restore_cpu_ipis(cpu); | |
1395 | } | |
6903591f | 1396 | |
0a85226f | 1397 | restore_pirqs(); |
0e91398f JF |
1398 | } |
1399 | ||
e46cdb66 | 1400 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1401 | .name = "xen-dyn", |
54a353a0 | 1402 | |
c9e265e0 TG |
1403 | .irq_disable = disable_dynirq, |
1404 | .irq_mask = disable_dynirq, | |
1405 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1406 | |
c9e265e0 TG |
1407 | .irq_eoi = ack_dynirq, |
1408 | .irq_set_affinity = set_affinity_irq, | |
1409 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1410 | }; |
1411 | ||
d46a78b0 | 1412 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1413 | .name = "xen-pirq", |
d46a78b0 | 1414 | |
c9e265e0 TG |
1415 | .irq_startup = startup_pirq, |
1416 | .irq_shutdown = shutdown_pirq, | |
d46a78b0 | 1417 | |
c9e265e0 TG |
1418 | .irq_enable = enable_pirq, |
1419 | .irq_unmask = enable_pirq, | |
d46a78b0 | 1420 | |
c9e265e0 TG |
1421 | .irq_disable = disable_pirq, |
1422 | .irq_mask = disable_pirq, | |
d46a78b0 | 1423 | |
c9e265e0 | 1424 | .irq_ack = ack_pirq, |
d46a78b0 | 1425 | |
c9e265e0 | 1426 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1427 | |
c9e265e0 | 1428 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1429 | }; |
1430 | ||
aaca4964 | 1431 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1432 | .name = "xen-percpu", |
aaca4964 | 1433 | |
c9e265e0 TG |
1434 | .irq_disable = disable_dynirq, |
1435 | .irq_mask = disable_dynirq, | |
1436 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1437 | |
c9e265e0 | 1438 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1439 | }; |
1440 | ||
38e20b07 SY |
1441 | int xen_set_callback_via(uint64_t via) |
1442 | { | |
1443 | struct xen_hvm_param a; | |
1444 | a.domid = DOMID_SELF; | |
1445 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1446 | a.value = via; | |
1447 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1448 | } | |
1449 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1450 | ||
ca65f9fc | 1451 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1452 | /* Vector callbacks are better than PCI interrupts to receive event |
1453 | * channel notifications because we can receive vector callbacks on any | |
1454 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1455 | void xen_callback_vector(void) | |
1456 | { | |
1457 | int rc; | |
1458 | uint64_t callback_via; | |
1459 | if (xen_have_vector_callback) { | |
1460 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1461 | rc = xen_set_callback_via(callback_via); | |
1462 | if (rc) { | |
1463 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1464 | " failed.\n"); | |
1465 | xen_have_vector_callback = 0; | |
1466 | return; | |
1467 | } | |
1468 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1469 | "enabled\n"); | |
1470 | /* in the restore case the vector has already been allocated */ | |
1471 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1472 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1473 | } | |
1474 | } | |
ca65f9fc SS |
1475 | #else |
1476 | void xen_callback_vector(void) {} | |
1477 | #endif | |
38e20b07 | 1478 | |
e46cdb66 JF |
1479 | void __init xen_init_IRQ(void) |
1480 | { | |
e5fc7345 | 1481 | int i; |
c7a3589e | 1482 | |
b21ddbf5 JF |
1483 | irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL); |
1484 | ||
e5fc7345 SS |
1485 | /* We are using nr_irqs as the maximum number of pirq available but |
1486 | * that number is actually chosen by Xen and we don't know exactly | |
1487 | * what it is. Be careful choosing high pirq numbers. */ | |
1488 | pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL); | |
1489 | for (i = 0; i < nr_irqs; i++) | |
7a043f11 SS |
1490 | pirq_to_irq[i] = -1; |
1491 | ||
b21ddbf5 JF |
1492 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1493 | GFP_KERNEL); | |
1494 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1495 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1496 | |
1497 | init_evtchn_cpu_bindings(); | |
1498 | ||
1499 | /* No event channels are 'live' right now. */ | |
1500 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1501 | mask_evtchn(i); | |
1502 | ||
38e20b07 SY |
1503 | if (xen_hvm_domain()) { |
1504 | xen_callback_vector(); | |
1505 | native_init_IRQ(); | |
3942b740 SS |
1506 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1507 | * __acpi_register_gsi can point at the right function */ | |
1508 | pci_xen_hvm_init(); | |
38e20b07 SY |
1509 | } else { |
1510 | irq_ctx_init(smp_processor_id()); | |
38aa66fc JF |
1511 | if (xen_initial_domain()) |
1512 | xen_setup_pirqs(); | |
38e20b07 | 1513 | } |
e46cdb66 | 1514 | } |