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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
19 | * 4. Hardware interrupts. Not supported at present. | |
20 | * | |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
29 | ||
30 | #include <asm/ptrace.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/sync_bitops.h> | |
33 | #include <asm/xen/hypercall.h> | |
8d1b8753 | 34 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 35 | |
e04d0d07 | 36 | #include <xen/xen-ops.h> |
e46cdb66 JF |
37 | #include <xen/events.h> |
38 | #include <xen/interface/xen.h> | |
39 | #include <xen/interface/event_channel.h> | |
40 | ||
e46cdb66 JF |
41 | /* |
42 | * This lock protects updates to the following mapping and reference-count | |
43 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
44 | */ | |
45 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
46 | ||
47 | /* IRQ <-> VIRQ mapping. */ | |
48 | static DEFINE_PER_CPU(int, virq_to_irq[NR_VIRQS]) = {[0 ... NR_VIRQS-1] = -1}; | |
49 | ||
f87e4cac JF |
50 | /* IRQ <-> IPI mapping */ |
51 | static DEFINE_PER_CPU(int, ipi_to_irq[XEN_NR_IPIS]) = {[0 ... XEN_NR_IPIS-1] = -1}; | |
52 | ||
e46cdb66 JF |
53 | /* Packed IRQ information: binding type, sub-type index, and event channel. */ |
54 | struct packed_irq | |
55 | { | |
56 | unsigned short evtchn; | |
57 | unsigned char index; | |
58 | unsigned char type; | |
59 | }; | |
60 | ||
61 | static struct packed_irq irq_info[NR_IRQS]; | |
62 | ||
63 | /* Binding types. */ | |
f87e4cac JF |
64 | enum { |
65 | IRQT_UNBOUND, | |
66 | IRQT_PIRQ, | |
67 | IRQT_VIRQ, | |
68 | IRQT_IPI, | |
69 | IRQT_EVTCHN | |
70 | }; | |
e46cdb66 JF |
71 | |
72 | /* Convenient shorthand for packed representation of an unbound IRQ. */ | |
73 | #define IRQ_UNBOUND mk_irq_info(IRQT_UNBOUND, 0, 0) | |
74 | ||
75 | static int evtchn_to_irq[NR_EVENT_CHANNELS] = { | |
76 | [0 ... NR_EVENT_CHANNELS-1] = -1 | |
77 | }; | |
c7a3589e MT |
78 | struct cpu_evtchn_s { |
79 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
80 | }; | |
81 | static struct cpu_evtchn_s *cpu_evtchn_mask_p; | |
82 | static inline unsigned long *cpu_evtchn_mask(int cpu) | |
83 | { | |
84 | return cpu_evtchn_mask_p[cpu].bits; | |
85 | } | |
e46cdb66 JF |
86 | static u8 cpu_evtchn[NR_EVENT_CHANNELS]; |
87 | ||
88 | /* Reference counts for bindings to IRQs. */ | |
89 | static int irq_bindcount[NR_IRQS]; | |
90 | ||
91 | /* Xen will never allocate port zero for any purpose. */ | |
92 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
93 | ||
e46cdb66 JF |
94 | static struct irq_chip xen_dynamic_chip; |
95 | ||
96 | /* Constructor for packed IRQ information. */ | |
97 | static inline struct packed_irq mk_irq_info(u32 type, u32 index, u32 evtchn) | |
98 | { | |
99 | return (struct packed_irq) { evtchn, index, type }; | |
100 | } | |
101 | ||
102 | /* | |
103 | * Accessors for packed IRQ information. | |
104 | */ | |
105 | static inline unsigned int evtchn_from_irq(int irq) | |
106 | { | |
107 | return irq_info[irq].evtchn; | |
108 | } | |
109 | ||
110 | static inline unsigned int index_from_irq(int irq) | |
111 | { | |
112 | return irq_info[irq].index; | |
113 | } | |
114 | ||
115 | static inline unsigned int type_from_irq(int irq) | |
116 | { | |
117 | return irq_info[irq].type; | |
118 | } | |
119 | ||
120 | static inline unsigned long active_evtchns(unsigned int cpu, | |
121 | struct shared_info *sh, | |
122 | unsigned int idx) | |
123 | { | |
124 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 125 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
126 | ~sh->evtchn_mask[idx]); |
127 | } | |
128 | ||
129 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
130 | { | |
131 | int irq = evtchn_to_irq[chn]; | |
132 | ||
133 | BUG_ON(irq == -1); | |
134 | #ifdef CONFIG_SMP | |
7f7ace0c | 135 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
136 | #endif |
137 | ||
c7a3589e MT |
138 | __clear_bit(chn, cpu_evtchn_mask(cpu_evtchn[chn])); |
139 | __set_bit(chn, cpu_evtchn_mask(cpu)); | |
e46cdb66 JF |
140 | |
141 | cpu_evtchn[chn] = cpu; | |
142 | } | |
143 | ||
144 | static void init_evtchn_cpu_bindings(void) | |
145 | { | |
146 | #ifdef CONFIG_SMP | |
10e58084 | 147 | struct irq_desc *desc; |
e46cdb66 | 148 | int i; |
10e58084 | 149 | |
e46cdb66 | 150 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 151 | for_each_irq_desc(i, desc) { |
7f7ace0c | 152 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 153 | } |
e46cdb66 JF |
154 | #endif |
155 | ||
156 | memset(cpu_evtchn, 0, sizeof(cpu_evtchn)); | |
c7a3589e | 157 | memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0))); |
e46cdb66 JF |
158 | } |
159 | ||
160 | static inline unsigned int cpu_from_evtchn(unsigned int evtchn) | |
161 | { | |
162 | return cpu_evtchn[evtchn]; | |
163 | } | |
164 | ||
165 | static inline void clear_evtchn(int port) | |
166 | { | |
167 | struct shared_info *s = HYPERVISOR_shared_info; | |
168 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
169 | } | |
170 | ||
171 | static inline void set_evtchn(int port) | |
172 | { | |
173 | struct shared_info *s = HYPERVISOR_shared_info; | |
174 | sync_set_bit(port, &s->evtchn_pending[0]); | |
175 | } | |
176 | ||
168d2f46 JF |
177 | static inline int test_evtchn(int port) |
178 | { | |
179 | struct shared_info *s = HYPERVISOR_shared_info; | |
180 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
181 | } | |
182 | ||
e46cdb66 JF |
183 | |
184 | /** | |
185 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
186 | * @irq: irq of event channel to send event to | |
187 | * | |
188 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
189 | * save/restore. Notifications on a broken connection are silently | |
190 | * dropped. | |
191 | */ | |
192 | void notify_remote_via_irq(int irq) | |
193 | { | |
194 | int evtchn = evtchn_from_irq(irq); | |
195 | ||
196 | if (VALID_EVTCHN(evtchn)) | |
197 | notify_remote_via_evtchn(evtchn); | |
198 | } | |
199 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
200 | ||
201 | static void mask_evtchn(int port) | |
202 | { | |
203 | struct shared_info *s = HYPERVISOR_shared_info; | |
204 | sync_set_bit(port, &s->evtchn_mask[0]); | |
205 | } | |
206 | ||
207 | static void unmask_evtchn(int port) | |
208 | { | |
209 | struct shared_info *s = HYPERVISOR_shared_info; | |
210 | unsigned int cpu = get_cpu(); | |
211 | ||
212 | BUG_ON(!irqs_disabled()); | |
213 | ||
214 | /* Slow path (hypercall) if this is a non-local port. */ | |
215 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
216 | struct evtchn_unmask unmask = { .port = port }; | |
217 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
218 | } else { | |
219 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
220 | ||
221 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
222 | ||
223 | /* | |
224 | * The following is basically the equivalent of | |
225 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
226 | * the interrupt edge' if the channel is masked. | |
227 | */ | |
228 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
229 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
230 | &vcpu_info->evtchn_pending_sel)) | |
231 | vcpu_info->evtchn_upcall_pending = 1; | |
232 | } | |
233 | ||
234 | put_cpu(); | |
235 | } | |
236 | ||
237 | static int find_unbound_irq(void) | |
238 | { | |
239 | int irq; | |
6f8a0ed4 | 240 | struct irq_desc *desc; |
e46cdb66 JF |
241 | |
242 | /* Only allocate from dynirq range */ | |
0b8f1efa | 243 | for (irq = 0; irq < nr_irqs; irq++) |
e46cdb66 JF |
244 | if (irq_bindcount[irq] == 0) |
245 | break; | |
246 | ||
5a15d7e8 YL |
247 | if (irq == nr_irqs) |
248 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 | 249 | |
6f8a0ed4 JF |
250 | desc = irq_to_desc_alloc_cpu(irq, 0); |
251 | if (WARN_ON(desc == NULL)) | |
252 | return -1; | |
253 | ||
e46cdb66 JF |
254 | return irq; |
255 | } | |
256 | ||
b536b4b9 | 257 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
258 | { |
259 | int irq; | |
260 | ||
261 | spin_lock(&irq_mapping_update_lock); | |
262 | ||
263 | irq = evtchn_to_irq[evtchn]; | |
264 | ||
265 | if (irq == -1) { | |
266 | irq = find_unbound_irq(); | |
267 | ||
268 | dynamic_irq_init(irq); | |
269 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, | |
270 | handle_level_irq, "event"); | |
271 | ||
272 | evtchn_to_irq[evtchn] = irq; | |
273 | irq_info[irq] = mk_irq_info(IRQT_EVTCHN, 0, evtchn); | |
274 | } | |
275 | ||
276 | irq_bindcount[irq]++; | |
277 | ||
278 | spin_unlock(&irq_mapping_update_lock); | |
279 | ||
280 | return irq; | |
281 | } | |
b536b4b9 | 282 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 283 | |
f87e4cac JF |
284 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
285 | { | |
286 | struct evtchn_bind_ipi bind_ipi; | |
287 | int evtchn, irq; | |
288 | ||
289 | spin_lock(&irq_mapping_update_lock); | |
290 | ||
291 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
292 | if (irq == -1) { | |
293 | irq = find_unbound_irq(); | |
294 | if (irq < 0) | |
295 | goto out; | |
296 | ||
297 | dynamic_irq_init(irq); | |
298 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, | |
299 | handle_level_irq, "ipi"); | |
300 | ||
301 | bind_ipi.vcpu = cpu; | |
302 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
303 | &bind_ipi) != 0) | |
304 | BUG(); | |
305 | evtchn = bind_ipi.port; | |
306 | ||
307 | evtchn_to_irq[evtchn] = irq; | |
308 | irq_info[irq] = mk_irq_info(IRQT_IPI, ipi, evtchn); | |
309 | ||
310 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
311 | ||
312 | bind_evtchn_to_cpu(evtchn, cpu); | |
313 | } | |
314 | ||
315 | irq_bindcount[irq]++; | |
316 | ||
317 | out: | |
318 | spin_unlock(&irq_mapping_update_lock); | |
319 | return irq; | |
320 | } | |
321 | ||
322 | ||
e46cdb66 JF |
323 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
324 | { | |
325 | struct evtchn_bind_virq bind_virq; | |
326 | int evtchn, irq; | |
327 | ||
328 | spin_lock(&irq_mapping_update_lock); | |
329 | ||
330 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
331 | ||
332 | if (irq == -1) { | |
333 | bind_virq.virq = virq; | |
334 | bind_virq.vcpu = cpu; | |
335 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
336 | &bind_virq) != 0) | |
337 | BUG(); | |
338 | evtchn = bind_virq.port; | |
339 | ||
340 | irq = find_unbound_irq(); | |
341 | ||
342 | dynamic_irq_init(irq); | |
343 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, | |
344 | handle_level_irq, "virq"); | |
345 | ||
346 | evtchn_to_irq[evtchn] = irq; | |
347 | irq_info[irq] = mk_irq_info(IRQT_VIRQ, virq, evtchn); | |
348 | ||
349 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
350 | ||
351 | bind_evtchn_to_cpu(evtchn, cpu); | |
352 | } | |
353 | ||
354 | irq_bindcount[irq]++; | |
355 | ||
356 | spin_unlock(&irq_mapping_update_lock); | |
357 | ||
358 | return irq; | |
359 | } | |
360 | ||
361 | static void unbind_from_irq(unsigned int irq) | |
362 | { | |
363 | struct evtchn_close close; | |
364 | int evtchn = evtchn_from_irq(irq); | |
365 | ||
366 | spin_lock(&irq_mapping_update_lock); | |
367 | ||
0f2287ad | 368 | if ((--irq_bindcount[irq] == 0) && VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
369 | close.port = evtchn; |
370 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
371 | BUG(); | |
372 | ||
373 | switch (type_from_irq(irq)) { | |
374 | case IRQT_VIRQ: | |
375 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
376 | [index_from_irq(irq)] = -1; | |
377 | break; | |
d68d82af AN |
378 | case IRQT_IPI: |
379 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
380 | [index_from_irq(irq)] = -1; | |
381 | break; | |
e46cdb66 JF |
382 | default: |
383 | break; | |
384 | } | |
385 | ||
386 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
387 | bind_evtchn_to_cpu(evtchn, 0); | |
388 | ||
389 | evtchn_to_irq[evtchn] = -1; | |
390 | irq_info[irq] = IRQ_UNBOUND; | |
391 | ||
0f2287ad | 392 | dynamic_irq_cleanup(irq); |
e46cdb66 JF |
393 | } |
394 | ||
395 | spin_unlock(&irq_mapping_update_lock); | |
396 | } | |
397 | ||
398 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 399 | irq_handler_t handler, |
e46cdb66 JF |
400 | unsigned long irqflags, |
401 | const char *devname, void *dev_id) | |
402 | { | |
403 | unsigned int irq; | |
404 | int retval; | |
405 | ||
406 | irq = bind_evtchn_to_irq(evtchn); | |
407 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
408 | if (retval != 0) { | |
409 | unbind_from_irq(irq); | |
410 | return retval; | |
411 | } | |
412 | ||
413 | return irq; | |
414 | } | |
415 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
416 | ||
417 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 418 | irq_handler_t handler, |
e46cdb66 JF |
419 | unsigned long irqflags, const char *devname, void *dev_id) |
420 | { | |
421 | unsigned int irq; | |
422 | int retval; | |
423 | ||
424 | irq = bind_virq_to_irq(virq, cpu); | |
425 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
426 | if (retval != 0) { | |
427 | unbind_from_irq(irq); | |
428 | return retval; | |
429 | } | |
430 | ||
431 | return irq; | |
432 | } | |
433 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
434 | ||
f87e4cac JF |
435 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
436 | unsigned int cpu, | |
437 | irq_handler_t handler, | |
438 | unsigned long irqflags, | |
439 | const char *devname, | |
440 | void *dev_id) | |
441 | { | |
442 | int irq, retval; | |
443 | ||
444 | irq = bind_ipi_to_irq(ipi, cpu); | |
445 | if (irq < 0) | |
446 | return irq; | |
447 | ||
448 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
449 | if (retval != 0) { | |
450 | unbind_from_irq(irq); | |
451 | return retval; | |
452 | } | |
453 | ||
454 | return irq; | |
455 | } | |
456 | ||
e46cdb66 JF |
457 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
458 | { | |
459 | free_irq(irq, dev_id); | |
460 | unbind_from_irq(irq); | |
461 | } | |
462 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
463 | ||
f87e4cac JF |
464 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
465 | { | |
466 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
467 | BUG_ON(irq < 0); | |
468 | notify_remote_via_irq(irq); | |
469 | } | |
470 | ||
ee523ca1 JF |
471 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
472 | { | |
473 | struct shared_info *sh = HYPERVISOR_shared_info; | |
474 | int cpu = smp_processor_id(); | |
475 | int i; | |
476 | unsigned long flags; | |
477 | static DEFINE_SPINLOCK(debug_lock); | |
478 | ||
479 | spin_lock_irqsave(&debug_lock, flags); | |
480 | ||
481 | printk("vcpu %d\n ", cpu); | |
482 | ||
483 | for_each_online_cpu(i) { | |
484 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
485 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 486 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
487 | v->evtchn_upcall_pending, |
488 | v->evtchn_pending_sel); | |
489 | } | |
490 | printk("pending:\n "); | |
491 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
492 | printk("%08lx%s", sh->evtchn_pending[i], | |
493 | i % 8 == 0 ? "\n " : " "); | |
494 | printk("\nmasks:\n "); | |
495 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
496 | printk("%08lx%s", sh->evtchn_mask[i], | |
497 | i % 8 == 0 ? "\n " : " "); | |
498 | ||
499 | printk("\nunmasked:\n "); | |
500 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
501 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
502 | i % 8 == 0 ? "\n " : " "); | |
503 | ||
504 | printk("\npending list:\n"); | |
505 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
506 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
507 | printk(" %d: event %d -> irq %d\n", | |
508 | cpu_evtchn[i], i, | |
509 | evtchn_to_irq[i]); | |
510 | } | |
511 | } | |
512 | ||
513 | spin_unlock_irqrestore(&debug_lock, flags); | |
514 | ||
515 | return IRQ_HANDLED; | |
516 | } | |
517 | ||
f87e4cac | 518 | |
e46cdb66 JF |
519 | /* |
520 | * Search the CPUs pending events bitmasks. For each one found, map | |
521 | * the event number to an irq, and feed it into do_IRQ() for | |
522 | * handling. | |
523 | * | |
524 | * Xen uses a two-level bitmap to speed searching. The first level is | |
525 | * a bitset of words which contain pending event bits. The second | |
526 | * level is a bitset of pending events themselves. | |
527 | */ | |
75604d7f | 528 | void xen_evtchn_do_upcall(struct pt_regs *regs) |
e46cdb66 JF |
529 | { |
530 | int cpu = get_cpu(); | |
531 | struct shared_info *s = HYPERVISOR_shared_info; | |
532 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be JF |
533 | static DEFINE_PER_CPU(unsigned, nesting_count); |
534 | unsigned count; | |
e46cdb66 | 535 | |
229664be JF |
536 | do { |
537 | unsigned long pending_words; | |
e46cdb66 | 538 | |
229664be | 539 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 540 | |
229664be JF |
541 | if (__get_cpu_var(nesting_count)++) |
542 | goto out; | |
e46cdb66 | 543 | |
e849c3e9 IY |
544 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
545 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 546 | wmb(); |
e849c3e9 | 547 | #endif |
229664be JF |
548 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
549 | while (pending_words != 0) { | |
550 | unsigned long pending_bits; | |
551 | int word_idx = __ffs(pending_words); | |
552 | pending_words &= ~(1UL << word_idx); | |
553 | ||
554 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
555 | int bit_idx = __ffs(pending_bits); | |
556 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
557 | int irq = evtchn_to_irq[port]; | |
558 | ||
e849c3e9 IY |
559 | if (irq != -1) |
560 | xen_do_IRQ(irq, regs); | |
e46cdb66 JF |
561 | } |
562 | } | |
e46cdb66 | 563 | |
229664be JF |
564 | BUG_ON(!irqs_disabled()); |
565 | ||
566 | count = __get_cpu_var(nesting_count); | |
567 | __get_cpu_var(nesting_count) = 0; | |
568 | } while(count != 1); | |
569 | ||
570 | out: | |
e46cdb66 JF |
571 | put_cpu(); |
572 | } | |
573 | ||
eb1e305f JF |
574 | /* Rebind a new event channel to an existing irq. */ |
575 | void rebind_evtchn_irq(int evtchn, int irq) | |
576 | { | |
577 | /* Make sure the irq is masked, since the new event channel | |
578 | will also be masked. */ | |
579 | disable_irq(irq); | |
580 | ||
581 | spin_lock(&irq_mapping_update_lock); | |
582 | ||
583 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
584 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
585 | /* Expect irq to have been bound before, | |
586 | so the bindcount should be non-0 */ | |
587 | BUG_ON(irq_bindcount[irq] == 0); | |
588 | ||
589 | evtchn_to_irq[evtchn] = irq; | |
590 | irq_info[irq] = mk_irq_info(IRQT_EVTCHN, 0, evtchn); | |
591 | ||
592 | spin_unlock(&irq_mapping_update_lock); | |
593 | ||
594 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 595 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
596 | |
597 | /* Unmask the event channel. */ | |
598 | enable_irq(irq); | |
599 | } | |
600 | ||
e46cdb66 JF |
601 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
602 | static void rebind_irq_to_cpu(unsigned irq, unsigned tcpu) | |
603 | { | |
604 | struct evtchn_bind_vcpu bind_vcpu; | |
605 | int evtchn = evtchn_from_irq(irq); | |
606 | ||
607 | if (!VALID_EVTCHN(evtchn)) | |
608 | return; | |
609 | ||
610 | /* Send future instances of this interrupt to other vcpu. */ | |
611 | bind_vcpu.port = evtchn; | |
612 | bind_vcpu.vcpu = tcpu; | |
613 | ||
614 | /* | |
615 | * If this fails, it usually just indicates that we're dealing with a | |
616 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
617 | * it, but don't do the xenlinux-level rebind in that case. | |
618 | */ | |
619 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
620 | bind_evtchn_to_cpu(evtchn, tcpu); | |
621 | } | |
622 | ||
623 | ||
0de26520 | 624 | static void set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 625 | { |
0de26520 | 626 | unsigned tcpu = cpumask_first(dest); |
e46cdb66 JF |
627 | rebind_irq_to_cpu(irq, tcpu); |
628 | } | |
629 | ||
642e0c88 IY |
630 | int resend_irq_on_evtchn(unsigned int irq) |
631 | { | |
632 | int masked, evtchn = evtchn_from_irq(irq); | |
633 | struct shared_info *s = HYPERVISOR_shared_info; | |
634 | ||
635 | if (!VALID_EVTCHN(evtchn)) | |
636 | return 1; | |
637 | ||
638 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
639 | sync_set_bit(evtchn, s->evtchn_pending); | |
640 | if (!masked) | |
641 | unmask_evtchn(evtchn); | |
642 | ||
643 | return 1; | |
644 | } | |
645 | ||
e46cdb66 JF |
646 | static void enable_dynirq(unsigned int irq) |
647 | { | |
648 | int evtchn = evtchn_from_irq(irq); | |
649 | ||
650 | if (VALID_EVTCHN(evtchn)) | |
651 | unmask_evtchn(evtchn); | |
652 | } | |
653 | ||
654 | static void disable_dynirq(unsigned int irq) | |
655 | { | |
656 | int evtchn = evtchn_from_irq(irq); | |
657 | ||
658 | if (VALID_EVTCHN(evtchn)) | |
659 | mask_evtchn(evtchn); | |
660 | } | |
661 | ||
662 | static void ack_dynirq(unsigned int irq) | |
663 | { | |
664 | int evtchn = evtchn_from_irq(irq); | |
665 | ||
666 | move_native_irq(irq); | |
667 | ||
668 | if (VALID_EVTCHN(evtchn)) | |
669 | clear_evtchn(evtchn); | |
670 | } | |
671 | ||
672 | static int retrigger_dynirq(unsigned int irq) | |
673 | { | |
674 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 675 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
676 | int ret = 0; |
677 | ||
678 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
679 | int masked; |
680 | ||
681 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
682 | sync_set_bit(evtchn, sh->evtchn_pending); | |
683 | if (!masked) | |
684 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
685 | ret = 1; |
686 | } | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
0e91398f JF |
691 | static void restore_cpu_virqs(unsigned int cpu) |
692 | { | |
693 | struct evtchn_bind_virq bind_virq; | |
694 | int virq, irq, evtchn; | |
695 | ||
696 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
697 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
698 | continue; | |
699 | ||
700 | BUG_ON(irq_info[irq].type != IRQT_VIRQ); | |
701 | BUG_ON(irq_info[irq].index != virq); | |
702 | ||
703 | /* Get a new binding from Xen. */ | |
704 | bind_virq.virq = virq; | |
705 | bind_virq.vcpu = cpu; | |
706 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
707 | &bind_virq) != 0) | |
708 | BUG(); | |
709 | evtchn = bind_virq.port; | |
710 | ||
711 | /* Record the new mapping. */ | |
712 | evtchn_to_irq[evtchn] = irq; | |
713 | irq_info[irq] = mk_irq_info(IRQT_VIRQ, virq, evtchn); | |
714 | bind_evtchn_to_cpu(evtchn, cpu); | |
715 | ||
716 | /* Ready for use. */ | |
717 | unmask_evtchn(evtchn); | |
718 | } | |
719 | } | |
720 | ||
721 | static void restore_cpu_ipis(unsigned int cpu) | |
722 | { | |
723 | struct evtchn_bind_ipi bind_ipi; | |
724 | int ipi, irq, evtchn; | |
725 | ||
726 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
727 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
728 | continue; | |
729 | ||
730 | BUG_ON(irq_info[irq].type != IRQT_IPI); | |
731 | BUG_ON(irq_info[irq].index != ipi); | |
732 | ||
733 | /* Get a new binding from Xen. */ | |
734 | bind_ipi.vcpu = cpu; | |
735 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
736 | &bind_ipi) != 0) | |
737 | BUG(); | |
738 | evtchn = bind_ipi.port; | |
739 | ||
740 | /* Record the new mapping. */ | |
741 | evtchn_to_irq[evtchn] = irq; | |
742 | irq_info[irq] = mk_irq_info(IRQT_IPI, ipi, evtchn); | |
743 | bind_evtchn_to_cpu(evtchn, cpu); | |
744 | ||
745 | /* Ready for use. */ | |
746 | unmask_evtchn(evtchn); | |
747 | ||
748 | } | |
749 | } | |
750 | ||
2d9e1e2f JF |
751 | /* Clear an irq's pending state, in preparation for polling on it */ |
752 | void xen_clear_irq_pending(int irq) | |
753 | { | |
754 | int evtchn = evtchn_from_irq(irq); | |
755 | ||
756 | if (VALID_EVTCHN(evtchn)) | |
757 | clear_evtchn(evtchn); | |
758 | } | |
759 | ||
168d2f46 JF |
760 | void xen_set_irq_pending(int irq) |
761 | { | |
762 | int evtchn = evtchn_from_irq(irq); | |
763 | ||
764 | if (VALID_EVTCHN(evtchn)) | |
765 | set_evtchn(evtchn); | |
766 | } | |
767 | ||
768 | bool xen_test_irq_pending(int irq) | |
769 | { | |
770 | int evtchn = evtchn_from_irq(irq); | |
771 | bool ret = false; | |
772 | ||
773 | if (VALID_EVTCHN(evtchn)) | |
774 | ret = test_evtchn(evtchn); | |
775 | ||
776 | return ret; | |
777 | } | |
778 | ||
2d9e1e2f JF |
779 | /* Poll waiting for an irq to become pending. In the usual case, the |
780 | irq will be disabled so it won't deliver an interrupt. */ | |
781 | void xen_poll_irq(int irq) | |
782 | { | |
783 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
784 | ||
785 | if (VALID_EVTCHN(evtchn)) { | |
786 | struct sched_poll poll; | |
787 | ||
788 | poll.nr_ports = 1; | |
789 | poll.timeout = 0; | |
ff3c5362 | 790 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
791 | |
792 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
793 | BUG(); | |
794 | } | |
795 | } | |
796 | ||
0e91398f JF |
797 | void xen_irq_resume(void) |
798 | { | |
799 | unsigned int cpu, irq, evtchn; | |
800 | ||
801 | init_evtchn_cpu_bindings(); | |
802 | ||
803 | /* New event-channel space is not 'live' yet. */ | |
804 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
805 | mask_evtchn(evtchn); | |
806 | ||
807 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 808 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
809 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
810 | ||
811 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
812 | evtchn_to_irq[evtchn] = -1; | |
813 | ||
814 | for_each_possible_cpu(cpu) { | |
815 | restore_cpu_virqs(cpu); | |
816 | restore_cpu_ipis(cpu); | |
817 | } | |
818 | } | |
819 | ||
e46cdb66 JF |
820 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
821 | .name = "xen-dyn", | |
822 | .mask = disable_dynirq, | |
823 | .unmask = enable_dynirq, | |
824 | .ack = ack_dynirq, | |
825 | .set_affinity = set_affinity_irq, | |
826 | .retrigger = retrigger_dynirq, | |
827 | }; | |
828 | ||
829 | void __init xen_init_IRQ(void) | |
830 | { | |
831 | int i; | |
c7a3589e MT |
832 | size_t size = nr_cpu_ids * sizeof(struct cpu_evtchn_s); |
833 | ||
834 | cpu_evtchn_mask_p = kmalloc(size, GFP_KERNEL); | |
835 | BUG_ON(cpu_evtchn_mask == NULL); | |
e46cdb66 JF |
836 | |
837 | init_evtchn_cpu_bindings(); | |
838 | ||
839 | /* No event channels are 'live' right now. */ | |
840 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
841 | mask_evtchn(i); | |
842 | ||
843 | /* Dynamic IRQ space is currently unbound. Zero the refcnts. */ | |
0b8f1efa | 844 | for (i = 0; i < nr_irqs; i++) |
e46cdb66 JF |
845 | irq_bindcount[i] = 0; |
846 | ||
847 | irq_ctx_init(smp_processor_id()); | |
848 | } |