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CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
77365948 57static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 58
6cb6537d
IC
59static LIST_HEAD(xen_irq_list_head);
60
e46cdb66 61/* IRQ <-> VIRQ mapping. */
204fba4a 62static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 63
f87e4cac 64/* IRQ <-> IPI mapping */
204fba4a 65static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 66
ced40d0f
JF
67/* Interrupt types. */
68enum xen_irq_type {
d77bbd4d 69 IRQT_UNBOUND = 0,
f87e4cac
JF
70 IRQT_PIRQ,
71 IRQT_VIRQ,
72 IRQT_IPI,
73 IRQT_EVTCHN
74};
e46cdb66 75
ced40d0f
JF
76/*
77 * Packed IRQ information:
78 * type - enum xen_irq_type
79 * event channel - irq->event channel mapping
80 * cpu - cpu this event channel is bound to
81 * index - type-specific information:
42a1de56
SS
82 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
83 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
84 * VIRQ - virq number
85 * IPI - IPI vector
86 * EVTCHN -
87 */
088c05a8 88struct irq_info {
6cb6537d 89 struct list_head list;
420eb554 90 int refcnt;
ced40d0f 91 enum xen_irq_type type; /* type */
6cb6537d 92 unsigned irq;
ced40d0f
JF
93 unsigned short evtchn; /* event channel */
94 unsigned short cpu; /* cpu bound */
95
96 union {
97 unsigned short virq;
98 enum ipi_vector ipi;
99 struct {
7a043f11 100 unsigned short pirq;
ced40d0f 101 unsigned short gsi;
d46a78b0
JF
102 unsigned char vector;
103 unsigned char flags;
beafbdc1 104 uint16_t domid;
ced40d0f
JF
105 } pirq;
106 } u;
107};
d46a78b0 108#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 109#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 110
b21ddbf5 111static int *evtchn_to_irq;
3b32f574 112
cb60d114
IC
113static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
114 cpu_evtchn_mask);
e46cdb66 115
e46cdb66
JF
116/* Xen will never allocate port zero for any purpose. */
117#define VALID_EVTCHN(chn) ((chn) != 0)
118
e46cdb66 119static struct irq_chip xen_dynamic_chip;
aaca4964 120static struct irq_chip xen_percpu_chip;
d46a78b0 121static struct irq_chip xen_pirq_chip;
7e186bdd
SS
122static void enable_dynirq(struct irq_data *data);
123static void disable_dynirq(struct irq_data *data);
e46cdb66 124
9158c358
IC
125/* Get info for IRQ */
126static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 127{
c442b806 128 return irq_get_handler_data(irq);
ced40d0f
JF
129}
130
9158c358
IC
131/* Constructors for packed IRQ information. */
132static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 133 unsigned irq,
9158c358
IC
134 enum xen_irq_type type,
135 unsigned short evtchn,
136 unsigned short cpu)
ced40d0f 137{
9158c358
IC
138
139 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
140
141 info->type = type;
6cb6537d 142 info->irq = irq;
9158c358
IC
143 info->evtchn = evtchn;
144 info->cpu = cpu;
3d4cfa37
IC
145
146 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
147}
148
9158c358
IC
149static void xen_irq_info_evtchn_init(unsigned irq,
150 unsigned short evtchn)
ced40d0f 151{
9158c358
IC
152 struct irq_info *info = info_for_irq(irq);
153
3d4cfa37 154 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
155}
156
3d4cfa37
IC
157static void xen_irq_info_ipi_init(unsigned cpu,
158 unsigned irq,
9158c358
IC
159 unsigned short evtchn,
160 enum ipi_vector ipi)
e46cdb66 161{
9158c358
IC
162 struct irq_info *info = info_for_irq(irq);
163
3d4cfa37 164 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
165
166 info->u.ipi = ipi;
3d4cfa37
IC
167
168 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
169}
170
3d4cfa37
IC
171static void xen_irq_info_virq_init(unsigned cpu,
172 unsigned irq,
9158c358
IC
173 unsigned short evtchn,
174 unsigned short virq)
ced40d0f 175{
9158c358
IC
176 struct irq_info *info = info_for_irq(irq);
177
3d4cfa37 178 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
179
180 info->u.virq = virq;
3d4cfa37
IC
181
182 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
183}
184
9158c358
IC
185static void xen_irq_info_pirq_init(unsigned irq,
186 unsigned short evtchn,
187 unsigned short pirq,
188 unsigned short gsi,
189 unsigned short vector,
beafbdc1 190 uint16_t domid,
9158c358 191 unsigned char flags)
ced40d0f 192{
9158c358
IC
193 struct irq_info *info = info_for_irq(irq);
194
3d4cfa37 195 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
196
197 info->u.pirq.pirq = pirq;
198 info->u.pirq.gsi = gsi;
199 info->u.pirq.vector = vector;
beafbdc1 200 info->u.pirq.domid = domid;
9158c358 201 info->u.pirq.flags = flags;
e46cdb66
JF
202}
203
204/*
205 * Accessors for packed IRQ information.
206 */
ced40d0f 207static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 208{
110e7c7e
JJ
209 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
210 return 0;
211
ced40d0f 212 return info_for_irq(irq)->evtchn;
e46cdb66
JF
213}
214
d4c04536
IC
215unsigned irq_from_evtchn(unsigned int evtchn)
216{
217 return evtchn_to_irq[evtchn];
218}
219EXPORT_SYMBOL_GPL(irq_from_evtchn);
220
ced40d0f 221static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 222{
ced40d0f
JF
223 struct irq_info *info = info_for_irq(irq);
224
225 BUG_ON(info == NULL);
226 BUG_ON(info->type != IRQT_IPI);
227
228 return info->u.ipi;
229}
230
231static unsigned virq_from_irq(unsigned irq)
232{
233 struct irq_info *info = info_for_irq(irq);
234
235 BUG_ON(info == NULL);
236 BUG_ON(info->type != IRQT_VIRQ);
237
238 return info->u.virq;
239}
240
7a043f11
SS
241static unsigned pirq_from_irq(unsigned irq)
242{
243 struct irq_info *info = info_for_irq(irq);
244
245 BUG_ON(info == NULL);
246 BUG_ON(info->type != IRQT_PIRQ);
247
248 return info->u.pirq.pirq;
249}
250
ced40d0f
JF
251static enum xen_irq_type type_from_irq(unsigned irq)
252{
253 return info_for_irq(irq)->type;
254}
255
256static unsigned cpu_from_irq(unsigned irq)
257{
258 return info_for_irq(irq)->cpu;
259}
260
261static unsigned int cpu_from_evtchn(unsigned int evtchn)
262{
263 int irq = evtchn_to_irq[evtchn];
264 unsigned ret = 0;
265
266 if (irq != -1)
267 ret = cpu_from_irq(irq);
268
269 return ret;
e46cdb66
JF
270}
271
d46a78b0
JF
272static bool pirq_needs_eoi(unsigned irq)
273{
274 struct irq_info *info = info_for_irq(irq);
275
276 BUG_ON(info->type != IRQT_PIRQ);
277
278 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
279}
280
e46cdb66
JF
281static inline unsigned long active_evtchns(unsigned int cpu,
282 struct shared_info *sh,
283 unsigned int idx)
284{
088c05a8 285 return sh->evtchn_pending[idx] &
cb60d114 286 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 287 ~sh->evtchn_mask[idx];
e46cdb66
JF
288}
289
290static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
291{
292 int irq = evtchn_to_irq[chn];
293
294 BUG_ON(irq == -1);
295#ifdef CONFIG_SMP
c9e265e0 296 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
297#endif
298
cb60d114
IC
299 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
300 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 301
ca62ce8c 302 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
303}
304
305static void init_evtchn_cpu_bindings(void)
306{
1c6969ec 307 int i;
e46cdb66 308#ifdef CONFIG_SMP
6cb6537d 309 struct irq_info *info;
10e58084 310
e46cdb66 311 /* By default all event channels notify CPU#0. */
6cb6537d
IC
312 list_for_each_entry(info, &xen_irq_list_head, list) {
313 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 314 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 315 }
e46cdb66
JF
316#endif
317
1c6969ec 318 for_each_possible_cpu(i)
cb60d114
IC
319 memset(per_cpu(cpu_evtchn_mask, i),
320 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
321}
322
e46cdb66
JF
323static inline void clear_evtchn(int port)
324{
325 struct shared_info *s = HYPERVISOR_shared_info;
326 sync_clear_bit(port, &s->evtchn_pending[0]);
327}
328
329static inline void set_evtchn(int port)
330{
331 struct shared_info *s = HYPERVISOR_shared_info;
332 sync_set_bit(port, &s->evtchn_pending[0]);
333}
334
168d2f46
JF
335static inline int test_evtchn(int port)
336{
337 struct shared_info *s = HYPERVISOR_shared_info;
338 return sync_test_bit(port, &s->evtchn_pending[0]);
339}
340
e46cdb66
JF
341
342/**
343 * notify_remote_via_irq - send event to remote end of event channel via irq
344 * @irq: irq of event channel to send event to
345 *
346 * Unlike notify_remote_via_evtchn(), this is safe to use across
347 * save/restore. Notifications on a broken connection are silently
348 * dropped.
349 */
350void notify_remote_via_irq(int irq)
351{
352 int evtchn = evtchn_from_irq(irq);
353
354 if (VALID_EVTCHN(evtchn))
355 notify_remote_via_evtchn(evtchn);
356}
357EXPORT_SYMBOL_GPL(notify_remote_via_irq);
358
359static void mask_evtchn(int port)
360{
361 struct shared_info *s = HYPERVISOR_shared_info;
362 sync_set_bit(port, &s->evtchn_mask[0]);
363}
364
365static void unmask_evtchn(int port)
366{
367 struct shared_info *s = HYPERVISOR_shared_info;
368 unsigned int cpu = get_cpu();
369
370 BUG_ON(!irqs_disabled());
371
372 /* Slow path (hypercall) if this is a non-local port. */
373 if (unlikely(cpu != cpu_from_evtchn(port))) {
374 struct evtchn_unmask unmask = { .port = port };
375 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
376 } else {
780f36d8 377 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
378
379 sync_clear_bit(port, &s->evtchn_mask[0]);
380
381 /*
382 * The following is basically the equivalent of
383 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
384 * the interrupt edge' if the channel is masked.
385 */
386 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
387 !sync_test_and_set_bit(port / BITS_PER_LONG,
388 &vcpu_info->evtchn_pending_sel))
389 vcpu_info->evtchn_upcall_pending = 1;
390 }
391
392 put_cpu();
393}
394
6cb6537d
IC
395static void xen_irq_init(unsigned irq)
396{
397 struct irq_info *info;
b5328cd1 398#ifdef CONFIG_SMP
6cb6537d
IC
399 struct irq_desc *desc = irq_to_desc(irq);
400
401 /* By default all event channels notify CPU#0. */
402 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 403#endif
6cb6537d 404
ca62ce8c
IC
405 info = kzalloc(sizeof(*info), GFP_KERNEL);
406 if (info == NULL)
407 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
408
409 info->type = IRQT_UNBOUND;
420eb554 410 info->refcnt = -1;
6cb6537d 411
c442b806 412 irq_set_handler_data(irq, info);
ca62ce8c 413
6cb6537d
IC
414 list_add_tail(&info->list, &xen_irq_list_head);
415}
416
7bee9768 417static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 418{
89911501
IC
419 int first = 0;
420 int irq;
0794bfc7
KRW
421
422#ifdef CONFIG_X86_IO_APIC
89911501
IC
423 /*
424 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 425 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
426 * e.g. those corresponding to event channels or MSIs
427 * etc. from the range above those "real" GSIs to avoid
428 * collisions.
429 */
430 if (xen_initial_domain() || xen_hvm_domain())
431 first = get_nr_irqs_gsi();
0794bfc7
KRW
432#endif
433
89911501 434 irq = irq_alloc_desc_from(first, -1);
3a69e916 435
e6599225
KRW
436 if (irq >= 0)
437 xen_irq_init(irq);
ced40d0f 438
e46cdb66 439 return irq;
d46a78b0
JF
440}
441
7bee9768 442static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
443{
444 int irq;
445
89911501
IC
446 /*
447 * A PV guest has no concept of a GSI (since it has no ACPI
448 * nor access to/knowledge of the physical APICs). Therefore
449 * all IRQs are dynamically allocated from the entire IRQ
450 * space.
451 */
452 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
453 return xen_allocate_irq_dynamic();
454
455 /* Legacy IRQ descriptors are already allocated by the arch. */
456 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
457 irq = gsi;
458 else
459 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 460
6cb6537d 461 xen_irq_init(irq);
c9df1ce5
IC
462
463 return irq;
464}
465
466static void xen_free_irq(unsigned irq)
467{
c442b806 468 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
469
470 list_del(&info->list);
9158c358 471
c442b806 472 irq_set_handler_data(irq, NULL);
ca62ce8c 473
420eb554
DDG
474 WARN_ON(info->refcnt > 0);
475
ca62ce8c
IC
476 kfree(info);
477
72146104
IC
478 /* Legacy IRQ descriptors are managed by the arch. */
479 if (irq < NR_IRQS_LEGACY)
480 return;
481
c9df1ce5
IC
482 irq_free_desc(irq);
483}
484
d46a78b0
JF
485static void pirq_query_unmask(int irq)
486{
487 struct physdev_irq_status_query irq_status;
488 struct irq_info *info = info_for_irq(irq);
489
490 BUG_ON(info->type != IRQT_PIRQ);
491
7a043f11 492 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
493 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
494 irq_status.flags = 0;
495
496 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
497 if (irq_status.flags & XENIRQSTAT_needs_eoi)
498 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
499}
500
501static bool probing_irq(int irq)
502{
503 struct irq_desc *desc = irq_to_desc(irq);
504
505 return desc && desc->action == NULL;
506}
507
7e186bdd
SS
508static void eoi_pirq(struct irq_data *data)
509{
510 int evtchn = evtchn_from_irq(data->irq);
511 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
512 int rc = 0;
513
514 irq_move_irq(data);
515
516 if (VALID_EVTCHN(evtchn))
517 clear_evtchn(evtchn);
518
519 if (pirq_needs_eoi(data->irq)) {
520 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
521 WARN_ON(rc);
522 }
523}
524
525static void mask_ack_pirq(struct irq_data *data)
526{
527 disable_dynirq(data);
528 eoi_pirq(data);
529}
530
c9e265e0 531static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
532{
533 struct evtchn_bind_pirq bind_pirq;
534 struct irq_info *info = info_for_irq(irq);
535 int evtchn = evtchn_from_irq(irq);
15ebbb82 536 int rc;
d46a78b0
JF
537
538 BUG_ON(info->type != IRQT_PIRQ);
539
540 if (VALID_EVTCHN(evtchn))
541 goto out;
542
7a043f11 543 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 544 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
545 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
546 BIND_PIRQ__WILL_SHARE : 0;
547 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
548 if (rc != 0) {
d46a78b0
JF
549 if (!probing_irq(irq))
550 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
551 irq);
552 return 0;
553 }
554 evtchn = bind_pirq.port;
555
556 pirq_query_unmask(irq);
557
558 evtchn_to_irq[evtchn] = irq;
559 bind_evtchn_to_cpu(evtchn, 0);
560 info->evtchn = evtchn;
561
562out:
563 unmask_evtchn(evtchn);
7e186bdd 564 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
565
566 return 0;
567}
568
c9e265e0
TG
569static unsigned int startup_pirq(struct irq_data *data)
570{
571 return __startup_pirq(data->irq);
572}
573
574static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
575{
576 struct evtchn_close close;
c9e265e0 577 unsigned int irq = data->irq;
d46a78b0
JF
578 struct irq_info *info = info_for_irq(irq);
579 int evtchn = evtchn_from_irq(irq);
580
581 BUG_ON(info->type != IRQT_PIRQ);
582
583 if (!VALID_EVTCHN(evtchn))
584 return;
585
586 mask_evtchn(evtchn);
587
588 close.port = evtchn;
589 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
590 BUG();
591
592 bind_evtchn_to_cpu(evtchn, 0);
593 evtchn_to_irq[evtchn] = -1;
594 info->evtchn = 0;
595}
596
c9e265e0 597static void enable_pirq(struct irq_data *data)
d46a78b0 598{
c9e265e0 599 startup_pirq(data);
d46a78b0
JF
600}
601
c9e265e0 602static void disable_pirq(struct irq_data *data)
d46a78b0 603{
7e186bdd 604 disable_dynirq(data);
d46a78b0
JF
605}
606
d46a78b0
JF
607static int find_irq_by_gsi(unsigned gsi)
608{
6cb6537d 609 struct irq_info *info;
d46a78b0 610
6cb6537d
IC
611 list_for_each_entry(info, &xen_irq_list_head, list) {
612 if (info->type != IRQT_PIRQ)
d46a78b0
JF
613 continue;
614
6cb6537d
IC
615 if (info->u.pirq.gsi == gsi)
616 return info->irq;
d46a78b0
JF
617 }
618
619 return -1;
620}
621
653378ac
IC
622/*
623 * Do not make any assumptions regarding the relationship between the
624 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
625 *
626 * Note: We don't assign an event channel until the irq actually started
627 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
628 *
629 * Shareable implies level triggered, not shareable implies edge
630 * triggered here.
d46a78b0 631 */
f4d0635b
IC
632int xen_bind_pirq_gsi_to_irq(unsigned gsi,
633 unsigned pirq, int shareable, char *name)
d46a78b0 634{
a0e18116 635 int irq = -1;
d46a78b0
JF
636 struct physdev_irq irq_op;
637
77365948 638 mutex_lock(&irq_mapping_update_lock);
d46a78b0
JF
639
640 irq = find_irq_by_gsi(gsi);
641 if (irq != -1) {
7a043f11 642 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 643 irq, gsi);
420eb554 644 goto out;
d46a78b0
JF
645 }
646
c9df1ce5 647 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
648 if (irq < 0)
649 goto out;
d46a78b0 650
d46a78b0 651 irq_op.irq = irq;
b5401a96
AN
652 irq_op.vector = 0;
653
654 /* Only the privileged domain can do this. For non-priv, the pcifront
655 * driver provides a PCI bus that does the call to do exactly
656 * this in the priv domain. */
657 if (xen_initial_domain() &&
658 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 659 xen_free_irq(irq);
d46a78b0
JF
660 irq = -ENOSPC;
661 goto out;
662 }
663
beafbdc1 664 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 665 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 666
7e186bdd
SS
667 pirq_query_unmask(irq);
668 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
669 * type of interrupt: if the interrupt is an edge triggered
670 * interrupt we use handle_edge_irq.
7e186bdd 671 *
e5ac0bda
SS
672 * On the other hand if the interrupt is level triggered we use
673 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 674 * interrupts.
e5ac0bda 675 *
7e186bdd
SS
676 * Depending on the Xen version, pirq_needs_eoi might return true
677 * not only for level triggered interrupts but for edge triggered
678 * interrupts too. In any case Xen always honors the eoi mechanism,
679 * not injecting any more pirqs of the same kind if the first one
680 * hasn't received an eoi yet. Therefore using the fasteoi handler
681 * is the right choice either way.
682 */
e5ac0bda 683 if (shareable)
7e186bdd
SS
684 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
685 handle_fasteoi_irq, name);
686 else
687 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
688 handle_edge_irq, name);
689
d46a78b0 690out:
77365948 691 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
692
693 return irq;
694}
695
f731e3ef 696#ifdef CONFIG_PCI_MSI
bf480d95 697int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 698{
5cad61a6 699 int rc;
cbf6aa89 700 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 701
bf480d95 702 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 703 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 704
5cad61a6
IC
705 WARN_ONCE(rc == -ENOSYS,
706 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
707
708 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
709}
710
bf480d95 711int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
712 int pirq, int vector, const char *name,
713 domid_t domid)
809f9267 714{
bf480d95 715 int irq, ret;
4b41df7f 716
77365948 717 mutex_lock(&irq_mapping_update_lock);
809f9267 718
4b41df7f 719 irq = xen_allocate_irq_dynamic();
e6599225 720 if (irq < 0)
bb5d079a 721 goto out;
809f9267 722
7e186bdd
SS
723 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
724 name);
809f9267 725
beafbdc1 726 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 727 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
728 if (ret < 0)
729 goto error_irq;
809f9267 730out:
77365948 731 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 732 return irq;
bf480d95 733error_irq:
77365948 734 mutex_unlock(&irq_mapping_update_lock);
bf480d95 735 xen_free_irq(irq);
e6599225 736 return ret;
809f9267 737}
f731e3ef
QH
738#endif
739
b5401a96
AN
740int xen_destroy_irq(int irq)
741{
742 struct irq_desc *desc;
38aa66fc
JF
743 struct physdev_unmap_pirq unmap_irq;
744 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
745 int rc = -ENOENT;
746
77365948 747 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
748
749 desc = irq_to_desc(irq);
750 if (!desc)
751 goto out;
752
38aa66fc 753 if (xen_initial_domain()) {
12334715 754 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 755 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 756 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
757 /* If another domain quits without making the pci_disable_msix
758 * call, the Xen hypervisor takes care of freeing the PIRQs
759 * (free_domain_pirqs).
760 */
761 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
762 printk(KERN_INFO "domain %d does not have %d anymore\n",
763 info->u.pirq.domid, info->u.pirq.pirq);
764 else if (rc) {
38aa66fc
JF
765 printk(KERN_WARNING "unmap irq failed %d\n", rc);
766 goto out;
767 }
768 }
b5401a96 769
c9df1ce5 770 xen_free_irq(irq);
b5401a96
AN
771
772out:
77365948 773 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
774 return rc;
775}
776
af42b8d1 777int xen_irq_from_pirq(unsigned pirq)
d46a78b0 778{
69c358ce 779 int irq;
d46a78b0 780
69c358ce 781 struct irq_info *info;
e46cdb66 782
77365948 783 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
784
785 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 786 if (info->type != IRQT_PIRQ)
69c358ce
IC
787 continue;
788 irq = info->irq;
789 if (info->u.pirq.pirq == pirq)
790 goto out;
791 }
792 irq = -1;
793out:
77365948 794 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
795
796 return irq;
af42b8d1
SS
797}
798
e6197acc
KRW
799
800int xen_pirq_from_irq(unsigned irq)
801{
802 return pirq_from_irq(irq);
803}
804EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 805int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
806{
807 int irq;
808
77365948 809 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
810
811 irq = evtchn_to_irq[evtchn];
812
813 if (irq == -1) {
c9df1ce5 814 irq = xen_allocate_irq_dynamic();
7bee9768
IC
815 if (irq == -1)
816 goto out;
e46cdb66 817
c442b806 818 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 819 handle_edge_irq, "event");
e46cdb66 820
9158c358 821 xen_irq_info_evtchn_init(irq, evtchn);
e46cdb66
JF
822 }
823
7bee9768 824out:
77365948 825 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
826
827 return irq;
828}
b536b4b9 829EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 830
f87e4cac
JF
831static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
832{
833 struct evtchn_bind_ipi bind_ipi;
834 int evtchn, irq;
835
77365948 836 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
837
838 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 839
f87e4cac 840 if (irq == -1) {
c9df1ce5 841 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
842 if (irq < 0)
843 goto out;
844
c442b806 845 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 846 handle_percpu_irq, "ipi");
f87e4cac
JF
847
848 bind_ipi.vcpu = cpu;
849 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
850 &bind_ipi) != 0)
851 BUG();
852 evtchn = bind_ipi.port;
853
3d4cfa37 854 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
855
856 bind_evtchn_to_cpu(evtchn, cpu);
857 }
858
f87e4cac 859 out:
77365948 860 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
861 return irq;
862}
863
2e820f58
IC
864static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
865 unsigned int remote_port)
866{
867 struct evtchn_bind_interdomain bind_interdomain;
868 int err;
869
870 bind_interdomain.remote_dom = remote_domain;
871 bind_interdomain.remote_port = remote_port;
872
873 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
874 &bind_interdomain);
875
876 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
877}
878
62cc5fc7
OH
879static int find_virq(unsigned int virq, unsigned int cpu)
880{
881 struct evtchn_status status;
882 int port, rc = -ENOENT;
883
884 memset(&status, 0, sizeof(status));
885 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
886 status.dom = DOMID_SELF;
887 status.port = port;
888 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
889 if (rc < 0)
890 continue;
891 if (status.status != EVTCHNSTAT_virq)
892 continue;
893 if (status.u.virq == virq && status.vcpu == cpu) {
894 rc = port;
895 break;
896 }
897 }
898 return rc;
899}
f87e4cac 900
4fe7d5a7 901int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
902{
903 struct evtchn_bind_virq bind_virq;
62cc5fc7 904 int evtchn, irq, ret;
e46cdb66 905
77365948 906 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
907
908 irq = per_cpu(virq_to_irq, cpu)[virq];
909
910 if (irq == -1) {
c9df1ce5 911 irq = xen_allocate_irq_dynamic();
7bee9768
IC
912 if (irq == -1)
913 goto out;
a52521f1 914
c442b806 915 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
916 handle_percpu_irq, "virq");
917
e46cdb66
JF
918 bind_virq.virq = virq;
919 bind_virq.vcpu = cpu;
62cc5fc7
OH
920 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
921 &bind_virq);
922 if (ret == 0)
923 evtchn = bind_virq.port;
924 else {
925 if (ret == -EEXIST)
926 ret = find_virq(virq, cpu);
927 BUG_ON(ret < 0);
928 evtchn = ret;
929 }
e46cdb66 930
3d4cfa37 931 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
932
933 bind_evtchn_to_cpu(evtchn, cpu);
934 }
935
7bee9768 936out:
77365948 937 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
938
939 return irq;
940}
941
942static void unbind_from_irq(unsigned int irq)
943{
944 struct evtchn_close close;
945 int evtchn = evtchn_from_irq(irq);
420eb554 946 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 947
77365948 948 mutex_lock(&irq_mapping_update_lock);
e46cdb66 949
420eb554
DDG
950 if (info->refcnt > 0) {
951 info->refcnt--;
952 if (info->refcnt != 0)
953 goto done;
954 }
955
d77bbd4d 956 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
957 close.port = evtchn;
958 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
959 BUG();
960
961 switch (type_from_irq(irq)) {
962 case IRQT_VIRQ:
963 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 964 [virq_from_irq(irq)] = -1;
e46cdb66 965 break;
d68d82af
AN
966 case IRQT_IPI:
967 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 968 [ipi_from_irq(irq)] = -1;
d68d82af 969 break;
e46cdb66
JF
970 default:
971 break;
972 }
973
974 /* Closed ports are implicitly re-bound to VCPU0. */
975 bind_evtchn_to_cpu(evtchn, 0);
976
977 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
978 }
979
ca62ce8c 980 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 981
9158c358 982 xen_free_irq(irq);
e46cdb66 983
420eb554 984 done:
77365948 985 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
986}
987
988int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 989 irq_handler_t handler,
e46cdb66
JF
990 unsigned long irqflags,
991 const char *devname, void *dev_id)
992{
361ae8cb 993 int irq, retval;
e46cdb66
JF
994
995 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
996 if (irq < 0)
997 return irq;
e46cdb66
JF
998 retval = request_irq(irq, handler, irqflags, devname, dev_id);
999 if (retval != 0) {
1000 unbind_from_irq(irq);
1001 return retval;
1002 }
1003
1004 return irq;
1005}
1006EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1007
2e820f58
IC
1008int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1009 unsigned int remote_port,
1010 irq_handler_t handler,
1011 unsigned long irqflags,
1012 const char *devname,
1013 void *dev_id)
1014{
1015 int irq, retval;
1016
1017 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1018 if (irq < 0)
1019 return irq;
1020
1021 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1022 if (retval != 0) {
1023 unbind_from_irq(irq);
1024 return retval;
1025 }
1026
1027 return irq;
1028}
1029EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1030
e46cdb66 1031int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1032 irq_handler_t handler,
e46cdb66
JF
1033 unsigned long irqflags, const char *devname, void *dev_id)
1034{
361ae8cb 1035 int irq, retval;
e46cdb66
JF
1036
1037 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1038 if (irq < 0)
1039 return irq;
e46cdb66
JF
1040 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1041 if (retval != 0) {
1042 unbind_from_irq(irq);
1043 return retval;
1044 }
1045
1046 return irq;
1047}
1048EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1049
f87e4cac
JF
1050int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1051 unsigned int cpu,
1052 irq_handler_t handler,
1053 unsigned long irqflags,
1054 const char *devname,
1055 void *dev_id)
1056{
1057 int irq, retval;
1058
1059 irq = bind_ipi_to_irq(ipi, cpu);
1060 if (irq < 0)
1061 return irq;
1062
9bab0b7f 1063 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1064 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1065 if (retval != 0) {
1066 unbind_from_irq(irq);
1067 return retval;
1068 }
1069
1070 return irq;
1071}
1072
e46cdb66
JF
1073void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1074{
1075 free_irq(irq, dev_id);
1076 unbind_from_irq(irq);
1077}
1078EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1079
420eb554
DDG
1080int evtchn_make_refcounted(unsigned int evtchn)
1081{
1082 int irq = evtchn_to_irq[evtchn];
1083 struct irq_info *info;
1084
1085 if (irq == -1)
1086 return -ENOENT;
1087
1088 info = irq_get_handler_data(irq);
1089
1090 if (!info)
1091 return -ENOENT;
1092
1093 WARN_ON(info->refcnt != -1);
1094
1095 info->refcnt = 1;
1096
1097 return 0;
1098}
1099EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1100
1101int evtchn_get(unsigned int evtchn)
1102{
1103 int irq;
1104 struct irq_info *info;
1105 int err = -ENOENT;
1106
1107 mutex_lock(&irq_mapping_update_lock);
1108
1109 irq = evtchn_to_irq[evtchn];
1110 if (irq == -1)
1111 goto done;
1112
1113 info = irq_get_handler_data(irq);
1114
1115 if (!info)
1116 goto done;
1117
1118 err = -EINVAL;
1119 if (info->refcnt <= 0)
1120 goto done;
1121
1122 info->refcnt++;
1123 err = 0;
1124 done:
1125 mutex_unlock(&irq_mapping_update_lock);
1126
1127 return err;
1128}
1129EXPORT_SYMBOL_GPL(evtchn_get);
1130
1131void evtchn_put(unsigned int evtchn)
1132{
1133 int irq = evtchn_to_irq[evtchn];
1134 if (WARN_ON(irq == -1))
1135 return;
1136 unbind_from_irq(irq);
1137}
1138EXPORT_SYMBOL_GPL(evtchn_put);
1139
f87e4cac
JF
1140void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1141{
1142 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1143 BUG_ON(irq < 0);
1144 notify_remote_via_irq(irq);
1145}
1146
ee523ca1
JF
1147irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1148{
1149 struct shared_info *sh = HYPERVISOR_shared_info;
1150 int cpu = smp_processor_id();
cb60d114 1151 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1152 int i;
1153 unsigned long flags;
1154 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1155 struct vcpu_info *v;
ee523ca1
JF
1156
1157 spin_lock_irqsave(&debug_lock, flags);
1158
cb52e6d9 1159 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1160
1161 for_each_online_cpu(i) {
cb52e6d9
IC
1162 int pending;
1163 v = per_cpu(xen_vcpu, i);
1164 pending = (get_irq_regs() && i == cpu)
1165 ? xen_irqs_disabled(get_irq_regs())
1166 : v->evtchn_upcall_mask;
1167 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1168 pending, v->evtchn_upcall_pending,
1169 (int)(sizeof(v->evtchn_pending_sel)*2),
1170 v->evtchn_pending_sel);
1171 }
1172 v = per_cpu(xen_vcpu, cpu);
1173
1174 printk("\npending:\n ");
1175 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1176 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1177 sh->evtchn_pending[i],
1178 i % 8 == 0 ? "\n " : " ");
1179 printk("\nglobal mask:\n ");
1180 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1181 printk("%0*lx%s",
1182 (int)(sizeof(sh->evtchn_mask[0])*2),
1183 sh->evtchn_mask[i],
1184 i % 8 == 0 ? "\n " : " ");
1185
1186 printk("\nglobally unmasked:\n ");
1187 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1188 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1189 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1190 i % 8 == 0 ? "\n " : " ");
1191
1192 printk("\nlocal cpu%d mask:\n ", cpu);
1193 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1194 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1195 cpu_evtchn[i],
1196 i % 8 == 0 ? "\n " : " ");
1197
1198 printk("\nlocally unmasked:\n ");
1199 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1200 unsigned long pending = sh->evtchn_pending[i]
1201 & ~sh->evtchn_mask[i]
1202 & cpu_evtchn[i];
1203 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1204 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1205 }
ee523ca1
JF
1206
1207 printk("\npending list:\n");
cb52e6d9 1208 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1209 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1210 int word_idx = i / BITS_PER_LONG;
1211 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1212 cpu_from_evtchn(i), i,
cb52e6d9
IC
1213 evtchn_to_irq[i],
1214 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1215 ? "" : " l2-clear",
1216 !sync_test_bit(i, sh->evtchn_mask)
1217 ? "" : " globally-masked",
1218 sync_test_bit(i, cpu_evtchn)
1219 ? "" : " locally-masked");
ee523ca1
JF
1220 }
1221 }
1222
1223 spin_unlock_irqrestore(&debug_lock, flags);
1224
1225 return IRQ_HANDLED;
1226}
1227
245b2e70 1228static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1229static DEFINE_PER_CPU(unsigned int, current_word_idx);
1230static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1231
ab7f863e
SR
1232/*
1233 * Mask out the i least significant bits of w
1234 */
1235#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1236
e46cdb66
JF
1237/*
1238 * Search the CPUs pending events bitmasks. For each one found, map
1239 * the event number to an irq, and feed it into do_IRQ() for
1240 * handling.
1241 *
1242 * Xen uses a two-level bitmap to speed searching. The first level is
1243 * a bitset of words which contain pending event bits. The second
1244 * level is a bitset of pending events themselves.
1245 */
38e20b07 1246static void __xen_evtchn_do_upcall(void)
e46cdb66 1247{
24b51c2f 1248 int start_word_idx, start_bit_idx;
ab7f863e 1249 int word_idx, bit_idx;
24b51c2f 1250 int i;
e46cdb66
JF
1251 int cpu = get_cpu();
1252 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1253 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1254 unsigned count;
e46cdb66 1255
229664be
JF
1256 do {
1257 unsigned long pending_words;
e46cdb66 1258
229664be 1259 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1260
b2e4ae69 1261 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1262 goto out;
e46cdb66 1263
e849c3e9
IY
1264#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1265 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1266 wmb();
e849c3e9 1267#endif
229664be 1268 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1269
24b51c2f
KF
1270 start_word_idx = __this_cpu_read(current_word_idx);
1271 start_bit_idx = __this_cpu_read(current_bit_idx);
1272
1273 word_idx = start_word_idx;
ab7f863e 1274
24b51c2f 1275 for (i = 0; pending_words != 0; i++) {
229664be 1276 unsigned long pending_bits;
ab7f863e 1277 unsigned long words;
229664be 1278
ab7f863e
SR
1279 words = MASK_LSBS(pending_words, word_idx);
1280
1281 /*
ada6814c 1282 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1283 */
1284 if (words == 0) {
ada6814c
KF
1285 word_idx = 0;
1286 bit_idx = 0;
ab7f863e
SR
1287 continue;
1288 }
1289 word_idx = __ffs(words);
229664be 1290
24b51c2f
KF
1291 pending_bits = active_evtchns(cpu, s, word_idx);
1292 bit_idx = 0; /* usually scan entire word from start */
1293 if (word_idx == start_word_idx) {
1294 /* We scan the starting word in two parts */
1295 if (i == 0)
1296 /* 1st time: start in the middle */
1297 bit_idx = start_bit_idx;
1298 else
1299 /* 2nd time: mask bits done already */
1300 bit_idx &= (1UL << start_bit_idx) - 1;
1301 }
1302
ab7f863e
SR
1303 do {
1304 unsigned long bits;
1305 int port, irq;
ca4dbc66 1306 struct irq_desc *desc;
229664be 1307
ab7f863e
SR
1308 bits = MASK_LSBS(pending_bits, bit_idx);
1309
1310 /* If we masked out all events, move on. */
ada6814c 1311 if (bits == 0)
ab7f863e 1312 break;
ab7f863e
SR
1313
1314 bit_idx = __ffs(bits);
1315
1316 /* Process port. */
1317 port = (word_idx * BITS_PER_LONG) + bit_idx;
1318 irq = evtchn_to_irq[port];
1319
ca4dbc66
EB
1320 if (irq != -1) {
1321 desc = irq_to_desc(irq);
1322 if (desc)
1323 generic_handle_irq_desc(irq, desc);
1324 }
ab7f863e 1325
ada6814c
KF
1326 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1327
1328 /* Next caller starts at last processed + 1 */
1329 __this_cpu_write(current_word_idx,
1330 bit_idx ? word_idx :
1331 (word_idx+1) % BITS_PER_LONG);
1332 __this_cpu_write(current_bit_idx, bit_idx);
1333 } while (bit_idx != 0);
ab7f863e 1334
24b51c2f
KF
1335 /* Scan start_l1i twice; all others once. */
1336 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1337 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1338
1339 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1340 }
e46cdb66 1341
229664be
JF
1342 BUG_ON(!irqs_disabled());
1343
780f36d8
CL
1344 count = __this_cpu_read(xed_nesting_count);
1345 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1346 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1347
1348out:
38e20b07
SY
1349
1350 put_cpu();
1351}
1352
1353void xen_evtchn_do_upcall(struct pt_regs *regs)
1354{
1355 struct pt_regs *old_regs = set_irq_regs(regs);
1356
1357 exit_idle();
1358 irq_enter();
1359
1360 __xen_evtchn_do_upcall();
1361
3445a8fd
JF
1362 irq_exit();
1363 set_irq_regs(old_regs);
38e20b07 1364}
3445a8fd 1365
38e20b07
SY
1366void xen_hvm_evtchn_do_upcall(void)
1367{
1368 __xen_evtchn_do_upcall();
e46cdb66 1369}
183d03cc 1370EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1371
eb1e305f
JF
1372/* Rebind a new event channel to an existing irq. */
1373void rebind_evtchn_irq(int evtchn, int irq)
1374{
d77bbd4d
JF
1375 struct irq_info *info = info_for_irq(irq);
1376
eb1e305f
JF
1377 /* Make sure the irq is masked, since the new event channel
1378 will also be masked. */
1379 disable_irq(irq);
1380
77365948 1381 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1382
1383 /* After resume the irq<->evtchn mappings are all cleared out */
1384 BUG_ON(evtchn_to_irq[evtchn] != -1);
1385 /* Expect irq to have been bound before,
d77bbd4d
JF
1386 so there should be a proper type */
1387 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1388
9158c358 1389 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1390
77365948 1391 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1392
1393 /* new event channels are always bound to cpu 0 */
0de26520 1394 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1395
1396 /* Unmask the event channel. */
1397 enable_irq(irq);
1398}
1399
e46cdb66 1400/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1401static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1402{
1403 struct evtchn_bind_vcpu bind_vcpu;
1404 int evtchn = evtchn_from_irq(irq);
1405
be49472f
IC
1406 if (!VALID_EVTCHN(evtchn))
1407 return -1;
1408
1409 /*
1410 * Events delivered via platform PCI interrupts are always
1411 * routed to vcpu 0 and hence cannot be rebound.
1412 */
1413 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1414 return -1;
e46cdb66
JF
1415
1416 /* Send future instances of this interrupt to other vcpu. */
1417 bind_vcpu.port = evtchn;
1418 bind_vcpu.vcpu = tcpu;
1419
1420 /*
1421 * If this fails, it usually just indicates that we're dealing with a
1422 * virq or IPI channel, which don't actually need to be rebound. Ignore
1423 * it, but don't do the xenlinux-level rebind in that case.
1424 */
1425 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1426 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1427
d5dedd45
YL
1428 return 0;
1429}
e46cdb66 1430
c9e265e0
TG
1431static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1432 bool force)
e46cdb66 1433{
0de26520 1434 unsigned tcpu = cpumask_first(dest);
d5dedd45 1435
c9e265e0 1436 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1437}
1438
642e0c88
IY
1439int resend_irq_on_evtchn(unsigned int irq)
1440{
1441 int masked, evtchn = evtchn_from_irq(irq);
1442 struct shared_info *s = HYPERVISOR_shared_info;
1443
1444 if (!VALID_EVTCHN(evtchn))
1445 return 1;
1446
1447 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1448 sync_set_bit(evtchn, s->evtchn_pending);
1449 if (!masked)
1450 unmask_evtchn(evtchn);
1451
1452 return 1;
1453}
1454
c9e265e0 1455static void enable_dynirq(struct irq_data *data)
e46cdb66 1456{
c9e265e0 1457 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1458
1459 if (VALID_EVTCHN(evtchn))
1460 unmask_evtchn(evtchn);
1461}
1462
c9e265e0 1463static void disable_dynirq(struct irq_data *data)
e46cdb66 1464{
c9e265e0 1465 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1466
1467 if (VALID_EVTCHN(evtchn))
1468 mask_evtchn(evtchn);
1469}
1470
c9e265e0 1471static void ack_dynirq(struct irq_data *data)
e46cdb66 1472{
c9e265e0 1473 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1474
7e186bdd 1475 irq_move_irq(data);
e46cdb66
JF
1476
1477 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1478 clear_evtchn(evtchn);
1479}
1480
1481static void mask_ack_dynirq(struct irq_data *data)
1482{
1483 disable_dynirq(data);
1484 ack_dynirq(data);
e46cdb66
JF
1485}
1486
c9e265e0 1487static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1488{
c9e265e0 1489 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1490 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1491 int ret = 0;
1492
1493 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1494 int masked;
1495
1496 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1497 sync_set_bit(evtchn, sh->evtchn_pending);
1498 if (!masked)
1499 unmask_evtchn(evtchn);
e46cdb66
JF
1500 ret = 1;
1501 }
1502
1503 return ret;
1504}
1505
0a85226f 1506static void restore_pirqs(void)
9a069c33
SS
1507{
1508 int pirq, rc, irq, gsi;
1509 struct physdev_map_pirq map_irq;
69c358ce 1510 struct irq_info *info;
9a069c33 1511
69c358ce
IC
1512 list_for_each_entry(info, &xen_irq_list_head, list) {
1513 if (info->type != IRQT_PIRQ)
9a069c33
SS
1514 continue;
1515
69c358ce
IC
1516 pirq = info->u.pirq.pirq;
1517 gsi = info->u.pirq.gsi;
1518 irq = info->irq;
1519
9a069c33
SS
1520 /* save/restore of PT devices doesn't work, so at this point the
1521 * only devices present are GSI based emulated devices */
9a069c33
SS
1522 if (!gsi)
1523 continue;
1524
1525 map_irq.domid = DOMID_SELF;
1526 map_irq.type = MAP_PIRQ_TYPE_GSI;
1527 map_irq.index = gsi;
1528 map_irq.pirq = pirq;
1529
1530 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1531 if (rc) {
1532 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1533 gsi, irq, pirq, rc);
9158c358 1534 xen_free_irq(irq);
9a069c33
SS
1535 continue;
1536 }
1537
1538 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1539
c9e265e0 1540 __startup_pirq(irq);
9a069c33
SS
1541 }
1542}
1543
0e91398f
JF
1544static void restore_cpu_virqs(unsigned int cpu)
1545{
1546 struct evtchn_bind_virq bind_virq;
1547 int virq, irq, evtchn;
1548
1549 for (virq = 0; virq < NR_VIRQS; virq++) {
1550 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1551 continue;
1552
ced40d0f 1553 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1554
1555 /* Get a new binding from Xen. */
1556 bind_virq.virq = virq;
1557 bind_virq.vcpu = cpu;
1558 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1559 &bind_virq) != 0)
1560 BUG();
1561 evtchn = bind_virq.port;
1562
1563 /* Record the new mapping. */
3d4cfa37 1564 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1565 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1566 }
1567}
1568
1569static void restore_cpu_ipis(unsigned int cpu)
1570{
1571 struct evtchn_bind_ipi bind_ipi;
1572 int ipi, irq, evtchn;
1573
1574 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1575 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1576 continue;
1577
ced40d0f 1578 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1579
1580 /* Get a new binding from Xen. */
1581 bind_ipi.vcpu = cpu;
1582 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1583 &bind_ipi) != 0)
1584 BUG();
1585 evtchn = bind_ipi.port;
1586
1587 /* Record the new mapping. */
3d4cfa37 1588 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1589 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1590 }
1591}
1592
2d9e1e2f
JF
1593/* Clear an irq's pending state, in preparation for polling on it */
1594void xen_clear_irq_pending(int irq)
1595{
1596 int evtchn = evtchn_from_irq(irq);
1597
1598 if (VALID_EVTCHN(evtchn))
1599 clear_evtchn(evtchn);
1600}
d9a8814f 1601EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1602void xen_set_irq_pending(int irq)
1603{
1604 int evtchn = evtchn_from_irq(irq);
1605
1606 if (VALID_EVTCHN(evtchn))
1607 set_evtchn(evtchn);
1608}
1609
1610bool xen_test_irq_pending(int irq)
1611{
1612 int evtchn = evtchn_from_irq(irq);
1613 bool ret = false;
1614
1615 if (VALID_EVTCHN(evtchn))
1616 ret = test_evtchn(evtchn);
1617
1618 return ret;
1619}
1620
d9a8814f
KRW
1621/* Poll waiting for an irq to become pending with timeout. In the usual case,
1622 * the irq will be disabled so it won't deliver an interrupt. */
1623void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1624{
1625 evtchn_port_t evtchn = evtchn_from_irq(irq);
1626
1627 if (VALID_EVTCHN(evtchn)) {
1628 struct sched_poll poll;
1629
1630 poll.nr_ports = 1;
d9a8814f 1631 poll.timeout = timeout;
ff3c5362 1632 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1633
1634 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1635 BUG();
1636 }
1637}
d9a8814f
KRW
1638EXPORT_SYMBOL(xen_poll_irq_timeout);
1639/* Poll waiting for an irq to become pending. In the usual case, the
1640 * irq will be disabled so it won't deliver an interrupt. */
1641void xen_poll_irq(int irq)
1642{
1643 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1644}
2d9e1e2f 1645
c7c2c3a2
KRW
1646/* Check whether the IRQ line is shared with other guests. */
1647int xen_test_irq_shared(int irq)
1648{
1649 struct irq_info *info = info_for_irq(irq);
1650 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1651
1652 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1653 return 0;
1654 return !(irq_status.flags & XENIRQSTAT_shared);
1655}
1656EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1657
0e91398f
JF
1658void xen_irq_resume(void)
1659{
6cb6537d
IC
1660 unsigned int cpu, evtchn;
1661 struct irq_info *info;
0e91398f
JF
1662
1663 init_evtchn_cpu_bindings();
1664
1665 /* New event-channel space is not 'live' yet. */
1666 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1667 mask_evtchn(evtchn);
1668
1669 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1670 list_for_each_entry(info, &xen_irq_list_head, list)
1671 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1672
1673 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1674 evtchn_to_irq[evtchn] = -1;
1675
1676 for_each_possible_cpu(cpu) {
1677 restore_cpu_virqs(cpu);
1678 restore_cpu_ipis(cpu);
1679 }
6903591f 1680
0a85226f 1681 restore_pirqs();
0e91398f
JF
1682}
1683
e46cdb66 1684static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1685 .name = "xen-dyn",
54a353a0 1686
c9e265e0
TG
1687 .irq_disable = disable_dynirq,
1688 .irq_mask = disable_dynirq,
1689 .irq_unmask = enable_dynirq,
54a353a0 1690
7e186bdd
SS
1691 .irq_ack = ack_dynirq,
1692 .irq_mask_ack = mask_ack_dynirq,
1693
c9e265e0
TG
1694 .irq_set_affinity = set_affinity_irq,
1695 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1696};
1697
d46a78b0 1698static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1699 .name = "xen-pirq",
d46a78b0 1700
c9e265e0
TG
1701 .irq_startup = startup_pirq,
1702 .irq_shutdown = shutdown_pirq,
c9e265e0 1703 .irq_enable = enable_pirq,
c9e265e0 1704 .irq_disable = disable_pirq,
d46a78b0 1705
7e186bdd
SS
1706 .irq_mask = disable_dynirq,
1707 .irq_unmask = enable_dynirq,
1708
1709 .irq_ack = eoi_pirq,
1710 .irq_eoi = eoi_pirq,
1711 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1712
c9e265e0 1713 .irq_set_affinity = set_affinity_irq,
d46a78b0 1714
c9e265e0 1715 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1716};
1717
aaca4964 1718static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1719 .name = "xen-percpu",
aaca4964 1720
c9e265e0
TG
1721 .irq_disable = disable_dynirq,
1722 .irq_mask = disable_dynirq,
1723 .irq_unmask = enable_dynirq,
aaca4964 1724
c9e265e0 1725 .irq_ack = ack_dynirq,
aaca4964
JF
1726};
1727
38e20b07
SY
1728int xen_set_callback_via(uint64_t via)
1729{
1730 struct xen_hvm_param a;
1731 a.domid = DOMID_SELF;
1732 a.index = HVM_PARAM_CALLBACK_IRQ;
1733 a.value = via;
1734 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1735}
1736EXPORT_SYMBOL_GPL(xen_set_callback_via);
1737
ca65f9fc 1738#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1739/* Vector callbacks are better than PCI interrupts to receive event
1740 * channel notifications because we can receive vector callbacks on any
1741 * vcpu and we don't need PCI support or APIC interactions. */
1742void xen_callback_vector(void)
1743{
1744 int rc;
1745 uint64_t callback_via;
1746 if (xen_have_vector_callback) {
1747 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1748 rc = xen_set_callback_via(callback_via);
1749 if (rc) {
1750 printk(KERN_ERR "Request for Xen HVM callback vector"
1751 " failed.\n");
1752 xen_have_vector_callback = 0;
1753 return;
1754 }
1755 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1756 "enabled\n");
1757 /* in the restore case the vector has already been allocated */
1758 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1759 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1760 }
1761}
ca65f9fc
SS
1762#else
1763void xen_callback_vector(void) {}
1764#endif
38e20b07 1765
e46cdb66
JF
1766void __init xen_init_IRQ(void)
1767{
e5fc7345 1768 int i;
c7a3589e 1769
b21ddbf5
JF
1770 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1771 GFP_KERNEL);
9d093e29 1772 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1773 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1774 evtchn_to_irq[i] = -1;
e46cdb66
JF
1775
1776 init_evtchn_cpu_bindings();
1777
1778 /* No event channels are 'live' right now. */
1779 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1780 mask_evtchn(i);
1781
38e20b07
SY
1782 if (xen_hvm_domain()) {
1783 xen_callback_vector();
1784 native_init_IRQ();
3942b740
SS
1785 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1786 * __acpi_register_gsi can point at the right function */
1787 pci_xen_hvm_init();
38e20b07
SY
1788 } else {
1789 irq_ctx_init(smp_processor_id());
38aa66fc 1790 if (xen_initial_domain())
a0ee0567 1791 pci_xen_initial_domain();
38e20b07 1792 }
e46cdb66 1793}