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xen: events: do not leak IRQ from xen_allocate_pirq_msi when no pirq available.
[mirror_ubuntu-artful-kernel.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
110e7c7e
JJ
173 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
174 return 0;
175
ced40d0f 176 return info_for_irq(irq)->evtchn;
e46cdb66
JF
177}
178
d4c04536
IC
179unsigned irq_from_evtchn(unsigned int evtchn)
180{
181 return evtchn_to_irq[evtchn];
182}
183EXPORT_SYMBOL_GPL(irq_from_evtchn);
184
ced40d0f 185static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 186{
ced40d0f
JF
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_IPI);
191
192 return info->u.ipi;
193}
194
195static unsigned virq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_VIRQ);
201
202 return info->u.virq;
203}
204
7a043f11
SS
205static unsigned pirq_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.pirq;
213}
214
ced40d0f
JF
215static unsigned gsi_from_irq(unsigned irq)
216{
217 struct irq_info *info = info_for_irq(irq);
218
219 BUG_ON(info == NULL);
220 BUG_ON(info->type != IRQT_PIRQ);
221
222 return info->u.pirq.gsi;
223}
224
225static unsigned vector_from_irq(unsigned irq)
226{
227 struct irq_info *info = info_for_irq(irq);
228
229 BUG_ON(info == NULL);
230 BUG_ON(info->type != IRQT_PIRQ);
231
232 return info->u.pirq.vector;
233}
234
235static enum xen_irq_type type_from_irq(unsigned irq)
236{
237 return info_for_irq(irq)->type;
238}
239
240static unsigned cpu_from_irq(unsigned irq)
241{
242 return info_for_irq(irq)->cpu;
243}
244
245static unsigned int cpu_from_evtchn(unsigned int evtchn)
246{
247 int irq = evtchn_to_irq[evtchn];
248 unsigned ret = 0;
249
250 if (irq != -1)
251 ret = cpu_from_irq(irq);
252
253 return ret;
e46cdb66
JF
254}
255
d46a78b0
JF
256static bool pirq_needs_eoi(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info->type != IRQT_PIRQ);
261
262 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
263}
264
e46cdb66
JF
265static inline unsigned long active_evtchns(unsigned int cpu,
266 struct shared_info *sh,
267 unsigned int idx)
268{
269 return (sh->evtchn_pending[idx] &
c7a3589e 270 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
271 ~sh->evtchn_mask[idx]);
272}
273
274static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
275{
276 int irq = evtchn_to_irq[chn];
277
278 BUG_ON(irq == -1);
279#ifdef CONFIG_SMP
c9e265e0 280 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
281#endif
282
e0419564
JF
283 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
284 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 285
ced40d0f 286 irq_info[irq].cpu = cpu;
e46cdb66
JF
287}
288
289static void init_evtchn_cpu_bindings(void)
290{
1c6969ec 291 int i;
e46cdb66 292#ifdef CONFIG_SMP
10e58084 293 struct irq_desc *desc;
10e58084 294
e46cdb66 295 /* By default all event channels notify CPU#0. */
0b8f1efa 296 for_each_irq_desc(i, desc) {
c9e265e0 297 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 298 }
e46cdb66
JF
299#endif
300
1c6969ec
JB
301 for_each_possible_cpu(i)
302 memset(cpu_evtchn_mask(i),
303 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
304
e46cdb66
JF
305}
306
e46cdb66
JF
307static inline void clear_evtchn(int port)
308{
309 struct shared_info *s = HYPERVISOR_shared_info;
310 sync_clear_bit(port, &s->evtchn_pending[0]);
311}
312
313static inline void set_evtchn(int port)
314{
315 struct shared_info *s = HYPERVISOR_shared_info;
316 sync_set_bit(port, &s->evtchn_pending[0]);
317}
318
168d2f46
JF
319static inline int test_evtchn(int port)
320{
321 struct shared_info *s = HYPERVISOR_shared_info;
322 return sync_test_bit(port, &s->evtchn_pending[0]);
323}
324
e46cdb66
JF
325
326/**
327 * notify_remote_via_irq - send event to remote end of event channel via irq
328 * @irq: irq of event channel to send event to
329 *
330 * Unlike notify_remote_via_evtchn(), this is safe to use across
331 * save/restore. Notifications on a broken connection are silently
332 * dropped.
333 */
334void notify_remote_via_irq(int irq)
335{
336 int evtchn = evtchn_from_irq(irq);
337
338 if (VALID_EVTCHN(evtchn))
339 notify_remote_via_evtchn(evtchn);
340}
341EXPORT_SYMBOL_GPL(notify_remote_via_irq);
342
343static void mask_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
346 sync_set_bit(port, &s->evtchn_mask[0]);
347}
348
349static void unmask_evtchn(int port)
350{
351 struct shared_info *s = HYPERVISOR_shared_info;
352 unsigned int cpu = get_cpu();
353
354 BUG_ON(!irqs_disabled());
355
356 /* Slow path (hypercall) if this is a non-local port. */
357 if (unlikely(cpu != cpu_from_evtchn(port))) {
358 struct evtchn_unmask unmask = { .port = port };
359 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
360 } else {
780f36d8 361 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
362
363 sync_clear_bit(port, &s->evtchn_mask[0]);
364
365 /*
366 * The following is basically the equivalent of
367 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
368 * the interrupt edge' if the channel is masked.
369 */
370 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
371 !sync_test_and_set_bit(port / BITS_PER_LONG,
372 &vcpu_info->evtchn_pending_sel))
373 vcpu_info->evtchn_upcall_pending = 1;
374 }
375
376 put_cpu();
377}
378
89911501 379static int xen_allocate_irq_dynamic(void)
0794bfc7 380{
89911501
IC
381 int first = 0;
382 int irq;
0794bfc7
KRW
383
384#ifdef CONFIG_X86_IO_APIC
89911501
IC
385 /*
386 * For an HVM guest or domain 0 which see "real" (emulated or
387 * actual repectively) GSIs we allocate dynamic IRQs
388 * e.g. those corresponding to event channels or MSIs
389 * etc. from the range above those "real" GSIs to avoid
390 * collisions.
391 */
392 if (xen_initial_domain() || xen_hvm_domain())
393 first = get_nr_irqs_gsi();
0794bfc7
KRW
394#endif
395
89911501
IC
396retry:
397 irq = irq_alloc_desc_from(first, -1);
3a69e916 398
89911501
IC
399 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
400 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
401 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
402 goto retry;
99ad198c 403 }
e46cdb66 404
89911501
IC
405 if (irq < 0)
406 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 407
e46cdb66 408 return irq;
d46a78b0
JF
409}
410
c9df1ce5
IC
411static int xen_allocate_irq_gsi(unsigned gsi)
412{
413 int irq;
414
89911501
IC
415 /*
416 * A PV guest has no concept of a GSI (since it has no ACPI
417 * nor access to/knowledge of the physical APICs). Therefore
418 * all IRQs are dynamically allocated from the entire IRQ
419 * space.
420 */
421 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
422 return xen_allocate_irq_dynamic();
423
424 /* Legacy IRQ descriptors are already allocated by the arch. */
425 if (gsi < NR_IRQS_LEGACY)
426 return gsi;
427
428 irq = irq_alloc_desc_at(gsi, -1);
429 if (irq < 0)
430 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
431
432 return irq;
433}
434
435static void xen_free_irq(unsigned irq)
436{
72146104
IC
437 /* Legacy IRQ descriptors are managed by the arch. */
438 if (irq < NR_IRQS_LEGACY)
439 return;
440
c9df1ce5
IC
441 irq_free_desc(irq);
442}
443
d46a78b0
JF
444static void pirq_unmask_notify(int irq)
445{
7a043f11 446 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
447
448 if (unlikely(pirq_needs_eoi(irq))) {
449 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
450 WARN_ON(rc);
451 }
452}
453
454static void pirq_query_unmask(int irq)
455{
456 struct physdev_irq_status_query irq_status;
457 struct irq_info *info = info_for_irq(irq);
458
459 BUG_ON(info->type != IRQT_PIRQ);
460
7a043f11 461 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
462 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
463 irq_status.flags = 0;
464
465 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
466 if (irq_status.flags & XENIRQSTAT_needs_eoi)
467 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
468}
469
470static bool probing_irq(int irq)
471{
472 struct irq_desc *desc = irq_to_desc(irq);
473
474 return desc && desc->action == NULL;
475}
476
c9e265e0 477static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
478{
479 struct evtchn_bind_pirq bind_pirq;
480 struct irq_info *info = info_for_irq(irq);
481 int evtchn = evtchn_from_irq(irq);
15ebbb82 482 int rc;
d46a78b0
JF
483
484 BUG_ON(info->type != IRQT_PIRQ);
485
486 if (VALID_EVTCHN(evtchn))
487 goto out;
488
7a043f11 489 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 490 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
491 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
492 BIND_PIRQ__WILL_SHARE : 0;
493 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
494 if (rc != 0) {
d46a78b0
JF
495 if (!probing_irq(irq))
496 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
497 irq);
498 return 0;
499 }
500 evtchn = bind_pirq.port;
501
502 pirq_query_unmask(irq);
503
504 evtchn_to_irq[evtchn] = irq;
505 bind_evtchn_to_cpu(evtchn, 0);
506 info->evtchn = evtchn;
507
508out:
509 unmask_evtchn(evtchn);
510 pirq_unmask_notify(irq);
511
512 return 0;
513}
514
c9e265e0
TG
515static unsigned int startup_pirq(struct irq_data *data)
516{
517 return __startup_pirq(data->irq);
518}
519
520static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
521{
522 struct evtchn_close close;
c9e265e0 523 unsigned int irq = data->irq;
d46a78b0
JF
524 struct irq_info *info = info_for_irq(irq);
525 int evtchn = evtchn_from_irq(irq);
526
527 BUG_ON(info->type != IRQT_PIRQ);
528
529 if (!VALID_EVTCHN(evtchn))
530 return;
531
532 mask_evtchn(evtchn);
533
534 close.port = evtchn;
535 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
536 BUG();
537
538 bind_evtchn_to_cpu(evtchn, 0);
539 evtchn_to_irq[evtchn] = -1;
540 info->evtchn = 0;
541}
542
c9e265e0 543static void enable_pirq(struct irq_data *data)
d46a78b0 544{
c9e265e0 545 startup_pirq(data);
d46a78b0
JF
546}
547
c9e265e0 548static void disable_pirq(struct irq_data *data)
d46a78b0
JF
549{
550}
551
c9e265e0 552static void ack_pirq(struct irq_data *data)
d46a78b0 553{
c9e265e0 554 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 555
aa673c1c 556 move_native_irq(data->irq);
d46a78b0
JF
557
558 if (VALID_EVTCHN(evtchn)) {
559 mask_evtchn(evtchn);
560 clear_evtchn(evtchn);
561 }
562}
563
d46a78b0
JF
564static int find_irq_by_gsi(unsigned gsi)
565{
566 int irq;
567
b21ddbf5 568 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
569 struct irq_info *info = info_for_irq(irq);
570
571 if (info == NULL || info->type != IRQT_PIRQ)
572 continue;
573
574 if (gsi_from_irq(irq) == gsi)
575 return irq;
576 }
577
578 return -1;
579}
580
7a043f11
SS
581int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
582{
583 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
584}
585
586/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
587 * consequence don't assume that the irq number returned has a low value
588 * or can be used as a pirq number unless you know otherwise.
589 *
7a043f11 590 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 591 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
592 * matches the gsi number passed as second argument.
593 *
594 * Note: We don't assign an event channel until the irq actually started
595 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 596 */
7a043f11 597int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 598{
7a043f11 599 int irq = 0;
d46a78b0
JF
600 struct physdev_irq irq_op;
601
602 spin_lock(&irq_mapping_update_lock);
603
e5fc7345 604 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 605 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
606 pirq > nr_irqs ? "pirq" :"",
607 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
608 goto out;
609 }
610
d46a78b0
JF
611 irq = find_irq_by_gsi(gsi);
612 if (irq != -1) {
7a043f11 613 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
614 irq, gsi);
615 goto out; /* XXX need refcount? */
616 }
617
c9df1ce5 618 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
619
620 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 621 handle_level_irq, name);
d46a78b0
JF
622
623 irq_op.irq = irq;
b5401a96
AN
624 irq_op.vector = 0;
625
626 /* Only the privileged domain can do this. For non-priv, the pcifront
627 * driver provides a PCI bus that does the call to do exactly
628 * this in the priv domain. */
629 if (xen_initial_domain() &&
630 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 631 xen_free_irq(irq);
d46a78b0
JF
632 irq = -ENOSPC;
633 goto out;
634 }
635
7a043f11 636 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 637 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 638 pirq_to_irq[pirq] = irq;
d46a78b0
JF
639
640out:
641 spin_unlock(&irq_mapping_update_lock);
642
643 return irq;
644}
645
f731e3ef
QH
646#ifdef CONFIG_PCI_MSI
647#include <linux/msi.h>
648#include "../pci/msi.h"
649
cbf6aa89
IC
650static int find_unbound_pirq(int type)
651{
652 int rc, i;
653 struct physdev_get_free_pirq op_get_free_pirq;
654 op_get_free_pirq.type = type;
655
656 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
657 if (!rc)
658 return op_get_free_pirq.pirq;
659
660 for (i = 0; i < nr_irqs; i++) {
661 if (pirq_to_irq[i] < 0)
662 return i;
663 }
664 return -1;
665}
666
af42b8d1 667void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc)
809f9267
SS
668{
669 spin_lock(&irq_mapping_update_lock);
670
af42b8d1 671 if (alloc & XEN_ALLOC_IRQ) {
c9df1ce5 672 *irq = xen_allocate_irq_dynamic();
af42b8d1
SS
673 if (*irq == -1)
674 goto out;
675 }
809f9267 676
af42b8d1
SS
677 if (alloc & XEN_ALLOC_PIRQ) {
678 *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
ae1635b0
IC
679 if (*pirq == -1) {
680 xen_free_irq(*irq);
681 *irq = -1;
af42b8d1 682 goto out;
ae1635b0 683 }
af42b8d1 684 }
809f9267
SS
685
686 set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
687 handle_level_irq, name);
688
689 irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
690 pirq_to_irq[*pirq] = *irq;
691
692out:
693 spin_unlock(&irq_mapping_update_lock);
694}
695
f731e3ef
QH
696int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
697{
698 int irq = -1;
699 struct physdev_map_pirq map_irq;
700 int rc;
701 int pos;
702 u32 table_offset, bir;
703
704 memset(&map_irq, 0, sizeof(map_irq));
705 map_irq.domid = DOMID_SELF;
706 map_irq.type = MAP_PIRQ_TYPE_MSI;
707 map_irq.index = -1;
708 map_irq.pirq = -1;
709 map_irq.bus = dev->bus->number;
710 map_irq.devfn = dev->devfn;
711
712 if (type == PCI_CAP_ID_MSIX) {
713 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
714
715 pci_read_config_dword(dev, msix_table_offset_reg(pos),
716 &table_offset);
717 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
718
719 map_irq.table_base = pci_resource_start(dev, bir);
720 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
721 }
722
723 spin_lock(&irq_mapping_update_lock);
724
c9df1ce5 725 irq = xen_allocate_irq_dynamic();
f731e3ef
QH
726
727 if (irq == -1)
728 goto out;
729
730 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
731 if (rc) {
732 printk(KERN_WARNING "xen map irq failed %d\n", rc);
733
c9df1ce5 734 xen_free_irq(irq);
f731e3ef
QH
735
736 irq = -1;
737 goto out;
738 }
739 irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
740
741 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
742 handle_level_irq,
743 (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
744
745out:
746 spin_unlock(&irq_mapping_update_lock);
747 return irq;
748}
749#endif
750
b5401a96
AN
751int xen_destroy_irq(int irq)
752{
753 struct irq_desc *desc;
38aa66fc
JF
754 struct physdev_unmap_pirq unmap_irq;
755 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
756 int rc = -ENOENT;
757
758 spin_lock(&irq_mapping_update_lock);
759
760 desc = irq_to_desc(irq);
761 if (!desc)
762 goto out;
763
38aa66fc 764 if (xen_initial_domain()) {
12334715 765 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
766 unmap_irq.domid = DOMID_SELF;
767 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
768 if (rc) {
769 printk(KERN_WARNING "unmap irq failed %d\n", rc);
770 goto out;
771 }
772 }
1aa0b51a
KRW
773 pirq_to_irq[info->u.pirq.pirq] = -1;
774
b5401a96
AN
775 irq_info[irq] = mk_unbound_info();
776
c9df1ce5 777 xen_free_irq(irq);
b5401a96
AN
778
779out:
780 spin_unlock(&irq_mapping_update_lock);
781 return rc;
782}
783
d46a78b0
JF
784int xen_vector_from_irq(unsigned irq)
785{
786 return vector_from_irq(irq);
787}
788
789int xen_gsi_from_irq(unsigned irq)
790{
791 return gsi_from_irq(irq);
e46cdb66
JF
792}
793
af42b8d1
SS
794int xen_irq_from_pirq(unsigned pirq)
795{
796 return pirq_to_irq[pirq];
797}
798
b536b4b9 799int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
800{
801 int irq;
802
803 spin_lock(&irq_mapping_update_lock);
804
805 irq = evtchn_to_irq[evtchn];
806
807 if (irq == -1) {
c9df1ce5 808 irq = xen_allocate_irq_dynamic();
e46cdb66 809
e46cdb66 810 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 811 handle_fasteoi_irq, "event");
e46cdb66
JF
812
813 evtchn_to_irq[evtchn] = irq;
ced40d0f 814 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
815 }
816
e46cdb66
JF
817 spin_unlock(&irq_mapping_update_lock);
818
819 return irq;
820}
b536b4b9 821EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 822
f87e4cac
JF
823static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
824{
825 struct evtchn_bind_ipi bind_ipi;
826 int evtchn, irq;
827
828 spin_lock(&irq_mapping_update_lock);
829
830 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 831
f87e4cac 832 if (irq == -1) {
c9df1ce5 833 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
834 if (irq < 0)
835 goto out;
836
aaca4964
JF
837 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
838 handle_percpu_irq, "ipi");
f87e4cac
JF
839
840 bind_ipi.vcpu = cpu;
841 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
842 &bind_ipi) != 0)
843 BUG();
844 evtchn = bind_ipi.port;
845
846 evtchn_to_irq[evtchn] = irq;
ced40d0f 847 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
848 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
849
850 bind_evtchn_to_cpu(evtchn, cpu);
851 }
852
f87e4cac
JF
853 out:
854 spin_unlock(&irq_mapping_update_lock);
855 return irq;
856}
857
858
4fe7d5a7 859int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
860{
861 struct evtchn_bind_virq bind_virq;
862 int evtchn, irq;
863
864 spin_lock(&irq_mapping_update_lock);
865
866 irq = per_cpu(virq_to_irq, cpu)[virq];
867
868 if (irq == -1) {
c9df1ce5 869 irq = xen_allocate_irq_dynamic();
a52521f1
JF
870
871 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
872 handle_percpu_irq, "virq");
873
e46cdb66
JF
874 bind_virq.virq = virq;
875 bind_virq.vcpu = cpu;
876 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
877 &bind_virq) != 0)
878 BUG();
879 evtchn = bind_virq.port;
880
e46cdb66 881 evtchn_to_irq[evtchn] = irq;
ced40d0f 882 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
883
884 per_cpu(virq_to_irq, cpu)[virq] = irq;
885
886 bind_evtchn_to_cpu(evtchn, cpu);
887 }
888
e46cdb66
JF
889 spin_unlock(&irq_mapping_update_lock);
890
891 return irq;
892}
893
894static void unbind_from_irq(unsigned int irq)
895{
896 struct evtchn_close close;
897 int evtchn = evtchn_from_irq(irq);
898
899 spin_lock(&irq_mapping_update_lock);
900
d77bbd4d 901 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
902 close.port = evtchn;
903 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
904 BUG();
905
906 switch (type_from_irq(irq)) {
907 case IRQT_VIRQ:
908 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 909 [virq_from_irq(irq)] = -1;
e46cdb66 910 break;
d68d82af
AN
911 case IRQT_IPI:
912 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 913 [ipi_from_irq(irq)] = -1;
d68d82af 914 break;
e46cdb66
JF
915 default:
916 break;
917 }
918
919 /* Closed ports are implicitly re-bound to VCPU0. */
920 bind_evtchn_to_cpu(evtchn, 0);
921
922 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
923 }
924
925 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 926 irq_info[irq] = mk_unbound_info();
e46cdb66 927
c9df1ce5 928 xen_free_irq(irq);
e46cdb66
JF
929 }
930
931 spin_unlock(&irq_mapping_update_lock);
932}
933
934int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 935 irq_handler_t handler,
e46cdb66
JF
936 unsigned long irqflags,
937 const char *devname, void *dev_id)
938{
939 unsigned int irq;
940 int retval;
941
942 irq = bind_evtchn_to_irq(evtchn);
943 retval = request_irq(irq, handler, irqflags, devname, dev_id);
944 if (retval != 0) {
945 unbind_from_irq(irq);
946 return retval;
947 }
948
949 return irq;
950}
951EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
952
953int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 954 irq_handler_t handler,
e46cdb66
JF
955 unsigned long irqflags, const char *devname, void *dev_id)
956{
957 unsigned int irq;
958 int retval;
959
960 irq = bind_virq_to_irq(virq, cpu);
961 retval = request_irq(irq, handler, irqflags, devname, dev_id);
962 if (retval != 0) {
963 unbind_from_irq(irq);
964 return retval;
965 }
966
967 return irq;
968}
969EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
970
f87e4cac
JF
971int bind_ipi_to_irqhandler(enum ipi_vector ipi,
972 unsigned int cpu,
973 irq_handler_t handler,
974 unsigned long irqflags,
975 const char *devname,
976 void *dev_id)
977{
978 int irq, retval;
979
980 irq = bind_ipi_to_irq(ipi, cpu);
981 if (irq < 0)
982 return irq;
983
676dc3cf 984 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
985 retval = request_irq(irq, handler, irqflags, devname, dev_id);
986 if (retval != 0) {
987 unbind_from_irq(irq);
988 return retval;
989 }
990
991 return irq;
992}
993
e46cdb66
JF
994void unbind_from_irqhandler(unsigned int irq, void *dev_id)
995{
996 free_irq(irq, dev_id);
997 unbind_from_irq(irq);
998}
999EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1000
f87e4cac
JF
1001void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1002{
1003 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1004 BUG_ON(irq < 0);
1005 notify_remote_via_irq(irq);
1006}
1007
ee523ca1
JF
1008irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1009{
1010 struct shared_info *sh = HYPERVISOR_shared_info;
1011 int cpu = smp_processor_id();
cb52e6d9 1012 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
1013 int i;
1014 unsigned long flags;
1015 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1016 struct vcpu_info *v;
ee523ca1
JF
1017
1018 spin_lock_irqsave(&debug_lock, flags);
1019
cb52e6d9 1020 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1021
1022 for_each_online_cpu(i) {
cb52e6d9
IC
1023 int pending;
1024 v = per_cpu(xen_vcpu, i);
1025 pending = (get_irq_regs() && i == cpu)
1026 ? xen_irqs_disabled(get_irq_regs())
1027 : v->evtchn_upcall_mask;
1028 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1029 pending, v->evtchn_upcall_pending,
1030 (int)(sizeof(v->evtchn_pending_sel)*2),
1031 v->evtchn_pending_sel);
1032 }
1033 v = per_cpu(xen_vcpu, cpu);
1034
1035 printk("\npending:\n ");
1036 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1037 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1038 sh->evtchn_pending[i],
1039 i % 8 == 0 ? "\n " : " ");
1040 printk("\nglobal mask:\n ");
1041 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1042 printk("%0*lx%s",
1043 (int)(sizeof(sh->evtchn_mask[0])*2),
1044 sh->evtchn_mask[i],
1045 i % 8 == 0 ? "\n " : " ");
1046
1047 printk("\nglobally unmasked:\n ");
1048 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1049 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1050 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1051 i % 8 == 0 ? "\n " : " ");
1052
1053 printk("\nlocal cpu%d mask:\n ", cpu);
1054 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1055 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1056 cpu_evtchn[i],
1057 i % 8 == 0 ? "\n " : " ");
1058
1059 printk("\nlocally unmasked:\n ");
1060 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1061 unsigned long pending = sh->evtchn_pending[i]
1062 & ~sh->evtchn_mask[i]
1063 & cpu_evtchn[i];
1064 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1065 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1066 }
ee523ca1
JF
1067
1068 printk("\npending list:\n");
cb52e6d9 1069 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1070 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1071 int word_idx = i / BITS_PER_LONG;
1072 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1073 cpu_from_evtchn(i), i,
cb52e6d9
IC
1074 evtchn_to_irq[i],
1075 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1076 ? "" : " l2-clear",
1077 !sync_test_bit(i, sh->evtchn_mask)
1078 ? "" : " globally-masked",
1079 sync_test_bit(i, cpu_evtchn)
1080 ? "" : " locally-masked");
ee523ca1
JF
1081 }
1082 }
1083
1084 spin_unlock_irqrestore(&debug_lock, flags);
1085
1086 return IRQ_HANDLED;
1087}
1088
245b2e70
TH
1089static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1090
e46cdb66
JF
1091/*
1092 * Search the CPUs pending events bitmasks. For each one found, map
1093 * the event number to an irq, and feed it into do_IRQ() for
1094 * handling.
1095 *
1096 * Xen uses a two-level bitmap to speed searching. The first level is
1097 * a bitset of words which contain pending event bits. The second
1098 * level is a bitset of pending events themselves.
1099 */
38e20b07 1100static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1101{
1102 int cpu = get_cpu();
1103 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1104 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1105 unsigned count;
e46cdb66 1106
229664be
JF
1107 do {
1108 unsigned long pending_words;
e46cdb66 1109
229664be 1110 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1111
b2e4ae69 1112 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1113 goto out;
e46cdb66 1114
e849c3e9
IY
1115#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1116 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1117 wmb();
e849c3e9 1118#endif
229664be
JF
1119 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1120 while (pending_words != 0) {
1121 unsigned long pending_bits;
1122 int word_idx = __ffs(pending_words);
1123 pending_words &= ~(1UL << word_idx);
1124
1125 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1126 int bit_idx = __ffs(pending_bits);
1127 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1128 int irq = evtchn_to_irq[port];
ca4dbc66 1129 struct irq_desc *desc;
229664be 1130
3588fe2e
JF
1131 mask_evtchn(port);
1132 clear_evtchn(port);
1133
ca4dbc66
EB
1134 if (irq != -1) {
1135 desc = irq_to_desc(irq);
1136 if (desc)
1137 generic_handle_irq_desc(irq, desc);
1138 }
e46cdb66
JF
1139 }
1140 }
e46cdb66 1141
229664be
JF
1142 BUG_ON(!irqs_disabled());
1143
780f36d8
CL
1144 count = __this_cpu_read(xed_nesting_count);
1145 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1146 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1147
1148out:
38e20b07
SY
1149
1150 put_cpu();
1151}
1152
1153void xen_evtchn_do_upcall(struct pt_regs *regs)
1154{
1155 struct pt_regs *old_regs = set_irq_regs(regs);
1156
1157 exit_idle();
1158 irq_enter();
1159
1160 __xen_evtchn_do_upcall();
1161
3445a8fd
JF
1162 irq_exit();
1163 set_irq_regs(old_regs);
38e20b07 1164}
3445a8fd 1165
38e20b07
SY
1166void xen_hvm_evtchn_do_upcall(void)
1167{
1168 __xen_evtchn_do_upcall();
e46cdb66 1169}
183d03cc 1170EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1171
eb1e305f
JF
1172/* Rebind a new event channel to an existing irq. */
1173void rebind_evtchn_irq(int evtchn, int irq)
1174{
d77bbd4d
JF
1175 struct irq_info *info = info_for_irq(irq);
1176
eb1e305f
JF
1177 /* Make sure the irq is masked, since the new event channel
1178 will also be masked. */
1179 disable_irq(irq);
1180
1181 spin_lock(&irq_mapping_update_lock);
1182
1183 /* After resume the irq<->evtchn mappings are all cleared out */
1184 BUG_ON(evtchn_to_irq[evtchn] != -1);
1185 /* Expect irq to have been bound before,
d77bbd4d
JF
1186 so there should be a proper type */
1187 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1188
1189 evtchn_to_irq[evtchn] = irq;
ced40d0f 1190 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1191
1192 spin_unlock(&irq_mapping_update_lock);
1193
1194 /* new event channels are always bound to cpu 0 */
0de26520 1195 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1196
1197 /* Unmask the event channel. */
1198 enable_irq(irq);
1199}
1200
e46cdb66 1201/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1202static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1203{
1204 struct evtchn_bind_vcpu bind_vcpu;
1205 int evtchn = evtchn_from_irq(irq);
1206
183d03cc
SS
1207 /* events delivered via platform PCI interrupts are always
1208 * routed to vcpu 0 */
1209 if (!VALID_EVTCHN(evtchn) ||
1210 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1211 return -1;
e46cdb66
JF
1212
1213 /* Send future instances of this interrupt to other vcpu. */
1214 bind_vcpu.port = evtchn;
1215 bind_vcpu.vcpu = tcpu;
1216
1217 /*
1218 * If this fails, it usually just indicates that we're dealing with a
1219 * virq or IPI channel, which don't actually need to be rebound. Ignore
1220 * it, but don't do the xenlinux-level rebind in that case.
1221 */
1222 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1223 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1224
d5dedd45
YL
1225 return 0;
1226}
e46cdb66 1227
c9e265e0
TG
1228static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1229 bool force)
e46cdb66 1230{
0de26520 1231 unsigned tcpu = cpumask_first(dest);
d5dedd45 1232
c9e265e0 1233 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1234}
1235
642e0c88
IY
1236int resend_irq_on_evtchn(unsigned int irq)
1237{
1238 int masked, evtchn = evtchn_from_irq(irq);
1239 struct shared_info *s = HYPERVISOR_shared_info;
1240
1241 if (!VALID_EVTCHN(evtchn))
1242 return 1;
1243
1244 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1245 sync_set_bit(evtchn, s->evtchn_pending);
1246 if (!masked)
1247 unmask_evtchn(evtchn);
1248
1249 return 1;
1250}
1251
c9e265e0 1252static void enable_dynirq(struct irq_data *data)
e46cdb66 1253{
c9e265e0 1254 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1255
1256 if (VALID_EVTCHN(evtchn))
1257 unmask_evtchn(evtchn);
1258}
1259
c9e265e0 1260static void disable_dynirq(struct irq_data *data)
e46cdb66 1261{
c9e265e0 1262 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1263
1264 if (VALID_EVTCHN(evtchn))
1265 mask_evtchn(evtchn);
1266}
1267
c9e265e0 1268static void ack_dynirq(struct irq_data *data)
e46cdb66 1269{
c9e265e0 1270 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1271
c9e265e0 1272 move_masked_irq(data->irq);
e46cdb66
JF
1273
1274 if (VALID_EVTCHN(evtchn))
3588fe2e 1275 unmask_evtchn(evtchn);
e46cdb66
JF
1276}
1277
c9e265e0 1278static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1279{
c9e265e0 1280 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1281 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1282 int ret = 0;
1283
1284 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1285 int masked;
1286
1287 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1288 sync_set_bit(evtchn, sh->evtchn_pending);
1289 if (!masked)
1290 unmask_evtchn(evtchn);
e46cdb66
JF
1291 ret = 1;
1292 }
1293
1294 return ret;
1295}
1296
9a069c33
SS
1297static void restore_cpu_pirqs(void)
1298{
1299 int pirq, rc, irq, gsi;
1300 struct physdev_map_pirq map_irq;
1301
1302 for (pirq = 0; pirq < nr_irqs; pirq++) {
1303 irq = pirq_to_irq[pirq];
1304 if (irq == -1)
1305 continue;
1306
1307 /* save/restore of PT devices doesn't work, so at this point the
1308 * only devices present are GSI based emulated devices */
1309 gsi = gsi_from_irq(irq);
1310 if (!gsi)
1311 continue;
1312
1313 map_irq.domid = DOMID_SELF;
1314 map_irq.type = MAP_PIRQ_TYPE_GSI;
1315 map_irq.index = gsi;
1316 map_irq.pirq = pirq;
1317
1318 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1319 if (rc) {
1320 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1321 gsi, irq, pirq, rc);
1322 irq_info[irq] = mk_unbound_info();
1323 pirq_to_irq[pirq] = -1;
1324 continue;
1325 }
1326
1327 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1328
c9e265e0 1329 __startup_pirq(irq);
9a069c33
SS
1330 }
1331}
1332
0e91398f
JF
1333static void restore_cpu_virqs(unsigned int cpu)
1334{
1335 struct evtchn_bind_virq bind_virq;
1336 int virq, irq, evtchn;
1337
1338 for (virq = 0; virq < NR_VIRQS; virq++) {
1339 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1340 continue;
1341
ced40d0f 1342 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1343
1344 /* Get a new binding from Xen. */
1345 bind_virq.virq = virq;
1346 bind_virq.vcpu = cpu;
1347 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1348 &bind_virq) != 0)
1349 BUG();
1350 evtchn = bind_virq.port;
1351
1352 /* Record the new mapping. */
1353 evtchn_to_irq[evtchn] = irq;
ced40d0f 1354 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1355 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1356 }
1357}
1358
1359static void restore_cpu_ipis(unsigned int cpu)
1360{
1361 struct evtchn_bind_ipi bind_ipi;
1362 int ipi, irq, evtchn;
1363
1364 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1365 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1366 continue;
1367
ced40d0f 1368 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1369
1370 /* Get a new binding from Xen. */
1371 bind_ipi.vcpu = cpu;
1372 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1373 &bind_ipi) != 0)
1374 BUG();
1375 evtchn = bind_ipi.port;
1376
1377 /* Record the new mapping. */
1378 evtchn_to_irq[evtchn] = irq;
ced40d0f 1379 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1380 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1381 }
1382}
1383
2d9e1e2f
JF
1384/* Clear an irq's pending state, in preparation for polling on it */
1385void xen_clear_irq_pending(int irq)
1386{
1387 int evtchn = evtchn_from_irq(irq);
1388
1389 if (VALID_EVTCHN(evtchn))
1390 clear_evtchn(evtchn);
1391}
d9a8814f 1392EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1393void xen_set_irq_pending(int irq)
1394{
1395 int evtchn = evtchn_from_irq(irq);
1396
1397 if (VALID_EVTCHN(evtchn))
1398 set_evtchn(evtchn);
1399}
1400
1401bool xen_test_irq_pending(int irq)
1402{
1403 int evtchn = evtchn_from_irq(irq);
1404 bool ret = false;
1405
1406 if (VALID_EVTCHN(evtchn))
1407 ret = test_evtchn(evtchn);
1408
1409 return ret;
1410}
1411
d9a8814f
KRW
1412/* Poll waiting for an irq to become pending with timeout. In the usual case,
1413 * the irq will be disabled so it won't deliver an interrupt. */
1414void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1415{
1416 evtchn_port_t evtchn = evtchn_from_irq(irq);
1417
1418 if (VALID_EVTCHN(evtchn)) {
1419 struct sched_poll poll;
1420
1421 poll.nr_ports = 1;
d9a8814f 1422 poll.timeout = timeout;
ff3c5362 1423 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1424
1425 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1426 BUG();
1427 }
1428}
d9a8814f
KRW
1429EXPORT_SYMBOL(xen_poll_irq_timeout);
1430/* Poll waiting for an irq to become pending. In the usual case, the
1431 * irq will be disabled so it won't deliver an interrupt. */
1432void xen_poll_irq(int irq)
1433{
1434 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1435}
2d9e1e2f 1436
0e91398f
JF
1437void xen_irq_resume(void)
1438{
1439 unsigned int cpu, irq, evtchn;
1440
1441 init_evtchn_cpu_bindings();
1442
1443 /* New event-channel space is not 'live' yet. */
1444 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1445 mask_evtchn(evtchn);
1446
1447 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1448 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1449 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1450
1451 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1452 evtchn_to_irq[evtchn] = -1;
1453
1454 for_each_possible_cpu(cpu) {
1455 restore_cpu_virqs(cpu);
1456 restore_cpu_ipis(cpu);
1457 }
6903591f 1458
9a069c33 1459 restore_cpu_pirqs();
0e91398f
JF
1460}
1461
e46cdb66 1462static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1463 .name = "xen-dyn",
54a353a0 1464
c9e265e0
TG
1465 .irq_disable = disable_dynirq,
1466 .irq_mask = disable_dynirq,
1467 .irq_unmask = enable_dynirq,
54a353a0 1468
c9e265e0
TG
1469 .irq_eoi = ack_dynirq,
1470 .irq_set_affinity = set_affinity_irq,
1471 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1472};
1473
d46a78b0 1474static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1475 .name = "xen-pirq",
d46a78b0 1476
c9e265e0
TG
1477 .irq_startup = startup_pirq,
1478 .irq_shutdown = shutdown_pirq,
d46a78b0 1479
c9e265e0
TG
1480 .irq_enable = enable_pirq,
1481 .irq_unmask = enable_pirq,
d46a78b0 1482
c9e265e0
TG
1483 .irq_disable = disable_pirq,
1484 .irq_mask = disable_pirq,
d46a78b0 1485
c9e265e0 1486 .irq_ack = ack_pirq,
d46a78b0 1487
c9e265e0 1488 .irq_set_affinity = set_affinity_irq,
d46a78b0 1489
c9e265e0 1490 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1491};
1492
aaca4964 1493static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1494 .name = "xen-percpu",
aaca4964 1495
c9e265e0
TG
1496 .irq_disable = disable_dynirq,
1497 .irq_mask = disable_dynirq,
1498 .irq_unmask = enable_dynirq,
aaca4964 1499
c9e265e0 1500 .irq_ack = ack_dynirq,
aaca4964
JF
1501};
1502
38e20b07
SY
1503int xen_set_callback_via(uint64_t via)
1504{
1505 struct xen_hvm_param a;
1506 a.domid = DOMID_SELF;
1507 a.index = HVM_PARAM_CALLBACK_IRQ;
1508 a.value = via;
1509 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1510}
1511EXPORT_SYMBOL_GPL(xen_set_callback_via);
1512
ca65f9fc 1513#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1514/* Vector callbacks are better than PCI interrupts to receive event
1515 * channel notifications because we can receive vector callbacks on any
1516 * vcpu and we don't need PCI support or APIC interactions. */
1517void xen_callback_vector(void)
1518{
1519 int rc;
1520 uint64_t callback_via;
1521 if (xen_have_vector_callback) {
1522 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1523 rc = xen_set_callback_via(callback_via);
1524 if (rc) {
1525 printk(KERN_ERR "Request for Xen HVM callback vector"
1526 " failed.\n");
1527 xen_have_vector_callback = 0;
1528 return;
1529 }
1530 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1531 "enabled\n");
1532 /* in the restore case the vector has already been allocated */
1533 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1534 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1535 }
1536}
ca65f9fc
SS
1537#else
1538void xen_callback_vector(void) {}
1539#endif
38e20b07 1540
e46cdb66
JF
1541void __init xen_init_IRQ(void)
1542{
e5fc7345 1543 int i;
c7a3589e 1544
a70c352a
PE
1545 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1546 GFP_KERNEL);
b21ddbf5
JF
1547 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1548
e5fc7345
SS
1549 /* We are using nr_irqs as the maximum number of pirq available but
1550 * that number is actually chosen by Xen and we don't know exactly
1551 * what it is. Be careful choosing high pirq numbers. */
1552 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1553 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1554 pirq_to_irq[i] = -1;
1555
b21ddbf5
JF
1556 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1557 GFP_KERNEL);
1558 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1559 evtchn_to_irq[i] = -1;
e46cdb66
JF
1560
1561 init_evtchn_cpu_bindings();
1562
1563 /* No event channels are 'live' right now. */
1564 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1565 mask_evtchn(i);
1566
38e20b07
SY
1567 if (xen_hvm_domain()) {
1568 xen_callback_vector();
1569 native_init_IRQ();
3942b740
SS
1570 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1571 * __acpi_register_gsi can point at the right function */
1572 pci_xen_hvm_init();
38e20b07
SY
1573 } else {
1574 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1575 if (xen_initial_domain())
1576 xen_setup_pirqs();
38e20b07 1577 }
e46cdb66 1578}