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xen: Switch to new irq_chip functions
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CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
110e7c7e
JJ
173 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
174 return 0;
175
ced40d0f 176 return info_for_irq(irq)->evtchn;
e46cdb66
JF
177}
178
d4c04536
IC
179unsigned irq_from_evtchn(unsigned int evtchn)
180{
181 return evtchn_to_irq[evtchn];
182}
183EXPORT_SYMBOL_GPL(irq_from_evtchn);
184
ced40d0f 185static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 186{
ced40d0f
JF
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_IPI);
191
192 return info->u.ipi;
193}
194
195static unsigned virq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_VIRQ);
201
202 return info->u.virq;
203}
204
7a043f11
SS
205static unsigned pirq_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.pirq;
213}
214
ced40d0f
JF
215static unsigned gsi_from_irq(unsigned irq)
216{
217 struct irq_info *info = info_for_irq(irq);
218
219 BUG_ON(info == NULL);
220 BUG_ON(info->type != IRQT_PIRQ);
221
222 return info->u.pirq.gsi;
223}
224
225static unsigned vector_from_irq(unsigned irq)
226{
227 struct irq_info *info = info_for_irq(irq);
228
229 BUG_ON(info == NULL);
230 BUG_ON(info->type != IRQT_PIRQ);
231
232 return info->u.pirq.vector;
233}
234
235static enum xen_irq_type type_from_irq(unsigned irq)
236{
237 return info_for_irq(irq)->type;
238}
239
240static unsigned cpu_from_irq(unsigned irq)
241{
242 return info_for_irq(irq)->cpu;
243}
244
245static unsigned int cpu_from_evtchn(unsigned int evtchn)
246{
247 int irq = evtchn_to_irq[evtchn];
248 unsigned ret = 0;
249
250 if (irq != -1)
251 ret = cpu_from_irq(irq);
252
253 return ret;
e46cdb66
JF
254}
255
d46a78b0
JF
256static bool pirq_needs_eoi(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info->type != IRQT_PIRQ);
261
262 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
263}
264
e46cdb66
JF
265static inline unsigned long active_evtchns(unsigned int cpu,
266 struct shared_info *sh,
267 unsigned int idx)
268{
269 return (sh->evtchn_pending[idx] &
c7a3589e 270 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
271 ~sh->evtchn_mask[idx]);
272}
273
274static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
275{
276 int irq = evtchn_to_irq[chn];
277
278 BUG_ON(irq == -1);
279#ifdef CONFIG_SMP
c9e265e0 280 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
281#endif
282
e0419564
JF
283 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
284 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 285
ced40d0f 286 irq_info[irq].cpu = cpu;
e46cdb66
JF
287}
288
289static void init_evtchn_cpu_bindings(void)
290{
1c6969ec 291 int i;
e46cdb66 292#ifdef CONFIG_SMP
10e58084 293 struct irq_desc *desc;
10e58084 294
e46cdb66 295 /* By default all event channels notify CPU#0. */
0b8f1efa 296 for_each_irq_desc(i, desc) {
c9e265e0 297 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 298 }
e46cdb66
JF
299#endif
300
1c6969ec
JB
301 for_each_possible_cpu(i)
302 memset(cpu_evtchn_mask(i),
303 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
304
e46cdb66
JF
305}
306
e46cdb66
JF
307static inline void clear_evtchn(int port)
308{
309 struct shared_info *s = HYPERVISOR_shared_info;
310 sync_clear_bit(port, &s->evtchn_pending[0]);
311}
312
313static inline void set_evtchn(int port)
314{
315 struct shared_info *s = HYPERVISOR_shared_info;
316 sync_set_bit(port, &s->evtchn_pending[0]);
317}
318
168d2f46
JF
319static inline int test_evtchn(int port)
320{
321 struct shared_info *s = HYPERVISOR_shared_info;
322 return sync_test_bit(port, &s->evtchn_pending[0]);
323}
324
e46cdb66
JF
325
326/**
327 * notify_remote_via_irq - send event to remote end of event channel via irq
328 * @irq: irq of event channel to send event to
329 *
330 * Unlike notify_remote_via_evtchn(), this is safe to use across
331 * save/restore. Notifications on a broken connection are silently
332 * dropped.
333 */
334void notify_remote_via_irq(int irq)
335{
336 int evtchn = evtchn_from_irq(irq);
337
338 if (VALID_EVTCHN(evtchn))
339 notify_remote_via_evtchn(evtchn);
340}
341EXPORT_SYMBOL_GPL(notify_remote_via_irq);
342
343static void mask_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
346 sync_set_bit(port, &s->evtchn_mask[0]);
347}
348
349static void unmask_evtchn(int port)
350{
351 struct shared_info *s = HYPERVISOR_shared_info;
352 unsigned int cpu = get_cpu();
353
354 BUG_ON(!irqs_disabled());
355
356 /* Slow path (hypercall) if this is a non-local port. */
357 if (unlikely(cpu != cpu_from_evtchn(port))) {
358 struct evtchn_unmask unmask = { .port = port };
359 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
360 } else {
780f36d8 361 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
362
363 sync_clear_bit(port, &s->evtchn_mask[0]);
364
365 /*
366 * The following is basically the equivalent of
367 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
368 * the interrupt edge' if the channel is masked.
369 */
370 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
371 !sync_test_and_set_bit(port / BITS_PER_LONG,
372 &vcpu_info->evtchn_pending_sel))
373 vcpu_info->evtchn_upcall_pending = 1;
374 }
375
376 put_cpu();
377}
378
89911501 379static int xen_allocate_irq_dynamic(void)
0794bfc7 380{
89911501
IC
381 int first = 0;
382 int irq;
0794bfc7
KRW
383
384#ifdef CONFIG_X86_IO_APIC
89911501
IC
385 /*
386 * For an HVM guest or domain 0 which see "real" (emulated or
387 * actual repectively) GSIs we allocate dynamic IRQs
388 * e.g. those corresponding to event channels or MSIs
389 * etc. from the range above those "real" GSIs to avoid
390 * collisions.
391 */
392 if (xen_initial_domain() || xen_hvm_domain())
393 first = get_nr_irqs_gsi();
0794bfc7
KRW
394#endif
395
89911501
IC
396retry:
397 irq = irq_alloc_desc_from(first, -1);
3a69e916 398
89911501
IC
399 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
400 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
401 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
402 goto retry;
99ad198c 403 }
e46cdb66 404
89911501
IC
405 if (irq < 0)
406 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 407
e46cdb66 408 return irq;
d46a78b0
JF
409}
410
c9df1ce5
IC
411static int xen_allocate_irq_gsi(unsigned gsi)
412{
413 int irq;
414
89911501
IC
415 /*
416 * A PV guest has no concept of a GSI (since it has no ACPI
417 * nor access to/knowledge of the physical APICs). Therefore
418 * all IRQs are dynamically allocated from the entire IRQ
419 * space.
420 */
421 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
422 return xen_allocate_irq_dynamic();
423
424 /* Legacy IRQ descriptors are already allocated by the arch. */
425 if (gsi < NR_IRQS_LEGACY)
426 return gsi;
427
428 irq = irq_alloc_desc_at(gsi, -1);
429 if (irq < 0)
430 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
431
432 return irq;
433}
434
435static void xen_free_irq(unsigned irq)
436{
72146104
IC
437 /* Legacy IRQ descriptors are managed by the arch. */
438 if (irq < NR_IRQS_LEGACY)
439 return;
440
c9df1ce5
IC
441 irq_free_desc(irq);
442}
443
d46a78b0
JF
444static void pirq_unmask_notify(int irq)
445{
7a043f11 446 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
447
448 if (unlikely(pirq_needs_eoi(irq))) {
449 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
450 WARN_ON(rc);
451 }
452}
453
454static void pirq_query_unmask(int irq)
455{
456 struct physdev_irq_status_query irq_status;
457 struct irq_info *info = info_for_irq(irq);
458
459 BUG_ON(info->type != IRQT_PIRQ);
460
7a043f11 461 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
462 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
463 irq_status.flags = 0;
464
465 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
466 if (irq_status.flags & XENIRQSTAT_needs_eoi)
467 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
468}
469
470static bool probing_irq(int irq)
471{
472 struct irq_desc *desc = irq_to_desc(irq);
473
474 return desc && desc->action == NULL;
475}
476
c9e265e0 477static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
478{
479 struct evtchn_bind_pirq bind_pirq;
480 struct irq_info *info = info_for_irq(irq);
481 int evtchn = evtchn_from_irq(irq);
15ebbb82 482 int rc;
d46a78b0
JF
483
484 BUG_ON(info->type != IRQT_PIRQ);
485
486 if (VALID_EVTCHN(evtchn))
487 goto out;
488
7a043f11 489 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 490 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
491 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
492 BIND_PIRQ__WILL_SHARE : 0;
493 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
494 if (rc != 0) {
d46a78b0
JF
495 if (!probing_irq(irq))
496 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
497 irq);
498 return 0;
499 }
500 evtchn = bind_pirq.port;
501
502 pirq_query_unmask(irq);
503
504 evtchn_to_irq[evtchn] = irq;
505 bind_evtchn_to_cpu(evtchn, 0);
506 info->evtchn = evtchn;
507
508out:
509 unmask_evtchn(evtchn);
510 pirq_unmask_notify(irq);
511
512 return 0;
513}
514
c9e265e0
TG
515static unsigned int startup_pirq(struct irq_data *data)
516{
517 return __startup_pirq(data->irq);
518}
519
520static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
521{
522 struct evtchn_close close;
c9e265e0 523 unsigned int irq = data->irq;
d46a78b0
JF
524 struct irq_info *info = info_for_irq(irq);
525 int evtchn = evtchn_from_irq(irq);
526
527 BUG_ON(info->type != IRQT_PIRQ);
528
529 if (!VALID_EVTCHN(evtchn))
530 return;
531
532 mask_evtchn(evtchn);
533
534 close.port = evtchn;
535 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
536 BUG();
537
538 bind_evtchn_to_cpu(evtchn, 0);
539 evtchn_to_irq[evtchn] = -1;
540 info->evtchn = 0;
541}
542
c9e265e0 543static void enable_pirq(struct irq_data *data)
d46a78b0 544{
c9e265e0 545 startup_pirq(data);
d46a78b0
JF
546}
547
c9e265e0 548static void disable_pirq(struct irq_data *data)
d46a78b0
JF
549{
550}
551
c9e265e0 552static void ack_pirq(struct irq_data *data)
d46a78b0 553{
c9e265e0 554 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 555
c9e265e0 556 irq_move_irq(data);
d46a78b0
JF
557
558 if (VALID_EVTCHN(evtchn)) {
559 mask_evtchn(evtchn);
560 clear_evtchn(evtchn);
561 }
562}
563
d46a78b0
JF
564static int find_irq_by_gsi(unsigned gsi)
565{
566 int irq;
567
b21ddbf5 568 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
569 struct irq_info *info = info_for_irq(irq);
570
571 if (info == NULL || info->type != IRQT_PIRQ)
572 continue;
573
574 if (gsi_from_irq(irq) == gsi)
575 return irq;
576 }
577
578 return -1;
579}
580
7a043f11
SS
581int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
582{
583 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
584}
585
586/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
587 * consequence don't assume that the irq number returned has a low value
588 * or can be used as a pirq number unless you know otherwise.
589 *
7a043f11 590 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 591 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
592 * matches the gsi number passed as second argument.
593 *
594 * Note: We don't assign an event channel until the irq actually started
595 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 596 */
7a043f11 597int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 598{
7a043f11 599 int irq = 0;
d46a78b0
JF
600 struct physdev_irq irq_op;
601
602 spin_lock(&irq_mapping_update_lock);
603
e5fc7345 604 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 605 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
606 pirq > nr_irqs ? "pirq" :"",
607 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
608 goto out;
609 }
610
d46a78b0
JF
611 irq = find_irq_by_gsi(gsi);
612 if (irq != -1) {
7a043f11 613 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
614 irq, gsi);
615 goto out; /* XXX need refcount? */
616 }
617
c9df1ce5 618 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
619
620 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 621 handle_level_irq, name);
d46a78b0
JF
622
623 irq_op.irq = irq;
b5401a96
AN
624 irq_op.vector = 0;
625
626 /* Only the privileged domain can do this. For non-priv, the pcifront
627 * driver provides a PCI bus that does the call to do exactly
628 * this in the priv domain. */
629 if (xen_initial_domain() &&
630 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 631 xen_free_irq(irq);
d46a78b0
JF
632 irq = -ENOSPC;
633 goto out;
634 }
635
7a043f11 636 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 637 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 638 pirq_to_irq[pirq] = irq;
d46a78b0
JF
639
640out:
641 spin_unlock(&irq_mapping_update_lock);
642
643 return irq;
644}
645
f731e3ef
QH
646#ifdef CONFIG_PCI_MSI
647#include <linux/msi.h>
648#include "../pci/msi.h"
649
cbf6aa89
IC
650static int find_unbound_pirq(int type)
651{
652 int rc, i;
653 struct physdev_get_free_pirq op_get_free_pirq;
654 op_get_free_pirq.type = type;
655
656 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
657 if (!rc)
658 return op_get_free_pirq.pirq;
659
660 for (i = 0; i < nr_irqs; i++) {
661 if (pirq_to_irq[i] < 0)
662 return i;
663 }
664 return -1;
665}
666
af42b8d1 667void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc)
809f9267
SS
668{
669 spin_lock(&irq_mapping_update_lock);
670
af42b8d1 671 if (alloc & XEN_ALLOC_IRQ) {
c9df1ce5 672 *irq = xen_allocate_irq_dynamic();
af42b8d1
SS
673 if (*irq == -1)
674 goto out;
675 }
809f9267 676
af42b8d1
SS
677 if (alloc & XEN_ALLOC_PIRQ) {
678 *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
679 if (*pirq == -1)
680 goto out;
681 }
809f9267
SS
682
683 set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
684 handle_level_irq, name);
685
686 irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
687 pirq_to_irq[*pirq] = *irq;
688
689out:
690 spin_unlock(&irq_mapping_update_lock);
691}
692
f731e3ef
QH
693int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
694{
695 int irq = -1;
696 struct physdev_map_pirq map_irq;
697 int rc;
698 int pos;
699 u32 table_offset, bir;
700
701 memset(&map_irq, 0, sizeof(map_irq));
702 map_irq.domid = DOMID_SELF;
703 map_irq.type = MAP_PIRQ_TYPE_MSI;
704 map_irq.index = -1;
705 map_irq.pirq = -1;
706 map_irq.bus = dev->bus->number;
707 map_irq.devfn = dev->devfn;
708
709 if (type == PCI_CAP_ID_MSIX) {
710 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
711
712 pci_read_config_dword(dev, msix_table_offset_reg(pos),
713 &table_offset);
714 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
715
716 map_irq.table_base = pci_resource_start(dev, bir);
717 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
718 }
719
720 spin_lock(&irq_mapping_update_lock);
721
c9df1ce5 722 irq = xen_allocate_irq_dynamic();
f731e3ef
QH
723
724 if (irq == -1)
725 goto out;
726
727 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
728 if (rc) {
729 printk(KERN_WARNING "xen map irq failed %d\n", rc);
730
c9df1ce5 731 xen_free_irq(irq);
f731e3ef
QH
732
733 irq = -1;
734 goto out;
735 }
736 irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
737
738 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
739 handle_level_irq,
740 (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
741
742out:
743 spin_unlock(&irq_mapping_update_lock);
744 return irq;
745}
746#endif
747
b5401a96
AN
748int xen_destroy_irq(int irq)
749{
750 struct irq_desc *desc;
38aa66fc
JF
751 struct physdev_unmap_pirq unmap_irq;
752 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
753 int rc = -ENOENT;
754
755 spin_lock(&irq_mapping_update_lock);
756
757 desc = irq_to_desc(irq);
758 if (!desc)
759 goto out;
760
38aa66fc 761 if (xen_initial_domain()) {
12334715 762 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
763 unmap_irq.domid = DOMID_SELF;
764 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
765 if (rc) {
766 printk(KERN_WARNING "unmap irq failed %d\n", rc);
767 goto out;
768 }
af42b8d1 769 pirq_to_irq[info->u.pirq.pirq] = -1;
38aa66fc 770 }
b5401a96
AN
771 irq_info[irq] = mk_unbound_info();
772
c9df1ce5 773 xen_free_irq(irq);
b5401a96
AN
774
775out:
776 spin_unlock(&irq_mapping_update_lock);
777 return rc;
778}
779
d46a78b0
JF
780int xen_vector_from_irq(unsigned irq)
781{
782 return vector_from_irq(irq);
783}
784
785int xen_gsi_from_irq(unsigned irq)
786{
787 return gsi_from_irq(irq);
e46cdb66
JF
788}
789
af42b8d1
SS
790int xen_irq_from_pirq(unsigned pirq)
791{
792 return pirq_to_irq[pirq];
793}
794
b536b4b9 795int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
796{
797 int irq;
798
799 spin_lock(&irq_mapping_update_lock);
800
801 irq = evtchn_to_irq[evtchn];
802
803 if (irq == -1) {
c9df1ce5 804 irq = xen_allocate_irq_dynamic();
e46cdb66 805
e46cdb66 806 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 807 handle_fasteoi_irq, "event");
e46cdb66
JF
808
809 evtchn_to_irq[evtchn] = irq;
ced40d0f 810 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
811 }
812
e46cdb66
JF
813 spin_unlock(&irq_mapping_update_lock);
814
815 return irq;
816}
b536b4b9 817EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 818
f87e4cac
JF
819static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
820{
821 struct evtchn_bind_ipi bind_ipi;
822 int evtchn, irq;
823
824 spin_lock(&irq_mapping_update_lock);
825
826 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 827
f87e4cac 828 if (irq == -1) {
c9df1ce5 829 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
830 if (irq < 0)
831 goto out;
832
aaca4964
JF
833 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
834 handle_percpu_irq, "ipi");
f87e4cac
JF
835
836 bind_ipi.vcpu = cpu;
837 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
838 &bind_ipi) != 0)
839 BUG();
840 evtchn = bind_ipi.port;
841
842 evtchn_to_irq[evtchn] = irq;
ced40d0f 843 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
844 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
845
846 bind_evtchn_to_cpu(evtchn, cpu);
847 }
848
f87e4cac
JF
849 out:
850 spin_unlock(&irq_mapping_update_lock);
851 return irq;
852}
853
854
4fe7d5a7 855int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
856{
857 struct evtchn_bind_virq bind_virq;
858 int evtchn, irq;
859
860 spin_lock(&irq_mapping_update_lock);
861
862 irq = per_cpu(virq_to_irq, cpu)[virq];
863
864 if (irq == -1) {
c9df1ce5 865 irq = xen_allocate_irq_dynamic();
a52521f1
JF
866
867 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
868 handle_percpu_irq, "virq");
869
e46cdb66
JF
870 bind_virq.virq = virq;
871 bind_virq.vcpu = cpu;
872 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
873 &bind_virq) != 0)
874 BUG();
875 evtchn = bind_virq.port;
876
e46cdb66 877 evtchn_to_irq[evtchn] = irq;
ced40d0f 878 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
879
880 per_cpu(virq_to_irq, cpu)[virq] = irq;
881
882 bind_evtchn_to_cpu(evtchn, cpu);
883 }
884
e46cdb66
JF
885 spin_unlock(&irq_mapping_update_lock);
886
887 return irq;
888}
889
890static void unbind_from_irq(unsigned int irq)
891{
892 struct evtchn_close close;
893 int evtchn = evtchn_from_irq(irq);
894
895 spin_lock(&irq_mapping_update_lock);
896
d77bbd4d 897 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
898 close.port = evtchn;
899 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
900 BUG();
901
902 switch (type_from_irq(irq)) {
903 case IRQT_VIRQ:
904 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 905 [virq_from_irq(irq)] = -1;
e46cdb66 906 break;
d68d82af
AN
907 case IRQT_IPI:
908 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 909 [ipi_from_irq(irq)] = -1;
d68d82af 910 break;
e46cdb66
JF
911 default:
912 break;
913 }
914
915 /* Closed ports are implicitly re-bound to VCPU0. */
916 bind_evtchn_to_cpu(evtchn, 0);
917
918 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
919 }
920
921 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 922 irq_info[irq] = mk_unbound_info();
e46cdb66 923
c9df1ce5 924 xen_free_irq(irq);
e46cdb66
JF
925 }
926
927 spin_unlock(&irq_mapping_update_lock);
928}
929
930int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 931 irq_handler_t handler,
e46cdb66
JF
932 unsigned long irqflags,
933 const char *devname, void *dev_id)
934{
935 unsigned int irq;
936 int retval;
937
938 irq = bind_evtchn_to_irq(evtchn);
939 retval = request_irq(irq, handler, irqflags, devname, dev_id);
940 if (retval != 0) {
941 unbind_from_irq(irq);
942 return retval;
943 }
944
945 return irq;
946}
947EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
948
949int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 950 irq_handler_t handler,
e46cdb66
JF
951 unsigned long irqflags, const char *devname, void *dev_id)
952{
953 unsigned int irq;
954 int retval;
955
956 irq = bind_virq_to_irq(virq, cpu);
957 retval = request_irq(irq, handler, irqflags, devname, dev_id);
958 if (retval != 0) {
959 unbind_from_irq(irq);
960 return retval;
961 }
962
963 return irq;
964}
965EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
966
f87e4cac
JF
967int bind_ipi_to_irqhandler(enum ipi_vector ipi,
968 unsigned int cpu,
969 irq_handler_t handler,
970 unsigned long irqflags,
971 const char *devname,
972 void *dev_id)
973{
974 int irq, retval;
975
976 irq = bind_ipi_to_irq(ipi, cpu);
977 if (irq < 0)
978 return irq;
979
4877c737 980 irqflags |= IRQF_NO_SUSPEND;
f87e4cac
JF
981 retval = request_irq(irq, handler, irqflags, devname, dev_id);
982 if (retval != 0) {
983 unbind_from_irq(irq);
984 return retval;
985 }
986
987 return irq;
988}
989
e46cdb66
JF
990void unbind_from_irqhandler(unsigned int irq, void *dev_id)
991{
992 free_irq(irq, dev_id);
993 unbind_from_irq(irq);
994}
995EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
996
f87e4cac
JF
997void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
998{
999 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1000 BUG_ON(irq < 0);
1001 notify_remote_via_irq(irq);
1002}
1003
ee523ca1
JF
1004irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1005{
1006 struct shared_info *sh = HYPERVISOR_shared_info;
1007 int cpu = smp_processor_id();
cb52e6d9 1008 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
1009 int i;
1010 unsigned long flags;
1011 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1012 struct vcpu_info *v;
ee523ca1
JF
1013
1014 spin_lock_irqsave(&debug_lock, flags);
1015
cb52e6d9 1016 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1017
1018 for_each_online_cpu(i) {
cb52e6d9
IC
1019 int pending;
1020 v = per_cpu(xen_vcpu, i);
1021 pending = (get_irq_regs() && i == cpu)
1022 ? xen_irqs_disabled(get_irq_regs())
1023 : v->evtchn_upcall_mask;
1024 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1025 pending, v->evtchn_upcall_pending,
1026 (int)(sizeof(v->evtchn_pending_sel)*2),
1027 v->evtchn_pending_sel);
1028 }
1029 v = per_cpu(xen_vcpu, cpu);
1030
1031 printk("\npending:\n ");
1032 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1033 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1034 sh->evtchn_pending[i],
1035 i % 8 == 0 ? "\n " : " ");
1036 printk("\nglobal mask:\n ");
1037 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1038 printk("%0*lx%s",
1039 (int)(sizeof(sh->evtchn_mask[0])*2),
1040 sh->evtchn_mask[i],
1041 i % 8 == 0 ? "\n " : " ");
1042
1043 printk("\nglobally unmasked:\n ");
1044 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1045 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1046 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1047 i % 8 == 0 ? "\n " : " ");
1048
1049 printk("\nlocal cpu%d mask:\n ", cpu);
1050 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1051 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1052 cpu_evtchn[i],
1053 i % 8 == 0 ? "\n " : " ");
1054
1055 printk("\nlocally unmasked:\n ");
1056 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1057 unsigned long pending = sh->evtchn_pending[i]
1058 & ~sh->evtchn_mask[i]
1059 & cpu_evtchn[i];
1060 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1061 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1062 }
ee523ca1
JF
1063
1064 printk("\npending list:\n");
cb52e6d9 1065 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1066 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1067 int word_idx = i / BITS_PER_LONG;
1068 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1069 cpu_from_evtchn(i), i,
cb52e6d9
IC
1070 evtchn_to_irq[i],
1071 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1072 ? "" : " l2-clear",
1073 !sync_test_bit(i, sh->evtchn_mask)
1074 ? "" : " globally-masked",
1075 sync_test_bit(i, cpu_evtchn)
1076 ? "" : " locally-masked");
ee523ca1
JF
1077 }
1078 }
1079
1080 spin_unlock_irqrestore(&debug_lock, flags);
1081
1082 return IRQ_HANDLED;
1083}
1084
245b2e70
TH
1085static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1086
e46cdb66
JF
1087/*
1088 * Search the CPUs pending events bitmasks. For each one found, map
1089 * the event number to an irq, and feed it into do_IRQ() for
1090 * handling.
1091 *
1092 * Xen uses a two-level bitmap to speed searching. The first level is
1093 * a bitset of words which contain pending event bits. The second
1094 * level is a bitset of pending events themselves.
1095 */
38e20b07 1096static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1097{
1098 int cpu = get_cpu();
1099 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1100 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1101 unsigned count;
e46cdb66 1102
229664be
JF
1103 do {
1104 unsigned long pending_words;
e46cdb66 1105
229664be 1106 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1107
b2e4ae69 1108 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1109 goto out;
e46cdb66 1110
e849c3e9
IY
1111#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1112 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1113 wmb();
e849c3e9 1114#endif
229664be
JF
1115 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1116 while (pending_words != 0) {
1117 unsigned long pending_bits;
1118 int word_idx = __ffs(pending_words);
1119 pending_words &= ~(1UL << word_idx);
1120
1121 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1122 int bit_idx = __ffs(pending_bits);
1123 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1124 int irq = evtchn_to_irq[port];
ca4dbc66 1125 struct irq_desc *desc;
229664be 1126
3588fe2e
JF
1127 mask_evtchn(port);
1128 clear_evtchn(port);
1129
ca4dbc66
EB
1130 if (irq != -1) {
1131 desc = irq_to_desc(irq);
1132 if (desc)
1133 generic_handle_irq_desc(irq, desc);
1134 }
e46cdb66
JF
1135 }
1136 }
e46cdb66 1137
229664be
JF
1138 BUG_ON(!irqs_disabled());
1139
780f36d8
CL
1140 count = __this_cpu_read(xed_nesting_count);
1141 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1142 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1143
1144out:
38e20b07
SY
1145
1146 put_cpu();
1147}
1148
1149void xen_evtchn_do_upcall(struct pt_regs *regs)
1150{
1151 struct pt_regs *old_regs = set_irq_regs(regs);
1152
1153 exit_idle();
1154 irq_enter();
1155
1156 __xen_evtchn_do_upcall();
1157
3445a8fd
JF
1158 irq_exit();
1159 set_irq_regs(old_regs);
38e20b07 1160}
3445a8fd 1161
38e20b07
SY
1162void xen_hvm_evtchn_do_upcall(void)
1163{
1164 __xen_evtchn_do_upcall();
e46cdb66 1165}
183d03cc 1166EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1167
eb1e305f
JF
1168/* Rebind a new event channel to an existing irq. */
1169void rebind_evtchn_irq(int evtchn, int irq)
1170{
d77bbd4d
JF
1171 struct irq_info *info = info_for_irq(irq);
1172
eb1e305f
JF
1173 /* Make sure the irq is masked, since the new event channel
1174 will also be masked. */
1175 disable_irq(irq);
1176
1177 spin_lock(&irq_mapping_update_lock);
1178
1179 /* After resume the irq<->evtchn mappings are all cleared out */
1180 BUG_ON(evtchn_to_irq[evtchn] != -1);
1181 /* Expect irq to have been bound before,
d77bbd4d
JF
1182 so there should be a proper type */
1183 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1184
1185 evtchn_to_irq[evtchn] = irq;
ced40d0f 1186 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1187
1188 spin_unlock(&irq_mapping_update_lock);
1189
1190 /* new event channels are always bound to cpu 0 */
0de26520 1191 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1192
1193 /* Unmask the event channel. */
1194 enable_irq(irq);
1195}
1196
e46cdb66 1197/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1198static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1199{
1200 struct evtchn_bind_vcpu bind_vcpu;
1201 int evtchn = evtchn_from_irq(irq);
1202
183d03cc
SS
1203 /* events delivered via platform PCI interrupts are always
1204 * routed to vcpu 0 */
1205 if (!VALID_EVTCHN(evtchn) ||
1206 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1207 return -1;
e46cdb66
JF
1208
1209 /* Send future instances of this interrupt to other vcpu. */
1210 bind_vcpu.port = evtchn;
1211 bind_vcpu.vcpu = tcpu;
1212
1213 /*
1214 * If this fails, it usually just indicates that we're dealing with a
1215 * virq or IPI channel, which don't actually need to be rebound. Ignore
1216 * it, but don't do the xenlinux-level rebind in that case.
1217 */
1218 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1219 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1220
d5dedd45
YL
1221 return 0;
1222}
e46cdb66 1223
c9e265e0
TG
1224static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1225 bool force)
e46cdb66 1226{
0de26520 1227 unsigned tcpu = cpumask_first(dest);
d5dedd45 1228
c9e265e0 1229 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1230}
1231
642e0c88
IY
1232int resend_irq_on_evtchn(unsigned int irq)
1233{
1234 int masked, evtchn = evtchn_from_irq(irq);
1235 struct shared_info *s = HYPERVISOR_shared_info;
1236
1237 if (!VALID_EVTCHN(evtchn))
1238 return 1;
1239
1240 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1241 sync_set_bit(evtchn, s->evtchn_pending);
1242 if (!masked)
1243 unmask_evtchn(evtchn);
1244
1245 return 1;
1246}
1247
c9e265e0 1248static void enable_dynirq(struct irq_data *data)
e46cdb66 1249{
c9e265e0 1250 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1251
1252 if (VALID_EVTCHN(evtchn))
1253 unmask_evtchn(evtchn);
1254}
1255
c9e265e0 1256static void disable_dynirq(struct irq_data *data)
e46cdb66 1257{
c9e265e0 1258 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1259
1260 if (VALID_EVTCHN(evtchn))
1261 mask_evtchn(evtchn);
1262}
1263
c9e265e0 1264static void ack_dynirq(struct irq_data *data)
e46cdb66 1265{
c9e265e0 1266 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1267
c9e265e0 1268 move_masked_irq(data->irq);
e46cdb66
JF
1269
1270 if (VALID_EVTCHN(evtchn))
3588fe2e 1271 unmask_evtchn(evtchn);
e46cdb66
JF
1272}
1273
c9e265e0 1274static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1275{
c9e265e0 1276 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1277 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1278 int ret = 0;
1279
1280 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1281 int masked;
1282
1283 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1284 sync_set_bit(evtchn, sh->evtchn_pending);
1285 if (!masked)
1286 unmask_evtchn(evtchn);
e46cdb66
JF
1287 ret = 1;
1288 }
1289
1290 return ret;
1291}
1292
9a069c33
SS
1293static void restore_cpu_pirqs(void)
1294{
1295 int pirq, rc, irq, gsi;
1296 struct physdev_map_pirq map_irq;
1297
1298 for (pirq = 0; pirq < nr_irqs; pirq++) {
1299 irq = pirq_to_irq[pirq];
1300 if (irq == -1)
1301 continue;
1302
1303 /* save/restore of PT devices doesn't work, so at this point the
1304 * only devices present are GSI based emulated devices */
1305 gsi = gsi_from_irq(irq);
1306 if (!gsi)
1307 continue;
1308
1309 map_irq.domid = DOMID_SELF;
1310 map_irq.type = MAP_PIRQ_TYPE_GSI;
1311 map_irq.index = gsi;
1312 map_irq.pirq = pirq;
1313
1314 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1315 if (rc) {
1316 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1317 gsi, irq, pirq, rc);
1318 irq_info[irq] = mk_unbound_info();
1319 pirq_to_irq[pirq] = -1;
1320 continue;
1321 }
1322
1323 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1324
c9e265e0 1325 __startup_pirq(irq);
9a069c33
SS
1326 }
1327}
1328
0e91398f
JF
1329static void restore_cpu_virqs(unsigned int cpu)
1330{
1331 struct evtchn_bind_virq bind_virq;
1332 int virq, irq, evtchn;
1333
1334 for (virq = 0; virq < NR_VIRQS; virq++) {
1335 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1336 continue;
1337
ced40d0f 1338 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1339
1340 /* Get a new binding from Xen. */
1341 bind_virq.virq = virq;
1342 bind_virq.vcpu = cpu;
1343 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1344 &bind_virq) != 0)
1345 BUG();
1346 evtchn = bind_virq.port;
1347
1348 /* Record the new mapping. */
1349 evtchn_to_irq[evtchn] = irq;
ced40d0f 1350 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1351 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1352 }
1353}
1354
1355static void restore_cpu_ipis(unsigned int cpu)
1356{
1357 struct evtchn_bind_ipi bind_ipi;
1358 int ipi, irq, evtchn;
1359
1360 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1361 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1362 continue;
1363
ced40d0f 1364 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1365
1366 /* Get a new binding from Xen. */
1367 bind_ipi.vcpu = cpu;
1368 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1369 &bind_ipi) != 0)
1370 BUG();
1371 evtchn = bind_ipi.port;
1372
1373 /* Record the new mapping. */
1374 evtchn_to_irq[evtchn] = irq;
ced40d0f 1375 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1376 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1377 }
1378}
1379
2d9e1e2f
JF
1380/* Clear an irq's pending state, in preparation for polling on it */
1381void xen_clear_irq_pending(int irq)
1382{
1383 int evtchn = evtchn_from_irq(irq);
1384
1385 if (VALID_EVTCHN(evtchn))
1386 clear_evtchn(evtchn);
1387}
d9a8814f 1388EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1389void xen_set_irq_pending(int irq)
1390{
1391 int evtchn = evtchn_from_irq(irq);
1392
1393 if (VALID_EVTCHN(evtchn))
1394 set_evtchn(evtchn);
1395}
1396
1397bool xen_test_irq_pending(int irq)
1398{
1399 int evtchn = evtchn_from_irq(irq);
1400 bool ret = false;
1401
1402 if (VALID_EVTCHN(evtchn))
1403 ret = test_evtchn(evtchn);
1404
1405 return ret;
1406}
1407
d9a8814f
KRW
1408/* Poll waiting for an irq to become pending with timeout. In the usual case,
1409 * the irq will be disabled so it won't deliver an interrupt. */
1410void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1411{
1412 evtchn_port_t evtchn = evtchn_from_irq(irq);
1413
1414 if (VALID_EVTCHN(evtchn)) {
1415 struct sched_poll poll;
1416
1417 poll.nr_ports = 1;
d9a8814f 1418 poll.timeout = timeout;
ff3c5362 1419 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1420
1421 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1422 BUG();
1423 }
1424}
d9a8814f
KRW
1425EXPORT_SYMBOL(xen_poll_irq_timeout);
1426/* Poll waiting for an irq to become pending. In the usual case, the
1427 * irq will be disabled so it won't deliver an interrupt. */
1428void xen_poll_irq(int irq)
1429{
1430 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1431}
2d9e1e2f 1432
0e91398f
JF
1433void xen_irq_resume(void)
1434{
1435 unsigned int cpu, irq, evtchn;
6903591f 1436 struct irq_desc *desc;
0e91398f
JF
1437
1438 init_evtchn_cpu_bindings();
1439
1440 /* New event-channel space is not 'live' yet. */
1441 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1442 mask_evtchn(evtchn);
1443
1444 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1445 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1446 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1447
1448 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1449 evtchn_to_irq[evtchn] = -1;
1450
1451 for_each_possible_cpu(cpu) {
1452 restore_cpu_virqs(cpu);
1453 restore_cpu_ipis(cpu);
1454 }
6903591f
IC
1455
1456 /*
1457 * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
1458 * are not handled by the IRQ core.
1459 */
1460 for_each_irq_desc(irq, desc) {
1461 if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
1462 continue;
1463 if (desc->status & IRQ_DISABLED)
1464 continue;
1465
1466 evtchn = evtchn_from_irq(irq);
1467 if (evtchn == -1)
1468 continue;
1469
1470 unmask_evtchn(evtchn);
1471 }
9a069c33
SS
1472
1473 restore_cpu_pirqs();
0e91398f
JF
1474}
1475
e46cdb66 1476static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1477 .name = "xen-dyn",
54a353a0 1478
c9e265e0
TG
1479 .irq_disable = disable_dynirq,
1480 .irq_mask = disable_dynirq,
1481 .irq_unmask = enable_dynirq,
54a353a0 1482
c9e265e0
TG
1483 .irq_eoi = ack_dynirq,
1484 .irq_set_affinity = set_affinity_irq,
1485 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1486};
1487
d46a78b0 1488static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1489 .name = "xen-pirq",
d46a78b0 1490
c9e265e0
TG
1491 .irq_startup = startup_pirq,
1492 .irq_shutdown = shutdown_pirq,
d46a78b0 1493
c9e265e0
TG
1494 .irq_enable = enable_pirq,
1495 .irq_unmask = enable_pirq,
d46a78b0 1496
c9e265e0
TG
1497 .irq_disable = disable_pirq,
1498 .irq_mask = disable_pirq,
d46a78b0 1499
c9e265e0 1500 .irq_ack = ack_pirq,
d46a78b0 1501
c9e265e0 1502 .irq_set_affinity = set_affinity_irq,
d46a78b0 1503
c9e265e0 1504 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1505};
1506
aaca4964 1507static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1508 .name = "xen-percpu",
aaca4964 1509
c9e265e0
TG
1510 .irq_disable = disable_dynirq,
1511 .irq_mask = disable_dynirq,
1512 .irq_unmask = enable_dynirq,
aaca4964 1513
c9e265e0 1514 .irq_ack = ack_dynirq,
aaca4964
JF
1515};
1516
38e20b07
SY
1517int xen_set_callback_via(uint64_t via)
1518{
1519 struct xen_hvm_param a;
1520 a.domid = DOMID_SELF;
1521 a.index = HVM_PARAM_CALLBACK_IRQ;
1522 a.value = via;
1523 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1524}
1525EXPORT_SYMBOL_GPL(xen_set_callback_via);
1526
ca65f9fc 1527#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1528/* Vector callbacks are better than PCI interrupts to receive event
1529 * channel notifications because we can receive vector callbacks on any
1530 * vcpu and we don't need PCI support or APIC interactions. */
1531void xen_callback_vector(void)
1532{
1533 int rc;
1534 uint64_t callback_via;
1535 if (xen_have_vector_callback) {
1536 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1537 rc = xen_set_callback_via(callback_via);
1538 if (rc) {
1539 printk(KERN_ERR "Request for Xen HVM callback vector"
1540 " failed.\n");
1541 xen_have_vector_callback = 0;
1542 return;
1543 }
1544 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1545 "enabled\n");
1546 /* in the restore case the vector has already been allocated */
1547 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1548 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1549 }
1550}
ca65f9fc
SS
1551#else
1552void xen_callback_vector(void) {}
1553#endif
38e20b07 1554
e46cdb66
JF
1555void __init xen_init_IRQ(void)
1556{
e5fc7345 1557 int i;
c7a3589e 1558
a70c352a
PE
1559 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1560 GFP_KERNEL);
b21ddbf5
JF
1561 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1562
e5fc7345
SS
1563 /* We are using nr_irqs as the maximum number of pirq available but
1564 * that number is actually chosen by Xen and we don't know exactly
1565 * what it is. Be careful choosing high pirq numbers. */
1566 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1567 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1568 pirq_to_irq[i] = -1;
1569
b21ddbf5
JF
1570 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1571 GFP_KERNEL);
1572 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1573 evtchn_to_irq[i] = -1;
e46cdb66
JF
1574
1575 init_evtchn_cpu_bindings();
1576
1577 /* No event channels are 'live' right now. */
1578 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1579 mask_evtchn(i);
1580
38e20b07
SY
1581 if (xen_hvm_domain()) {
1582 xen_callback_vector();
1583 native_init_IRQ();
3942b740
SS
1584 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1585 * __acpi_register_gsi can point at the right function */
1586 pci_xen_hvm_init();
38e20b07
SY
1587 } else {
1588 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1589 if (xen_initial_domain())
1590 xen_setup_pirqs();
38e20b07 1591 }
e46cdb66 1592}