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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
19 | * 4. Hardware interrupts. Not supported at present. | |
20 | * | |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
e46cdb66 JF |
30 | |
31 | #include <asm/ptrace.h> | |
32 | #include <asm/irq.h> | |
792dc4f6 | 33 | #include <asm/idle.h> |
e46cdb66 JF |
34 | #include <asm/sync_bitops.h> |
35 | #include <asm/xen/hypercall.h> | |
8d1b8753 | 36 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 37 | |
e04d0d07 | 38 | #include <xen/xen-ops.h> |
e46cdb66 JF |
39 | #include <xen/events.h> |
40 | #include <xen/interface/xen.h> | |
41 | #include <xen/interface/event_channel.h> | |
42 | ||
e46cdb66 JF |
43 | /* |
44 | * This lock protects updates to the following mapping and reference-count | |
45 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
46 | */ | |
47 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
48 | ||
49 | /* IRQ <-> VIRQ mapping. */ | |
50 | static DEFINE_PER_CPU(int, virq_to_irq[NR_VIRQS]) = {[0 ... NR_VIRQS-1] = -1}; | |
51 | ||
f87e4cac JF |
52 | /* IRQ <-> IPI mapping */ |
53 | static DEFINE_PER_CPU(int, ipi_to_irq[XEN_NR_IPIS]) = {[0 ... XEN_NR_IPIS-1] = -1}; | |
54 | ||
ced40d0f JF |
55 | /* Interrupt types. */ |
56 | enum xen_irq_type { | |
d77bbd4d | 57 | IRQT_UNBOUND = 0, |
f87e4cac JF |
58 | IRQT_PIRQ, |
59 | IRQT_VIRQ, | |
60 | IRQT_IPI, | |
61 | IRQT_EVTCHN | |
62 | }; | |
e46cdb66 | 63 | |
ced40d0f JF |
64 | /* |
65 | * Packed IRQ information: | |
66 | * type - enum xen_irq_type | |
67 | * event channel - irq->event channel mapping | |
68 | * cpu - cpu this event channel is bound to | |
69 | * index - type-specific information: | |
70 | * PIRQ - vector, with MSB being "needs EIO" | |
71 | * VIRQ - virq number | |
72 | * IPI - IPI vector | |
73 | * EVTCHN - | |
74 | */ | |
75 | struct irq_info | |
76 | { | |
77 | enum xen_irq_type type; /* type */ | |
78 | unsigned short evtchn; /* event channel */ | |
79 | unsigned short cpu; /* cpu bound */ | |
80 | ||
81 | union { | |
82 | unsigned short virq; | |
83 | enum ipi_vector ipi; | |
84 | struct { | |
85 | unsigned short gsi; | |
86 | unsigned short vector; | |
87 | } pirq; | |
88 | } u; | |
89 | }; | |
90 | ||
91 | static struct irq_info irq_info[NR_IRQS]; | |
e46cdb66 JF |
92 | |
93 | static int evtchn_to_irq[NR_EVENT_CHANNELS] = { | |
94 | [0 ... NR_EVENT_CHANNELS-1] = -1 | |
95 | }; | |
c7a3589e MT |
96 | struct cpu_evtchn_s { |
97 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
98 | }; | |
99 | static struct cpu_evtchn_s *cpu_evtchn_mask_p; | |
100 | static inline unsigned long *cpu_evtchn_mask(int cpu) | |
101 | { | |
102 | return cpu_evtchn_mask_p[cpu].bits; | |
103 | } | |
e46cdb66 | 104 | |
e46cdb66 JF |
105 | /* Xen will never allocate port zero for any purpose. */ |
106 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
107 | ||
e46cdb66 JF |
108 | static struct irq_chip xen_dynamic_chip; |
109 | ||
110 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
111 | static struct irq_info mk_unbound_info(void) |
112 | { | |
113 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
114 | } | |
115 | ||
116 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
117 | { | |
118 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn }; | |
119 | } | |
120 | ||
121 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 122 | { |
ced40d0f JF |
123 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
124 | .u.ipi = ipi }; | |
125 | } | |
126 | ||
127 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
128 | { | |
129 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
130 | .u.virq = virq }; | |
131 | } | |
132 | ||
133 | static struct irq_info mk_pirq_info(unsigned short evtchn, | |
134 | unsigned short gsi, unsigned short vector) | |
135 | { | |
136 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
137 | .u.pirq = { .gsi = gsi, .vector = vector } }; | |
e46cdb66 JF |
138 | } |
139 | ||
140 | /* | |
141 | * Accessors for packed IRQ information. | |
142 | */ | |
ced40d0f | 143 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 144 | { |
ced40d0f | 145 | return &irq_info[irq]; |
e46cdb66 JF |
146 | } |
147 | ||
ced40d0f | 148 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 149 | { |
ced40d0f | 150 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
151 | } |
152 | ||
ced40d0f | 153 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 154 | { |
ced40d0f JF |
155 | struct irq_info *info = info_for_irq(irq); |
156 | ||
157 | BUG_ON(info == NULL); | |
158 | BUG_ON(info->type != IRQT_IPI); | |
159 | ||
160 | return info->u.ipi; | |
161 | } | |
162 | ||
163 | static unsigned virq_from_irq(unsigned irq) | |
164 | { | |
165 | struct irq_info *info = info_for_irq(irq); | |
166 | ||
167 | BUG_ON(info == NULL); | |
168 | BUG_ON(info->type != IRQT_VIRQ); | |
169 | ||
170 | return info->u.virq; | |
171 | } | |
172 | ||
173 | static unsigned gsi_from_irq(unsigned irq) | |
174 | { | |
175 | struct irq_info *info = info_for_irq(irq); | |
176 | ||
177 | BUG_ON(info == NULL); | |
178 | BUG_ON(info->type != IRQT_PIRQ); | |
179 | ||
180 | return info->u.pirq.gsi; | |
181 | } | |
182 | ||
183 | static unsigned vector_from_irq(unsigned irq) | |
184 | { | |
185 | struct irq_info *info = info_for_irq(irq); | |
186 | ||
187 | BUG_ON(info == NULL); | |
188 | BUG_ON(info->type != IRQT_PIRQ); | |
189 | ||
190 | return info->u.pirq.vector; | |
191 | } | |
192 | ||
193 | static enum xen_irq_type type_from_irq(unsigned irq) | |
194 | { | |
195 | return info_for_irq(irq)->type; | |
196 | } | |
197 | ||
198 | static unsigned cpu_from_irq(unsigned irq) | |
199 | { | |
200 | return info_for_irq(irq)->cpu; | |
201 | } | |
202 | ||
203 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
204 | { | |
205 | int irq = evtchn_to_irq[evtchn]; | |
206 | unsigned ret = 0; | |
207 | ||
208 | if (irq != -1) | |
209 | ret = cpu_from_irq(irq); | |
210 | ||
211 | return ret; | |
e46cdb66 JF |
212 | } |
213 | ||
214 | static inline unsigned long active_evtchns(unsigned int cpu, | |
215 | struct shared_info *sh, | |
216 | unsigned int idx) | |
217 | { | |
218 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 219 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
220 | ~sh->evtchn_mask[idx]); |
221 | } | |
222 | ||
223 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
224 | { | |
225 | int irq = evtchn_to_irq[chn]; | |
226 | ||
227 | BUG_ON(irq == -1); | |
228 | #ifdef CONFIG_SMP | |
7f7ace0c | 229 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
230 | #endif |
231 | ||
ced40d0f | 232 | __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
c7a3589e | 233 | __set_bit(chn, cpu_evtchn_mask(cpu)); |
e46cdb66 | 234 | |
ced40d0f | 235 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
236 | } |
237 | ||
238 | static void init_evtchn_cpu_bindings(void) | |
239 | { | |
240 | #ifdef CONFIG_SMP | |
10e58084 | 241 | struct irq_desc *desc; |
e46cdb66 | 242 | int i; |
10e58084 | 243 | |
e46cdb66 | 244 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 245 | for_each_irq_desc(i, desc) { |
7f7ace0c | 246 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 247 | } |
e46cdb66 JF |
248 | #endif |
249 | ||
c7a3589e | 250 | memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0))); |
e46cdb66 JF |
251 | } |
252 | ||
e46cdb66 JF |
253 | static inline void clear_evtchn(int port) |
254 | { | |
255 | struct shared_info *s = HYPERVISOR_shared_info; | |
256 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
257 | } | |
258 | ||
259 | static inline void set_evtchn(int port) | |
260 | { | |
261 | struct shared_info *s = HYPERVISOR_shared_info; | |
262 | sync_set_bit(port, &s->evtchn_pending[0]); | |
263 | } | |
264 | ||
168d2f46 JF |
265 | static inline int test_evtchn(int port) |
266 | { | |
267 | struct shared_info *s = HYPERVISOR_shared_info; | |
268 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
269 | } | |
270 | ||
e46cdb66 JF |
271 | |
272 | /** | |
273 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
274 | * @irq: irq of event channel to send event to | |
275 | * | |
276 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
277 | * save/restore. Notifications on a broken connection are silently | |
278 | * dropped. | |
279 | */ | |
280 | void notify_remote_via_irq(int irq) | |
281 | { | |
282 | int evtchn = evtchn_from_irq(irq); | |
283 | ||
284 | if (VALID_EVTCHN(evtchn)) | |
285 | notify_remote_via_evtchn(evtchn); | |
286 | } | |
287 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
288 | ||
289 | static void mask_evtchn(int port) | |
290 | { | |
291 | struct shared_info *s = HYPERVISOR_shared_info; | |
292 | sync_set_bit(port, &s->evtchn_mask[0]); | |
293 | } | |
294 | ||
295 | static void unmask_evtchn(int port) | |
296 | { | |
297 | struct shared_info *s = HYPERVISOR_shared_info; | |
298 | unsigned int cpu = get_cpu(); | |
299 | ||
300 | BUG_ON(!irqs_disabled()); | |
301 | ||
302 | /* Slow path (hypercall) if this is a non-local port. */ | |
303 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
304 | struct evtchn_unmask unmask = { .port = port }; | |
305 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
306 | } else { | |
307 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
308 | ||
309 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
310 | ||
311 | /* | |
312 | * The following is basically the equivalent of | |
313 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
314 | * the interrupt edge' if the channel is masked. | |
315 | */ | |
316 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
317 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
318 | &vcpu_info->evtchn_pending_sel)) | |
319 | vcpu_info->evtchn_upcall_pending = 1; | |
320 | } | |
321 | ||
322 | put_cpu(); | |
323 | } | |
324 | ||
325 | static int find_unbound_irq(void) | |
326 | { | |
327 | int irq; | |
6f8a0ed4 | 328 | struct irq_desc *desc; |
e46cdb66 | 329 | |
0b8f1efa | 330 | for (irq = 0; irq < nr_irqs; irq++) |
d77bbd4d | 331 | if (irq_info[irq].type == IRQT_UNBOUND) |
e46cdb66 JF |
332 | break; |
333 | ||
5a15d7e8 YL |
334 | if (irq == nr_irqs) |
335 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 | 336 | |
6f8a0ed4 JF |
337 | desc = irq_to_desc_alloc_cpu(irq, 0); |
338 | if (WARN_ON(desc == NULL)) | |
339 | return -1; | |
340 | ||
ced40d0f JF |
341 | dynamic_irq_init(irq); |
342 | ||
e46cdb66 JF |
343 | return irq; |
344 | } | |
345 | ||
b536b4b9 | 346 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
347 | { |
348 | int irq; | |
349 | ||
350 | spin_lock(&irq_mapping_update_lock); | |
351 | ||
352 | irq = evtchn_to_irq[evtchn]; | |
353 | ||
354 | if (irq == -1) { | |
355 | irq = find_unbound_irq(); | |
356 | ||
e46cdb66 JF |
357 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
358 | handle_level_irq, "event"); | |
359 | ||
360 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 361 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
362 | } |
363 | ||
e46cdb66 JF |
364 | spin_unlock(&irq_mapping_update_lock); |
365 | ||
366 | return irq; | |
367 | } | |
b536b4b9 | 368 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 369 | |
f87e4cac JF |
370 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
371 | { | |
372 | struct evtchn_bind_ipi bind_ipi; | |
373 | int evtchn, irq; | |
374 | ||
375 | spin_lock(&irq_mapping_update_lock); | |
376 | ||
377 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
378 | if (irq == -1) { | |
379 | irq = find_unbound_irq(); | |
380 | if (irq < 0) | |
381 | goto out; | |
382 | ||
f87e4cac JF |
383 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
384 | handle_level_irq, "ipi"); | |
385 | ||
386 | bind_ipi.vcpu = cpu; | |
387 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
388 | &bind_ipi) != 0) | |
389 | BUG(); | |
390 | evtchn = bind_ipi.port; | |
391 | ||
392 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 393 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
394 | |
395 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
396 | ||
397 | bind_evtchn_to_cpu(evtchn, cpu); | |
398 | } | |
399 | ||
f87e4cac JF |
400 | out: |
401 | spin_unlock(&irq_mapping_update_lock); | |
402 | return irq; | |
403 | } | |
404 | ||
405 | ||
e46cdb66 JF |
406 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
407 | { | |
408 | struct evtchn_bind_virq bind_virq; | |
409 | int evtchn, irq; | |
410 | ||
411 | spin_lock(&irq_mapping_update_lock); | |
412 | ||
413 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
414 | ||
415 | if (irq == -1) { | |
416 | bind_virq.virq = virq; | |
417 | bind_virq.vcpu = cpu; | |
418 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
419 | &bind_virq) != 0) | |
420 | BUG(); | |
421 | evtchn = bind_virq.port; | |
422 | ||
423 | irq = find_unbound_irq(); | |
424 | ||
e46cdb66 JF |
425 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
426 | handle_level_irq, "virq"); | |
427 | ||
428 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 429 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
430 | |
431 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
432 | ||
433 | bind_evtchn_to_cpu(evtchn, cpu); | |
434 | } | |
435 | ||
e46cdb66 JF |
436 | spin_unlock(&irq_mapping_update_lock); |
437 | ||
438 | return irq; | |
439 | } | |
440 | ||
441 | static void unbind_from_irq(unsigned int irq) | |
442 | { | |
443 | struct evtchn_close close; | |
444 | int evtchn = evtchn_from_irq(irq); | |
445 | ||
446 | spin_lock(&irq_mapping_update_lock); | |
447 | ||
d77bbd4d | 448 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
449 | close.port = evtchn; |
450 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
451 | BUG(); | |
452 | ||
453 | switch (type_from_irq(irq)) { | |
454 | case IRQT_VIRQ: | |
455 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 456 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 457 | break; |
d68d82af AN |
458 | case IRQT_IPI: |
459 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 460 | [ipi_from_irq(irq)] = -1; |
d68d82af | 461 | break; |
e46cdb66 JF |
462 | default: |
463 | break; | |
464 | } | |
465 | ||
466 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
467 | bind_evtchn_to_cpu(evtchn, 0); | |
468 | ||
469 | evtchn_to_irq[evtchn] = -1; | |
ced40d0f | 470 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 471 | |
0f2287ad | 472 | dynamic_irq_cleanup(irq); |
e46cdb66 JF |
473 | } |
474 | ||
475 | spin_unlock(&irq_mapping_update_lock); | |
476 | } | |
477 | ||
478 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 479 | irq_handler_t handler, |
e46cdb66 JF |
480 | unsigned long irqflags, |
481 | const char *devname, void *dev_id) | |
482 | { | |
483 | unsigned int irq; | |
484 | int retval; | |
485 | ||
486 | irq = bind_evtchn_to_irq(evtchn); | |
487 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
488 | if (retval != 0) { | |
489 | unbind_from_irq(irq); | |
490 | return retval; | |
491 | } | |
492 | ||
493 | return irq; | |
494 | } | |
495 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
496 | ||
497 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 498 | irq_handler_t handler, |
e46cdb66 JF |
499 | unsigned long irqflags, const char *devname, void *dev_id) |
500 | { | |
501 | unsigned int irq; | |
502 | int retval; | |
503 | ||
504 | irq = bind_virq_to_irq(virq, cpu); | |
505 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
506 | if (retval != 0) { | |
507 | unbind_from_irq(irq); | |
508 | return retval; | |
509 | } | |
510 | ||
511 | return irq; | |
512 | } | |
513 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
514 | ||
f87e4cac JF |
515 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
516 | unsigned int cpu, | |
517 | irq_handler_t handler, | |
518 | unsigned long irqflags, | |
519 | const char *devname, | |
520 | void *dev_id) | |
521 | { | |
522 | int irq, retval; | |
523 | ||
524 | irq = bind_ipi_to_irq(ipi, cpu); | |
525 | if (irq < 0) | |
526 | return irq; | |
527 | ||
528 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
529 | if (retval != 0) { | |
530 | unbind_from_irq(irq); | |
531 | return retval; | |
532 | } | |
533 | ||
534 | return irq; | |
535 | } | |
536 | ||
e46cdb66 JF |
537 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
538 | { | |
539 | free_irq(irq, dev_id); | |
540 | unbind_from_irq(irq); | |
541 | } | |
542 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
543 | ||
f87e4cac JF |
544 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
545 | { | |
546 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
547 | BUG_ON(irq < 0); | |
548 | notify_remote_via_irq(irq); | |
549 | } | |
550 | ||
ee523ca1 JF |
551 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
552 | { | |
553 | struct shared_info *sh = HYPERVISOR_shared_info; | |
554 | int cpu = smp_processor_id(); | |
555 | int i; | |
556 | unsigned long flags; | |
557 | static DEFINE_SPINLOCK(debug_lock); | |
558 | ||
559 | spin_lock_irqsave(&debug_lock, flags); | |
560 | ||
561 | printk("vcpu %d\n ", cpu); | |
562 | ||
563 | for_each_online_cpu(i) { | |
564 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
565 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 566 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
567 | v->evtchn_upcall_pending, |
568 | v->evtchn_pending_sel); | |
569 | } | |
570 | printk("pending:\n "); | |
571 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
572 | printk("%08lx%s", sh->evtchn_pending[i], | |
573 | i % 8 == 0 ? "\n " : " "); | |
574 | printk("\nmasks:\n "); | |
575 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
576 | printk("%08lx%s", sh->evtchn_mask[i], | |
577 | i % 8 == 0 ? "\n " : " "); | |
578 | ||
579 | printk("\nunmasked:\n "); | |
580 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
581 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
582 | i % 8 == 0 ? "\n " : " "); | |
583 | ||
584 | printk("\npending list:\n"); | |
585 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
586 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
587 | printk(" %d: event %d -> irq %d\n", | |
ced40d0f JF |
588 | cpu_from_evtchn(i), i, |
589 | evtchn_to_irq[i]); | |
ee523ca1 JF |
590 | } |
591 | } | |
592 | ||
593 | spin_unlock_irqrestore(&debug_lock, flags); | |
594 | ||
595 | return IRQ_HANDLED; | |
596 | } | |
597 | ||
f87e4cac | 598 | |
792dc4f6 JF |
599 | static void xen_do_irq(unsigned irq, struct pt_regs *regs) |
600 | { | |
601 | struct pt_regs *old_regs = set_irq_regs(regs); | |
602 | ||
603 | if (WARN_ON(irq == -1)) | |
604 | return; | |
605 | ||
606 | exit_idle(); | |
607 | irq_enter(); | |
608 | ||
609 | //printk("cpu %d handling irq %d\n", smp_processor_id(), info->irq); | |
610 | handle_irq(irq, regs); | |
611 | ||
612 | irq_exit(); | |
613 | ||
614 | set_irq_regs(old_regs); | |
615 | } | |
616 | ||
e46cdb66 JF |
617 | /* |
618 | * Search the CPUs pending events bitmasks. For each one found, map | |
619 | * the event number to an irq, and feed it into do_IRQ() for | |
620 | * handling. | |
621 | * | |
622 | * Xen uses a two-level bitmap to speed searching. The first level is | |
623 | * a bitset of words which contain pending event bits. The second | |
624 | * level is a bitset of pending events themselves. | |
625 | */ | |
75604d7f | 626 | void xen_evtchn_do_upcall(struct pt_regs *regs) |
e46cdb66 JF |
627 | { |
628 | int cpu = get_cpu(); | |
629 | struct shared_info *s = HYPERVISOR_shared_info; | |
630 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be JF |
631 | static DEFINE_PER_CPU(unsigned, nesting_count); |
632 | unsigned count; | |
e46cdb66 | 633 | |
229664be JF |
634 | do { |
635 | unsigned long pending_words; | |
e46cdb66 | 636 | |
229664be | 637 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 638 | |
229664be JF |
639 | if (__get_cpu_var(nesting_count)++) |
640 | goto out; | |
e46cdb66 | 641 | |
e849c3e9 IY |
642 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
643 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 644 | wmb(); |
e849c3e9 | 645 | #endif |
229664be JF |
646 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
647 | while (pending_words != 0) { | |
648 | unsigned long pending_bits; | |
649 | int word_idx = __ffs(pending_words); | |
650 | pending_words &= ~(1UL << word_idx); | |
651 | ||
652 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
653 | int bit_idx = __ffs(pending_bits); | |
654 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
655 | int irq = evtchn_to_irq[port]; | |
656 | ||
792dc4f6 | 657 | xen_do_irq(irq, regs); |
e46cdb66 JF |
658 | } |
659 | } | |
e46cdb66 | 660 | |
229664be JF |
661 | BUG_ON(!irqs_disabled()); |
662 | ||
663 | count = __get_cpu_var(nesting_count); | |
664 | __get_cpu_var(nesting_count) = 0; | |
665 | } while(count != 1); | |
666 | ||
667 | out: | |
e46cdb66 JF |
668 | put_cpu(); |
669 | } | |
670 | ||
eb1e305f JF |
671 | /* Rebind a new event channel to an existing irq. */ |
672 | void rebind_evtchn_irq(int evtchn, int irq) | |
673 | { | |
d77bbd4d JF |
674 | struct irq_info *info = info_for_irq(irq); |
675 | ||
eb1e305f JF |
676 | /* Make sure the irq is masked, since the new event channel |
677 | will also be masked. */ | |
678 | disable_irq(irq); | |
679 | ||
680 | spin_lock(&irq_mapping_update_lock); | |
681 | ||
682 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
683 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
684 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
685 | so there should be a proper type */ |
686 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
687 | |
688 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 689 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
690 | |
691 | spin_unlock(&irq_mapping_update_lock); | |
692 | ||
693 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 694 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
695 | |
696 | /* Unmask the event channel. */ | |
697 | enable_irq(irq); | |
698 | } | |
699 | ||
e46cdb66 JF |
700 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
701 | static void rebind_irq_to_cpu(unsigned irq, unsigned tcpu) | |
702 | { | |
703 | struct evtchn_bind_vcpu bind_vcpu; | |
704 | int evtchn = evtchn_from_irq(irq); | |
705 | ||
706 | if (!VALID_EVTCHN(evtchn)) | |
707 | return; | |
708 | ||
709 | /* Send future instances of this interrupt to other vcpu. */ | |
710 | bind_vcpu.port = evtchn; | |
711 | bind_vcpu.vcpu = tcpu; | |
712 | ||
713 | /* | |
714 | * If this fails, it usually just indicates that we're dealing with a | |
715 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
716 | * it, but don't do the xenlinux-level rebind in that case. | |
717 | */ | |
718 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
719 | bind_evtchn_to_cpu(evtchn, tcpu); | |
720 | } | |
721 | ||
722 | ||
0de26520 | 723 | static void set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 724 | { |
0de26520 | 725 | unsigned tcpu = cpumask_first(dest); |
e46cdb66 JF |
726 | rebind_irq_to_cpu(irq, tcpu); |
727 | } | |
728 | ||
642e0c88 IY |
729 | int resend_irq_on_evtchn(unsigned int irq) |
730 | { | |
731 | int masked, evtchn = evtchn_from_irq(irq); | |
732 | struct shared_info *s = HYPERVISOR_shared_info; | |
733 | ||
734 | if (!VALID_EVTCHN(evtchn)) | |
735 | return 1; | |
736 | ||
737 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
738 | sync_set_bit(evtchn, s->evtchn_pending); | |
739 | if (!masked) | |
740 | unmask_evtchn(evtchn); | |
741 | ||
742 | return 1; | |
743 | } | |
744 | ||
e46cdb66 JF |
745 | static void enable_dynirq(unsigned int irq) |
746 | { | |
747 | int evtchn = evtchn_from_irq(irq); | |
748 | ||
749 | if (VALID_EVTCHN(evtchn)) | |
750 | unmask_evtchn(evtchn); | |
751 | } | |
752 | ||
753 | static void disable_dynirq(unsigned int irq) | |
754 | { | |
755 | int evtchn = evtchn_from_irq(irq); | |
756 | ||
757 | if (VALID_EVTCHN(evtchn)) | |
758 | mask_evtchn(evtchn); | |
759 | } | |
760 | ||
761 | static void ack_dynirq(unsigned int irq) | |
762 | { | |
763 | int evtchn = evtchn_from_irq(irq); | |
764 | ||
765 | move_native_irq(irq); | |
766 | ||
767 | if (VALID_EVTCHN(evtchn)) | |
768 | clear_evtchn(evtchn); | |
769 | } | |
770 | ||
771 | static int retrigger_dynirq(unsigned int irq) | |
772 | { | |
773 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 774 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
775 | int ret = 0; |
776 | ||
777 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
778 | int masked; |
779 | ||
780 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
781 | sync_set_bit(evtchn, sh->evtchn_pending); | |
782 | if (!masked) | |
783 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
784 | ret = 1; |
785 | } | |
786 | ||
787 | return ret; | |
788 | } | |
789 | ||
0e91398f JF |
790 | static void restore_cpu_virqs(unsigned int cpu) |
791 | { | |
792 | struct evtchn_bind_virq bind_virq; | |
793 | int virq, irq, evtchn; | |
794 | ||
795 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
796 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
797 | continue; | |
798 | ||
ced40d0f | 799 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
800 | |
801 | /* Get a new binding from Xen. */ | |
802 | bind_virq.virq = virq; | |
803 | bind_virq.vcpu = cpu; | |
804 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
805 | &bind_virq) != 0) | |
806 | BUG(); | |
807 | evtchn = bind_virq.port; | |
808 | ||
809 | /* Record the new mapping. */ | |
810 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 811 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f JF |
812 | bind_evtchn_to_cpu(evtchn, cpu); |
813 | ||
814 | /* Ready for use. */ | |
815 | unmask_evtchn(evtchn); | |
816 | } | |
817 | } | |
818 | ||
819 | static void restore_cpu_ipis(unsigned int cpu) | |
820 | { | |
821 | struct evtchn_bind_ipi bind_ipi; | |
822 | int ipi, irq, evtchn; | |
823 | ||
824 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
825 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
826 | continue; | |
827 | ||
ced40d0f | 828 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
829 | |
830 | /* Get a new binding from Xen. */ | |
831 | bind_ipi.vcpu = cpu; | |
832 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
833 | &bind_ipi) != 0) | |
834 | BUG(); | |
835 | evtchn = bind_ipi.port; | |
836 | ||
837 | /* Record the new mapping. */ | |
838 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 839 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f JF |
840 | bind_evtchn_to_cpu(evtchn, cpu); |
841 | ||
842 | /* Ready for use. */ | |
843 | unmask_evtchn(evtchn); | |
844 | ||
845 | } | |
846 | } | |
847 | ||
2d9e1e2f JF |
848 | /* Clear an irq's pending state, in preparation for polling on it */ |
849 | void xen_clear_irq_pending(int irq) | |
850 | { | |
851 | int evtchn = evtchn_from_irq(irq); | |
852 | ||
853 | if (VALID_EVTCHN(evtchn)) | |
854 | clear_evtchn(evtchn); | |
855 | } | |
856 | ||
168d2f46 JF |
857 | void xen_set_irq_pending(int irq) |
858 | { | |
859 | int evtchn = evtchn_from_irq(irq); | |
860 | ||
861 | if (VALID_EVTCHN(evtchn)) | |
862 | set_evtchn(evtchn); | |
863 | } | |
864 | ||
865 | bool xen_test_irq_pending(int irq) | |
866 | { | |
867 | int evtchn = evtchn_from_irq(irq); | |
868 | bool ret = false; | |
869 | ||
870 | if (VALID_EVTCHN(evtchn)) | |
871 | ret = test_evtchn(evtchn); | |
872 | ||
873 | return ret; | |
874 | } | |
875 | ||
2d9e1e2f JF |
876 | /* Poll waiting for an irq to become pending. In the usual case, the |
877 | irq will be disabled so it won't deliver an interrupt. */ | |
878 | void xen_poll_irq(int irq) | |
879 | { | |
880 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
881 | ||
882 | if (VALID_EVTCHN(evtchn)) { | |
883 | struct sched_poll poll; | |
884 | ||
885 | poll.nr_ports = 1; | |
886 | poll.timeout = 0; | |
ff3c5362 | 887 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
888 | |
889 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
890 | BUG(); | |
891 | } | |
892 | } | |
893 | ||
0e91398f JF |
894 | void xen_irq_resume(void) |
895 | { | |
896 | unsigned int cpu, irq, evtchn; | |
897 | ||
898 | init_evtchn_cpu_bindings(); | |
899 | ||
900 | /* New event-channel space is not 'live' yet. */ | |
901 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
902 | mask_evtchn(evtchn); | |
903 | ||
904 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 905 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
906 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
907 | ||
908 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
909 | evtchn_to_irq[evtchn] = -1; | |
910 | ||
911 | for_each_possible_cpu(cpu) { | |
912 | restore_cpu_virqs(cpu); | |
913 | restore_cpu_ipis(cpu); | |
914 | } | |
915 | } | |
916 | ||
e46cdb66 JF |
917 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
918 | .name = "xen-dyn", | |
54a353a0 JF |
919 | |
920 | .disable = disable_dynirq, | |
e46cdb66 JF |
921 | .mask = disable_dynirq, |
922 | .unmask = enable_dynirq, | |
54a353a0 | 923 | |
e46cdb66 JF |
924 | .ack = ack_dynirq, |
925 | .set_affinity = set_affinity_irq, | |
926 | .retrigger = retrigger_dynirq, | |
927 | }; | |
928 | ||
929 | void __init xen_init_IRQ(void) | |
930 | { | |
931 | int i; | |
c7a3589e MT |
932 | size_t size = nr_cpu_ids * sizeof(struct cpu_evtchn_s); |
933 | ||
28e08861 CS |
934 | cpu_evtchn_mask_p = alloc_bootmem(size); |
935 | BUG_ON(cpu_evtchn_mask_p == NULL); | |
e46cdb66 JF |
936 | |
937 | init_evtchn_cpu_bindings(); | |
938 | ||
939 | /* No event channels are 'live' right now. */ | |
940 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
941 | mask_evtchn(i); | |
942 | ||
e46cdb66 JF |
943 | irq_ctx_init(smp_processor_id()); |
944 | } |