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Commit | Line | Data |
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d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
b346ff46 FB |
21 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
22 | #define DEBUG_DISAS | |
23 | ||
33417e70 FB |
24 | #ifndef glue |
25 | #define xglue(x, y) x ## y | |
26 | #define glue(x, y) xglue(x, y) | |
27 | #define stringify(s) tostring(s) | |
28 | #define tostring(s) #s | |
29 | #endif | |
30 | ||
2e03286b | 31 | #ifndef likely |
c98baaac | 32 | #if __GNUC__ < 3 |
33417e70 FB |
33 | #define __builtin_expect(x, n) (x) |
34 | #endif | |
35 | ||
cbecba26 JM |
36 | #define likely(x) __builtin_expect(!!(x), 1) |
37 | #define unlikely(x) __builtin_expect(!!(x), 0) | |
2e03286b | 38 | #endif |
cbecba26 | 39 | |
29f640e2 | 40 | #ifndef always_inline |
8a84de23 | 41 | #if (__GNUC__ < 3) || defined(__APPLE__) |
29f640e2 JM |
42 | #define always_inline inline |
43 | #else | |
44 | #define always_inline __attribute__ (( always_inline )) inline | |
45 | #endif | |
46 | #endif | |
47 | ||
e2222c39 FB |
48 | #ifdef __i386__ |
49 | #define REGPARM(n) __attribute((regparm(n))) | |
50 | #else | |
51 | #define REGPARM(n) | |
52 | #endif | |
53 | ||
b346ff46 FB |
54 | /* is_jmp field values */ |
55 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
56 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
57 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
58 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
59 | ||
60 | struct TranslationBlock; | |
61 | ||
62 | /* XXX: make safe guess about sizes */ | |
63 | #define MAX_OP_PER_INSTR 32 | |
64 | #define OPC_BUF_SIZE 512 | |
65 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) | |
66 | ||
67 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) | |
68 | ||
69 | extern uint16_t gen_opc_buf[OPC_BUF_SIZE]; | |
70 | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE]; | |
c27004ec FB |
71 | extern long gen_labels[OPC_BUF_SIZE]; |
72 | extern int nb_gen_labels; | |
73 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; | |
74 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE]; | |
66e85a21 | 75 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
b346ff46 | 76 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
c3278b7b | 77 | extern target_ulong gen_opc_jump_pc[2]; |
30d6cb84 | 78 | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE]; |
b346ff46 | 79 | |
9886cc16 FB |
80 | typedef void (GenOpFunc)(void); |
81 | typedef void (GenOpFunc1)(long); | |
82 | typedef void (GenOpFunc2)(long, long); | |
83 | typedef void (GenOpFunc3)(long, long, long); | |
3b46e624 | 84 | |
b346ff46 FB |
85 | #if defined(TARGET_I386) |
86 | ||
33417e70 | 87 | void optimize_flags_init(void); |
d4e8164f | 88 | |
b346ff46 FB |
89 | #endif |
90 | ||
91 | extern FILE *logfile; | |
92 | extern int loglevel; | |
93 | ||
4c3a88a2 FB |
94 | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
95 | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); | |
b346ff46 | 96 | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
4c3a88a2 | 97 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
b346ff46 | 98 | int max_code_size, int *gen_code_size_ptr); |
5fafdf24 | 99 | int cpu_restore_state(struct TranslationBlock *tb, |
58fe2f10 FB |
100 | CPUState *env, unsigned long searched_pc, |
101 | void *puc); | |
102 | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, | |
103 | int max_code_size, int *gen_code_size_ptr); | |
5fafdf24 | 104 | int cpu_restore_state_copy(struct TranslationBlock *tb, |
58fe2f10 FB |
105 | CPUState *env, unsigned long searched_pc, |
106 | void *puc); | |
2e12669a | 107 | void cpu_resume_from_signal(CPUState *env1, void *puc); |
6a00d601 | 108 | void cpu_exec_init(CPUState *env); |
53a5960a | 109 | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
5fafdf24 | 110 | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, |
2e12669a | 111 | int is_cpu_write_access); |
4390df51 | 112 | void tb_invalidate_page_range(target_ulong start, target_ulong end); |
2e12669a | 113 | void tlb_flush_page(CPUState *env, target_ulong addr); |
ee8b7021 | 114 | void tlb_flush(CPUState *env, int flush_global); |
5fafdf24 TS |
115 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
116 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 117 | int mmu_idx, int is_softmmu); |
5fafdf24 TS |
118 | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
119 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 120 | int mmu_idx, int is_softmmu) |
84b7b8e7 FB |
121 | { |
122 | if (prot & PAGE_READ) | |
123 | prot |= PAGE_EXEC; | |
6ebbf390 | 124 | return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
84b7b8e7 | 125 | } |
d4e8164f FB |
126 | |
127 | #define CODE_GEN_MAX_SIZE 65536 | |
128 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ | |
129 | ||
4390df51 FB |
130 | #define CODE_GEN_PHYS_HASH_BITS 15 |
131 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) | |
132 | ||
d4e8164f | 133 | /* maximum total translate dcode allocated */ |
4390df51 FB |
134 | |
135 | /* NOTE: the translated code area cannot be too big because on some | |
c4c7e3e6 | 136 | archs the range of "fast" function calls is limited. Here is a |
4390df51 FB |
137 | summary of the ranges: |
138 | ||
139 | i386 : signed 32 bits | |
140 | arm : signed 26 bits | |
141 | ppc : signed 24 bits | |
142 | sparc : signed 32 bits | |
143 | alpha : signed 23 bits | |
144 | */ | |
145 | ||
146 | #if defined(__alpha__) | |
147 | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) | |
b8076a74 FB |
148 | #elif defined(__ia64) |
149 | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ | |
4390df51 | 150 | #elif defined(__powerpc__) |
c4c7e3e6 | 151 | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
4390df51 | 152 | #else |
c98baaac | 153 | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
4390df51 FB |
154 | #endif |
155 | ||
d4e8164f FB |
156 | //#define CODE_GEN_BUFFER_SIZE (128 * 1024) |
157 | ||
4390df51 FB |
158 | /* estimated block size for TB allocation */ |
159 | /* XXX: use a per code average code fragment size and modulate it | |
160 | according to the host CPU */ | |
161 | #if defined(CONFIG_SOFTMMU) | |
162 | #define CODE_GEN_AVG_BLOCK_SIZE 128 | |
163 | #else | |
164 | #define CODE_GEN_AVG_BLOCK_SIZE 64 | |
165 | #endif | |
166 | ||
167 | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE) | |
168 | ||
5fafdf24 | 169 | #if defined(__powerpc__) |
4390df51 FB |
170 | #define USE_DIRECT_JUMP |
171 | #endif | |
67b915a5 | 172 | #if defined(__i386__) && !defined(_WIN32) |
d4e8164f FB |
173 | #define USE_DIRECT_JUMP |
174 | #endif | |
175 | ||
176 | typedef struct TranslationBlock { | |
2e12669a FB |
177 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
178 | target_ulong cs_base; /* CS base for this block */ | |
c068688b | 179 | uint64_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
180 | uint16_t size; /* size of target code for this block (1 <= |
181 | size <= TARGET_PAGE_SIZE) */ | |
58fe2f10 | 182 | uint16_t cflags; /* compile flags */ |
bf088061 FB |
183 | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
184 | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ | |
185 | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ | |
2e12669a | 186 | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
58fe2f10 | 187 | |
d4e8164f | 188 | uint8_t *tc_ptr; /* pointer to the translated code */ |
4390df51 | 189 | /* next matching tb for physical address. */ |
5fafdf24 | 190 | struct TranslationBlock *phys_hash_next; |
4390df51 FB |
191 | /* first and second physical page containing code. The lower bit |
192 | of the pointer tells the index in page_next[] */ | |
5fafdf24 TS |
193 | struct TranslationBlock *page_next[2]; |
194 | target_ulong page_addr[2]; | |
4390df51 | 195 | |
d4e8164f FB |
196 | /* the following data are used to directly call another TB from |
197 | the code of this one. */ | |
198 | uint16_t tb_next_offset[2]; /* offset of original jump target */ | |
199 | #ifdef USE_DIRECT_JUMP | |
4cbb86e1 | 200 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
d4e8164f | 201 | #else |
95f7652d | 202 | uint32_t tb_next[2]; /* address of jump generated code */ |
d4e8164f FB |
203 | #endif |
204 | /* list of TBs jumping to this one. This is a circular list using | |
205 | the two least significant bits of the pointers to tell what is | |
206 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = | |
207 | jmp_first */ | |
5fafdf24 | 208 | struct TranslationBlock *jmp_next[2]; |
d4e8164f FB |
209 | struct TranslationBlock *jmp_first; |
210 | } TranslationBlock; | |
211 | ||
b362e5e0 PB |
212 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
213 | { | |
214 | target_ulong tmp; | |
215 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
216 | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK; | |
217 | } | |
218 | ||
8a40a180 | 219 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
d4e8164f | 220 | { |
b362e5e0 PB |
221 | target_ulong tmp; |
222 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
223 | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) | | |
224 | (tmp & TB_JMP_ADDR_MASK)); | |
d4e8164f FB |
225 | } |
226 | ||
4390df51 FB |
227 | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
228 | { | |
229 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); | |
230 | } | |
231 | ||
c27004ec | 232 | TranslationBlock *tb_alloc(target_ulong pc); |
0124311e | 233 | void tb_flush(CPUState *env); |
5fafdf24 | 234 | void tb_link_phys(TranslationBlock *tb, |
4390df51 | 235 | target_ulong phys_pc, target_ulong phys_page2); |
d4e8164f | 236 | |
4390df51 | 237 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
d4e8164f FB |
238 | |
239 | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; | |
240 | extern uint8_t *code_gen_ptr; | |
241 | ||
4390df51 FB |
242 | #if defined(USE_DIRECT_JUMP) |
243 | ||
244 | #if defined(__powerpc__) | |
4cbb86e1 | 245 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
d4e8164f FB |
246 | { |
247 | uint32_t val, *ptr; | |
d4e8164f FB |
248 | |
249 | /* patch the branch destination */ | |
4cbb86e1 | 250 | ptr = (uint32_t *)jmp_addr; |
d4e8164f | 251 | val = *ptr; |
4cbb86e1 | 252 | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
d4e8164f FB |
253 | *ptr = val; |
254 | /* flush icache */ | |
255 | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); | |
256 | asm volatile ("sync" : : : "memory"); | |
257 | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); | |
258 | asm volatile ("sync" : : : "memory"); | |
259 | asm volatile ("isync" : : : "memory"); | |
260 | } | |
4390df51 FB |
261 | #elif defined(__i386__) |
262 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) | |
263 | { | |
264 | /* patch the branch destination */ | |
265 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); | |
266 | /* no need to flush icache explicitely */ | |
267 | } | |
268 | #endif | |
d4e8164f | 269 | |
5fafdf24 | 270 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
4cbb86e1 FB |
271 | int n, unsigned long addr) |
272 | { | |
273 | unsigned long offset; | |
274 | ||
275 | offset = tb->tb_jmp_offset[n]; | |
276 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
277 | offset = tb->tb_jmp_offset[n + 2]; | |
278 | if (offset != 0xffff) | |
279 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
280 | } | |
281 | ||
d4e8164f FB |
282 | #else |
283 | ||
284 | /* set the jump target */ | |
5fafdf24 | 285 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
d4e8164f FB |
286 | int n, unsigned long addr) |
287 | { | |
95f7652d | 288 | tb->tb_next[n] = addr; |
d4e8164f FB |
289 | } |
290 | ||
291 | #endif | |
292 | ||
5fafdf24 | 293 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
294 | TranslationBlock *tb_next) |
295 | { | |
cf25629d FB |
296 | /* NOTE: this test is only needed for thread safety */ |
297 | if (!tb->jmp_next[n]) { | |
298 | /* patch the native jump address */ | |
299 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); | |
3b46e624 | 300 | |
cf25629d FB |
301 | /* add in TB jmp circular list */ |
302 | tb->jmp_next[n] = tb_next->jmp_first; | |
303 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); | |
304 | } | |
d4e8164f FB |
305 | } |
306 | ||
a513fe19 FB |
307 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
308 | ||
d4e8164f FB |
309 | #ifndef offsetof |
310 | #define offsetof(type, field) ((size_t) &((type *)0)->field) | |
311 | #endif | |
312 | ||
d549f7d9 FB |
313 | #if defined(_WIN32) |
314 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
315 | #define ASM_PREVIOUS_SECTION ".section .text\n" | |
316 | #elif defined(__APPLE__) | |
317 | #define ASM_DATA_SECTION ".data\n" | |
318 | #define ASM_PREVIOUS_SECTION ".text\n" | |
d549f7d9 FB |
319 | #else |
320 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
321 | #define ASM_PREVIOUS_SECTION ".previous\n" | |
d549f7d9 FB |
322 | #endif |
323 | ||
75913b72 FB |
324 | #define ASM_OP_LABEL_NAME(n, opname) \ |
325 | ASM_NAME(__op_label) #n "." ASM_NAME(opname) | |
326 | ||
b346ff46 FB |
327 | #if defined(__powerpc__) |
328 | ||
4390df51 | 329 | /* we patch the jump instruction directly */ |
ae063a68 | 330 | #define GOTO_TB(opname, tbparam, n)\ |
b346ff46 | 331 | do {\ |
d549f7d9 | 332 | asm volatile (ASM_DATA_SECTION\ |
75913b72 | 333 | ASM_OP_LABEL_NAME(n, opname) ":\n"\ |
9257a9e4 | 334 | ".long 1f\n"\ |
d549f7d9 FB |
335 | ASM_PREVIOUS_SECTION \ |
336 | "b " ASM_NAME(__op_jmp) #n "\n"\ | |
9257a9e4 | 337 | "1:\n");\ |
4390df51 FB |
338 | } while (0) |
339 | ||
340 | #elif defined(__i386__) && defined(USE_DIRECT_JUMP) | |
341 | ||
342 | /* we patch the jump instruction directly */ | |
ae063a68 | 343 | #define GOTO_TB(opname, tbparam, n)\ |
c27004ec FB |
344 | do {\ |
345 | asm volatile (".section .data\n"\ | |
75913b72 | 346 | ASM_OP_LABEL_NAME(n, opname) ":\n"\ |
c27004ec FB |
347 | ".long 1f\n"\ |
348 | ASM_PREVIOUS_SECTION \ | |
349 | "jmp " ASM_NAME(__op_jmp) #n "\n"\ | |
350 | "1:\n");\ | |
351 | } while (0) | |
352 | ||
9bbc5cc8 TS |
353 | #elif defined(__s390__) |
354 | /* GCC spills R13, so we have to restore it before branching away */ | |
355 | ||
356 | #define GOTO_TB(opname, tbparam, n)\ | |
357 | do {\ | |
358 | static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ | |
359 | static void __attribute__((used)) *__op_label ## n \ | |
360 | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ | |
361 | __asm__ __volatile__ ( \ | |
362 | "l %%r13,52(%%r15)\n" \ | |
363 | "br %0\n" \ | |
364 | : : "r" (((TranslationBlock*)tbparam)->tb_next[n]));\ | |
365 | \ | |
366 | for(;*((int*)0);); /* just to keep GCC busy */ \ | |
367 | label ## n: ;\ | |
368 | dummy_label ## n: ;\ | |
369 | } while(0) | |
370 | ||
b346ff46 FB |
371 | #else |
372 | ||
373 | /* jump to next block operations (more portable code, does not need | |
374 | cache flushing, but slower because of indirect jump) */ | |
ae063a68 | 375 | #define GOTO_TB(opname, tbparam, n)\ |
b346ff46 | 376 | do {\ |
6d8aa3bf AZ |
377 | static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ |
378 | static void __attribute__((used)) *__op_label ## n \ | |
75913b72 | 379 | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
b346ff46 | 380 | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
ae063a68 FB |
381 | label ## n: ;\ |
382 | dummy_label ## n: ;\ | |
b346ff46 FB |
383 | } while (0) |
384 | ||
ae063a68 FB |
385 | #endif |
386 | ||
33417e70 FB |
387 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
388 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 389 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
33417e70 | 390 | |
204a1b8d | 391 | #if defined(__powerpc__) |
d4e8164f FB |
392 | static inline int testandset (int *p) |
393 | { | |
394 | int ret; | |
395 | __asm__ __volatile__ ( | |
02e1ec9b FB |
396 | "0: lwarx %0,0,%1\n" |
397 | " xor. %0,%3,%0\n" | |
398 | " bne 1f\n" | |
399 | " stwcx. %2,0,%1\n" | |
400 | " bne- 0b\n" | |
d4e8164f FB |
401 | "1: " |
402 | : "=&r" (ret) | |
403 | : "r" (p), "r" (1), "r" (0) | |
404 | : "cr0", "memory"); | |
405 | return ret; | |
406 | } | |
204a1b8d | 407 | #elif defined(__i386__) |
d4e8164f FB |
408 | static inline int testandset (int *p) |
409 | { | |
4955a2cd | 410 | long int readval = 0; |
3b46e624 | 411 | |
4955a2cd FB |
412 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
413 | : "+m" (*p), "+a" (readval) | |
414 | : "r" (1) | |
415 | : "cc"); | |
416 | return readval; | |
d4e8164f | 417 | } |
204a1b8d | 418 | #elif defined(__x86_64__) |
bc51c5c9 FB |
419 | static inline int testandset (int *p) |
420 | { | |
4955a2cd | 421 | long int readval = 0; |
3b46e624 | 422 | |
4955a2cd FB |
423 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
424 | : "+m" (*p), "+a" (readval) | |
425 | : "r" (1) | |
426 | : "cc"); | |
427 | return readval; | |
bc51c5c9 | 428 | } |
204a1b8d | 429 | #elif defined(__s390__) |
d4e8164f FB |
430 | static inline int testandset (int *p) |
431 | { | |
432 | int ret; | |
433 | ||
434 | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n" | |
435 | " jl 0b" | |
436 | : "=&d" (ret) | |
5fafdf24 | 437 | : "r" (1), "a" (p), "0" (*p) |
d4e8164f FB |
438 | : "cc", "memory" ); |
439 | return ret; | |
440 | } | |
204a1b8d | 441 | #elif defined(__alpha__) |
2f87c607 | 442 | static inline int testandset (int *p) |
d4e8164f FB |
443 | { |
444 | int ret; | |
445 | unsigned long one; | |
446 | ||
447 | __asm__ __volatile__ ("0: mov 1,%2\n" | |
448 | " ldl_l %0,%1\n" | |
449 | " stl_c %2,%1\n" | |
450 | " beq %2,1f\n" | |
451 | ".subsection 2\n" | |
452 | "1: br 0b\n" | |
453 | ".previous" | |
454 | : "=r" (ret), "=m" (*p), "=r" (one) | |
455 | : "m" (*p)); | |
456 | return ret; | |
457 | } | |
204a1b8d | 458 | #elif defined(__sparc__) |
d4e8164f FB |
459 | static inline int testandset (int *p) |
460 | { | |
461 | int ret; | |
462 | ||
463 | __asm__ __volatile__("ldstub [%1], %0" | |
464 | : "=r" (ret) | |
465 | : "r" (p) | |
466 | : "memory"); | |
467 | ||
468 | return (ret ? 1 : 0); | |
469 | } | |
204a1b8d | 470 | #elif defined(__arm__) |
a95c6790 FB |
471 | static inline int testandset (int *spinlock) |
472 | { | |
473 | register unsigned int ret; | |
474 | __asm__ __volatile__("swp %0, %1, [%2]" | |
475 | : "=r"(ret) | |
476 | : "0"(1), "r"(spinlock)); | |
3b46e624 | 477 | |
a95c6790 FB |
478 | return ret; |
479 | } | |
204a1b8d | 480 | #elif defined(__mc68000) |
38e584a0 FB |
481 | static inline int testandset (int *p) |
482 | { | |
483 | char ret; | |
484 | __asm__ __volatile__("tas %1; sne %0" | |
485 | : "=r" (ret) | |
486 | : "m" (p) | |
487 | : "cc","memory"); | |
4955a2cd | 488 | return ret; |
38e584a0 | 489 | } |
204a1b8d | 490 | #elif defined(__ia64) |
38e584a0 | 491 | |
b8076a74 FB |
492 | #include <ia64intrin.h> |
493 | ||
494 | static inline int testandset (int *p) | |
495 | { | |
496 | return __sync_lock_test_and_set (p, 1); | |
497 | } | |
204a1b8d | 498 | #elif defined(__mips__) |
c4b89d18 TS |
499 | static inline int testandset (int *p) |
500 | { | |
501 | int ret; | |
502 | ||
503 | __asm__ __volatile__ ( | |
504 | " .set push \n" | |
505 | " .set noat \n" | |
506 | " .set mips2 \n" | |
507 | "1: li $1, 1 \n" | |
508 | " ll %0, %1 \n" | |
509 | " sc $1, %1 \n" | |
976a0d0d | 510 | " beqz $1, 1b \n" |
c4b89d18 TS |
511 | " .set pop " |
512 | : "=r" (ret), "+R" (*p) | |
513 | : | |
514 | : "memory"); | |
515 | ||
516 | return ret; | |
517 | } | |
204a1b8d TS |
518 | #else |
519 | #error unimplemented CPU support | |
c4b89d18 TS |
520 | #endif |
521 | ||
d4e8164f FB |
522 | typedef int spinlock_t; |
523 | ||
524 | #define SPIN_LOCK_UNLOCKED 0 | |
525 | ||
aebcb60e | 526 | #if defined(CONFIG_USER_ONLY) |
d4e8164f FB |
527 | static inline void spin_lock(spinlock_t *lock) |
528 | { | |
529 | while (testandset(lock)); | |
530 | } | |
531 | ||
532 | static inline void spin_unlock(spinlock_t *lock) | |
533 | { | |
534 | *lock = 0; | |
535 | } | |
536 | ||
537 | static inline int spin_trylock(spinlock_t *lock) | |
538 | { | |
539 | return !testandset(lock); | |
540 | } | |
3c1cf9fa FB |
541 | #else |
542 | static inline void spin_lock(spinlock_t *lock) | |
543 | { | |
544 | } | |
545 | ||
546 | static inline void spin_unlock(spinlock_t *lock) | |
547 | { | |
548 | } | |
549 | ||
550 | static inline int spin_trylock(spinlock_t *lock) | |
551 | { | |
552 | return 1; | |
553 | } | |
554 | #endif | |
d4e8164f FB |
555 | |
556 | extern spinlock_t tb_lock; | |
557 | ||
36bdbe54 | 558 | extern int tb_invalidated_flag; |
6e59c1db | 559 | |
e95c8d51 | 560 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 561 | |
6ebbf390 | 562 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
6e59c1db FB |
563 | void *retaddr); |
564 | ||
6ebbf390 | 565 | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
6e59c1db FB |
566 | #define MEMSUFFIX _code |
567 | #define env cpu_single_env | |
568 | ||
569 | #define DATA_SIZE 1 | |
570 | #include "softmmu_header.h" | |
571 | ||
572 | #define DATA_SIZE 2 | |
573 | #include "softmmu_header.h" | |
574 | ||
575 | #define DATA_SIZE 4 | |
576 | #include "softmmu_header.h" | |
577 | ||
c27004ec FB |
578 | #define DATA_SIZE 8 |
579 | #include "softmmu_header.h" | |
580 | ||
6e59c1db FB |
581 | #undef ACCESS_TYPE |
582 | #undef MEMSUFFIX | |
583 | #undef env | |
584 | ||
585 | #endif | |
4390df51 FB |
586 | |
587 | #if defined(CONFIG_USER_ONLY) | |
588 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) | |
589 | { | |
590 | return addr; | |
591 | } | |
592 | #else | |
593 | /* NOTE: this function can trigger an exception */ | |
1ccde1cb FB |
594 | /* NOTE2: the returned address is not exactly the physical address: it |
595 | is the offset relative to phys_ram_base */ | |
4390df51 FB |
596 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
597 | { | |
6ebbf390 | 598 | int mmu_idx, index, pd; |
4390df51 FB |
599 | |
600 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
6ebbf390 JM |
601 | mmu_idx = cpu_mmu_index(env); |
602 | if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code != | |
4390df51 | 603 | (addr & TARGET_PAGE_MASK), 0)) { |
c27004ec FB |
604 | ldub_code(addr); |
605 | } | |
6ebbf390 | 606 | pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; |
2a4188a3 | 607 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
647de6ca | 608 | #if defined(TARGET_SPARC) || defined(TARGET_MIPS) |
6c36d3fa BS |
609 | do_unassigned_access(addr, 0, 1, 0); |
610 | #else | |
36d23958 | 611 | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
6c36d3fa | 612 | #endif |
4390df51 | 613 | } |
6ebbf390 | 614 | return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base; |
4390df51 FB |
615 | } |
616 | #endif | |
9df217a3 | 617 | |
9df217a3 | 618 | #ifdef USE_KQEMU |
f32fc648 FB |
619 | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
620 | ||
9df217a3 FB |
621 | int kqemu_init(CPUState *env); |
622 | int kqemu_cpu_exec(CPUState *env); | |
623 | void kqemu_flush_page(CPUState *env, target_ulong addr); | |
624 | void kqemu_flush(CPUState *env, int global); | |
4b7df22f | 625 | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr); |
f32fc648 | 626 | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr); |
a332e112 | 627 | void kqemu_cpu_interrupt(CPUState *env); |
f32fc648 | 628 | void kqemu_record_dump(void); |
9df217a3 FB |
629 | |
630 | static inline int kqemu_is_ok(CPUState *env) | |
631 | { | |
632 | return(env->kqemu_enabled && | |
5fafdf24 | 633 | (env->cr[0] & CR0_PE_MASK) && |
f32fc648 | 634 | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
9df217a3 | 635 | (env->eflags & IF_MASK) && |
f32fc648 | 636 | !(env->eflags & VM_MASK) && |
5fafdf24 | 637 | (env->kqemu_enabled == 2 || |
f32fc648 FB |
638 | ((env->hflags & HF_CPL_MASK) == 3 && |
639 | (env->eflags & IOPL_MASK) != IOPL_MASK))); | |
9df217a3 FB |
640 | } |
641 | ||
642 | #endif |