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Commit | Line | Data |
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d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
b346ff46 FB |
21 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
22 | #define DEBUG_DISAS | |
23 | ||
24 | /* is_jmp field values */ | |
25 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
26 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
27 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
28 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
29 | ||
30 | struct TranslationBlock; | |
31 | ||
32 | /* XXX: make safe guess about sizes */ | |
33 | #define MAX_OP_PER_INSTR 32 | |
0115be31 PB |
34 | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */ |
35 | #define MAX_OPC_PARAM 10 | |
b346ff46 FB |
36 | #define OPC_BUF_SIZE 512 |
37 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) | |
38 | ||
a208e54a PB |
39 | /* Maximum size a TCG op can expand to. This is complicated because a |
40 | single op may require several host instructions and regirster reloads. | |
41 | For now take a wild guess at 128 bytes, which should allow at least | |
42 | a couple of fixup instructions per argument. */ | |
43 | #define TCG_MAX_OP_SIZE 128 | |
44 | ||
0115be31 | 45 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) |
b346ff46 | 46 | |
c27004ec FB |
47 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; |
48 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE]; | |
66e85a21 | 49 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
b346ff46 | 50 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
c3278b7b | 51 | extern target_ulong gen_opc_jump_pc[2]; |
30d6cb84 | 52 | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE]; |
b346ff46 | 53 | |
9886cc16 FB |
54 | typedef void (GenOpFunc)(void); |
55 | typedef void (GenOpFunc1)(long); | |
56 | typedef void (GenOpFunc2)(long, long); | |
57 | typedef void (GenOpFunc3)(long, long, long); | |
3b46e624 | 58 | |
b346ff46 FB |
59 | #if defined(TARGET_I386) |
60 | ||
33417e70 | 61 | void optimize_flags_init(void); |
d4e8164f | 62 | |
b346ff46 FB |
63 | #endif |
64 | ||
65 | extern FILE *logfile; | |
66 | extern int loglevel; | |
67 | ||
4c3a88a2 FB |
68 | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
69 | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); | |
d2856f1a AJ |
70 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
71 | unsigned long searched_pc, int pc_pos, void *puc); | |
72 | ||
d07bde88 | 73 | unsigned long code_gen_max_block_size(void); |
57fec1fe | 74 | void cpu_gen_init(void); |
4c3a88a2 | 75 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
d07bde88 | 76 | int *gen_code_size_ptr); |
5fafdf24 | 77 | int cpu_restore_state(struct TranslationBlock *tb, |
58fe2f10 FB |
78 | CPUState *env, unsigned long searched_pc, |
79 | void *puc); | |
80 | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, | |
81 | int max_code_size, int *gen_code_size_ptr); | |
5fafdf24 | 82 | int cpu_restore_state_copy(struct TranslationBlock *tb, |
58fe2f10 FB |
83 | CPUState *env, unsigned long searched_pc, |
84 | void *puc); | |
2e12669a | 85 | void cpu_resume_from_signal(CPUState *env1, void *puc); |
6a00d601 | 86 | void cpu_exec_init(CPUState *env); |
53a5960a | 87 | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
00f82b8a | 88 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
2e12669a | 89 | int is_cpu_write_access); |
4390df51 | 90 | void tb_invalidate_page_range(target_ulong start, target_ulong end); |
2e12669a | 91 | void tlb_flush_page(CPUState *env, target_ulong addr); |
ee8b7021 | 92 | void tlb_flush(CPUState *env, int flush_global); |
5fafdf24 TS |
93 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
94 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 95 | int mmu_idx, int is_softmmu); |
5fafdf24 TS |
96 | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
97 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 98 | int mmu_idx, int is_softmmu) |
84b7b8e7 FB |
99 | { |
100 | if (prot & PAGE_READ) | |
101 | prot |= PAGE_EXEC; | |
6ebbf390 | 102 | return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
84b7b8e7 | 103 | } |
d4e8164f | 104 | |
d4e8164f FB |
105 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
106 | ||
4390df51 FB |
107 | #define CODE_GEN_PHYS_HASH_BITS 15 |
108 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) | |
109 | ||
d4e8164f | 110 | /* maximum total translate dcode allocated */ |
4390df51 FB |
111 | |
112 | /* NOTE: the translated code area cannot be too big because on some | |
c4c7e3e6 | 113 | archs the range of "fast" function calls is limited. Here is a |
4390df51 FB |
114 | summary of the ranges: |
115 | ||
116 | i386 : signed 32 bits | |
117 | arm : signed 26 bits | |
118 | ppc : signed 24 bits | |
119 | sparc : signed 32 bits | |
120 | alpha : signed 23 bits | |
121 | */ | |
122 | ||
123 | #if defined(__alpha__) | |
124 | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) | |
b8076a74 FB |
125 | #elif defined(__ia64) |
126 | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ | |
4390df51 | 127 | #elif defined(__powerpc__) |
c4c7e3e6 | 128 | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
4390df51 | 129 | #else |
57fec1fe | 130 | /* XXX: make it dynamic on x86 */ |
c98baaac | 131 | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
4390df51 FB |
132 | #endif |
133 | ||
d4e8164f FB |
134 | //#define CODE_GEN_BUFFER_SIZE (128 * 1024) |
135 | ||
4390df51 FB |
136 | /* estimated block size for TB allocation */ |
137 | /* XXX: use a per code average code fragment size and modulate it | |
138 | according to the host CPU */ | |
139 | #if defined(CONFIG_SOFTMMU) | |
140 | #define CODE_GEN_AVG_BLOCK_SIZE 128 | |
141 | #else | |
142 | #define CODE_GEN_AVG_BLOCK_SIZE 64 | |
143 | #endif | |
144 | ||
145 | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE) | |
146 | ||
57fec1fe | 147 | #if defined(__powerpc__) || defined(__x86_64__) |
4390df51 FB |
148 | #define USE_DIRECT_JUMP |
149 | #endif | |
67b915a5 | 150 | #if defined(__i386__) && !defined(_WIN32) |
d4e8164f FB |
151 | #define USE_DIRECT_JUMP |
152 | #endif | |
153 | ||
154 | typedef struct TranslationBlock { | |
2e12669a FB |
155 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
156 | target_ulong cs_base; /* CS base for this block */ | |
c068688b | 157 | uint64_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
158 | uint16_t size; /* size of target code for this block (1 <= |
159 | size <= TARGET_PAGE_SIZE) */ | |
58fe2f10 | 160 | uint16_t cflags; /* compile flags */ |
bf088061 FB |
161 | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
162 | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ | |
163 | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ | |
2e12669a | 164 | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
58fe2f10 | 165 | |
d4e8164f | 166 | uint8_t *tc_ptr; /* pointer to the translated code */ |
4390df51 | 167 | /* next matching tb for physical address. */ |
5fafdf24 | 168 | struct TranslationBlock *phys_hash_next; |
4390df51 FB |
169 | /* first and second physical page containing code. The lower bit |
170 | of the pointer tells the index in page_next[] */ | |
5fafdf24 TS |
171 | struct TranslationBlock *page_next[2]; |
172 | target_ulong page_addr[2]; | |
4390df51 | 173 | |
d4e8164f FB |
174 | /* the following data are used to directly call another TB from |
175 | the code of this one. */ | |
176 | uint16_t tb_next_offset[2]; /* offset of original jump target */ | |
177 | #ifdef USE_DIRECT_JUMP | |
4cbb86e1 | 178 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
d4e8164f | 179 | #else |
57fec1fe | 180 | unsigned long tb_next[2]; /* address of jump generated code */ |
d4e8164f FB |
181 | #endif |
182 | /* list of TBs jumping to this one. This is a circular list using | |
183 | the two least significant bits of the pointers to tell what is | |
184 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = | |
185 | jmp_first */ | |
5fafdf24 | 186 | struct TranslationBlock *jmp_next[2]; |
d4e8164f FB |
187 | struct TranslationBlock *jmp_first; |
188 | } TranslationBlock; | |
189 | ||
b362e5e0 PB |
190 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
191 | { | |
192 | target_ulong tmp; | |
193 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
194 | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK; | |
195 | } | |
196 | ||
8a40a180 | 197 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
d4e8164f | 198 | { |
b362e5e0 PB |
199 | target_ulong tmp; |
200 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
201 | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) | | |
202 | (tmp & TB_JMP_ADDR_MASK)); | |
d4e8164f FB |
203 | } |
204 | ||
4390df51 FB |
205 | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
206 | { | |
207 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); | |
208 | } | |
209 | ||
c27004ec | 210 | TranslationBlock *tb_alloc(target_ulong pc); |
0124311e | 211 | void tb_flush(CPUState *env); |
5fafdf24 | 212 | void tb_link_phys(TranslationBlock *tb, |
4390df51 | 213 | target_ulong phys_pc, target_ulong phys_page2); |
d4e8164f | 214 | |
4390df51 | 215 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
d4e8164f FB |
216 | |
217 | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; | |
218 | extern uint8_t *code_gen_ptr; | |
219 | ||
4390df51 FB |
220 | #if defined(USE_DIRECT_JUMP) |
221 | ||
222 | #if defined(__powerpc__) | |
4cbb86e1 | 223 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
d4e8164f FB |
224 | { |
225 | uint32_t val, *ptr; | |
d4e8164f FB |
226 | |
227 | /* patch the branch destination */ | |
4cbb86e1 | 228 | ptr = (uint32_t *)jmp_addr; |
d4e8164f | 229 | val = *ptr; |
4cbb86e1 | 230 | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
d4e8164f FB |
231 | *ptr = val; |
232 | /* flush icache */ | |
233 | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); | |
234 | asm volatile ("sync" : : : "memory"); | |
235 | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); | |
236 | asm volatile ("sync" : : : "memory"); | |
237 | asm volatile ("isync" : : : "memory"); | |
238 | } | |
57fec1fe | 239 | #elif defined(__i386__) || defined(__x86_64__) |
4390df51 FB |
240 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
241 | { | |
242 | /* patch the branch destination */ | |
243 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); | |
244 | /* no need to flush icache explicitely */ | |
245 | } | |
246 | #endif | |
d4e8164f | 247 | |
5fafdf24 | 248 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
4cbb86e1 FB |
249 | int n, unsigned long addr) |
250 | { | |
251 | unsigned long offset; | |
252 | ||
253 | offset = tb->tb_jmp_offset[n]; | |
254 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
255 | offset = tb->tb_jmp_offset[n + 2]; | |
256 | if (offset != 0xffff) | |
257 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
258 | } | |
259 | ||
d4e8164f FB |
260 | #else |
261 | ||
262 | /* set the jump target */ | |
5fafdf24 | 263 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
d4e8164f FB |
264 | int n, unsigned long addr) |
265 | { | |
95f7652d | 266 | tb->tb_next[n] = addr; |
d4e8164f FB |
267 | } |
268 | ||
269 | #endif | |
270 | ||
5fafdf24 | 271 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
272 | TranslationBlock *tb_next) |
273 | { | |
cf25629d FB |
274 | /* NOTE: this test is only needed for thread safety */ |
275 | if (!tb->jmp_next[n]) { | |
276 | /* patch the native jump address */ | |
277 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); | |
3b46e624 | 278 | |
cf25629d FB |
279 | /* add in TB jmp circular list */ |
280 | tb->jmp_next[n] = tb_next->jmp_first; | |
281 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); | |
282 | } | |
d4e8164f FB |
283 | } |
284 | ||
a513fe19 FB |
285 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
286 | ||
d4e8164f FB |
287 | #ifndef offsetof |
288 | #define offsetof(type, field) ((size_t) &((type *)0)->field) | |
289 | #endif | |
290 | ||
d549f7d9 FB |
291 | #if defined(_WIN32) |
292 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
293 | #define ASM_PREVIOUS_SECTION ".section .text\n" | |
294 | #elif defined(__APPLE__) | |
295 | #define ASM_DATA_SECTION ".data\n" | |
296 | #define ASM_PREVIOUS_SECTION ".text\n" | |
d549f7d9 FB |
297 | #else |
298 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
299 | #define ASM_PREVIOUS_SECTION ".previous\n" | |
d549f7d9 FB |
300 | #endif |
301 | ||
75913b72 FB |
302 | #define ASM_OP_LABEL_NAME(n, opname) \ |
303 | ASM_NAME(__op_label) #n "." ASM_NAME(opname) | |
304 | ||
33417e70 FB |
305 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
306 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 307 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
33417e70 | 308 | |
15a51156 AJ |
309 | #if defined(__hppa__) |
310 | ||
311 | typedef int spinlock_t[4]; | |
312 | ||
313 | #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 } | |
314 | ||
315 | static inline void resetlock (spinlock_t *p) | |
316 | { | |
317 | (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1; | |
318 | } | |
319 | ||
320 | #else | |
321 | ||
322 | typedef int spinlock_t; | |
323 | ||
324 | #define SPIN_LOCK_UNLOCKED 0 | |
325 | ||
326 | static inline void resetlock (spinlock_t *p) | |
327 | { | |
328 | *p = SPIN_LOCK_UNLOCKED; | |
329 | } | |
330 | ||
331 | #endif | |
332 | ||
204a1b8d | 333 | #if defined(__powerpc__) |
d4e8164f FB |
334 | static inline int testandset (int *p) |
335 | { | |
336 | int ret; | |
337 | __asm__ __volatile__ ( | |
02e1ec9b FB |
338 | "0: lwarx %0,0,%1\n" |
339 | " xor. %0,%3,%0\n" | |
340 | " bne 1f\n" | |
341 | " stwcx. %2,0,%1\n" | |
342 | " bne- 0b\n" | |
d4e8164f FB |
343 | "1: " |
344 | : "=&r" (ret) | |
345 | : "r" (p), "r" (1), "r" (0) | |
346 | : "cr0", "memory"); | |
347 | return ret; | |
348 | } | |
204a1b8d | 349 | #elif defined(__i386__) |
d4e8164f FB |
350 | static inline int testandset (int *p) |
351 | { | |
4955a2cd | 352 | long int readval = 0; |
3b46e624 | 353 | |
4955a2cd FB |
354 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
355 | : "+m" (*p), "+a" (readval) | |
356 | : "r" (1) | |
357 | : "cc"); | |
358 | return readval; | |
d4e8164f | 359 | } |
204a1b8d | 360 | #elif defined(__x86_64__) |
bc51c5c9 FB |
361 | static inline int testandset (int *p) |
362 | { | |
4955a2cd | 363 | long int readval = 0; |
3b46e624 | 364 | |
4955a2cd FB |
365 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
366 | : "+m" (*p), "+a" (readval) | |
367 | : "r" (1) | |
368 | : "cc"); | |
369 | return readval; | |
bc51c5c9 | 370 | } |
204a1b8d | 371 | #elif defined(__s390__) |
d4e8164f FB |
372 | static inline int testandset (int *p) |
373 | { | |
374 | int ret; | |
375 | ||
376 | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n" | |
377 | " jl 0b" | |
378 | : "=&d" (ret) | |
5fafdf24 | 379 | : "r" (1), "a" (p), "0" (*p) |
d4e8164f FB |
380 | : "cc", "memory" ); |
381 | return ret; | |
382 | } | |
204a1b8d | 383 | #elif defined(__alpha__) |
2f87c607 | 384 | static inline int testandset (int *p) |
d4e8164f FB |
385 | { |
386 | int ret; | |
387 | unsigned long one; | |
388 | ||
389 | __asm__ __volatile__ ("0: mov 1,%2\n" | |
390 | " ldl_l %0,%1\n" | |
391 | " stl_c %2,%1\n" | |
392 | " beq %2,1f\n" | |
393 | ".subsection 2\n" | |
394 | "1: br 0b\n" | |
395 | ".previous" | |
396 | : "=r" (ret), "=m" (*p), "=r" (one) | |
397 | : "m" (*p)); | |
398 | return ret; | |
399 | } | |
204a1b8d | 400 | #elif defined(__sparc__) |
d4e8164f FB |
401 | static inline int testandset (int *p) |
402 | { | |
403 | int ret; | |
404 | ||
405 | __asm__ __volatile__("ldstub [%1], %0" | |
406 | : "=r" (ret) | |
407 | : "r" (p) | |
408 | : "memory"); | |
409 | ||
410 | return (ret ? 1 : 0); | |
411 | } | |
204a1b8d | 412 | #elif defined(__arm__) |
a95c6790 FB |
413 | static inline int testandset (int *spinlock) |
414 | { | |
415 | register unsigned int ret; | |
416 | __asm__ __volatile__("swp %0, %1, [%2]" | |
417 | : "=r"(ret) | |
418 | : "0"(1), "r"(spinlock)); | |
3b46e624 | 419 | |
a95c6790 FB |
420 | return ret; |
421 | } | |
204a1b8d | 422 | #elif defined(__mc68000) |
38e584a0 FB |
423 | static inline int testandset (int *p) |
424 | { | |
425 | char ret; | |
426 | __asm__ __volatile__("tas %1; sne %0" | |
427 | : "=r" (ret) | |
428 | : "m" (p) | |
429 | : "cc","memory"); | |
4955a2cd | 430 | return ret; |
38e584a0 | 431 | } |
15a51156 AJ |
432 | #elif defined(__hppa__) |
433 | ||
434 | /* Because malloc only guarantees 8-byte alignment for malloc'd data, | |
435 | and GCC only guarantees 8-byte alignment for stack locals, we can't | |
436 | be assured of 16-byte alignment for atomic lock data even if we | |
437 | specify "__attribute ((aligned(16)))" in the type declaration. So, | |
438 | we use a struct containing an array of four ints for the atomic lock | |
439 | type and dynamically select the 16-byte aligned int from the array | |
440 | for the semaphore. */ | |
441 | #define __PA_LDCW_ALIGNMENT 16 | |
442 | static inline void *ldcw_align (void *p) { | |
443 | unsigned long a = (unsigned long)p; | |
444 | a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); | |
445 | return (void *)a; | |
446 | } | |
447 | ||
448 | static inline int testandset (spinlock_t *p) | |
449 | { | |
450 | unsigned int ret; | |
451 | p = ldcw_align(p); | |
452 | __asm__ __volatile__("ldcw 0(%1),%0" | |
453 | : "=r" (ret) | |
454 | : "r" (p) | |
455 | : "memory" ); | |
456 | return !ret; | |
457 | } | |
458 | ||
204a1b8d | 459 | #elif defined(__ia64) |
38e584a0 | 460 | |
b8076a74 FB |
461 | #include <ia64intrin.h> |
462 | ||
463 | static inline int testandset (int *p) | |
464 | { | |
465 | return __sync_lock_test_and_set (p, 1); | |
466 | } | |
204a1b8d | 467 | #elif defined(__mips__) |
c4b89d18 TS |
468 | static inline int testandset (int *p) |
469 | { | |
470 | int ret; | |
471 | ||
472 | __asm__ __volatile__ ( | |
473 | " .set push \n" | |
474 | " .set noat \n" | |
475 | " .set mips2 \n" | |
476 | "1: li $1, 1 \n" | |
477 | " ll %0, %1 \n" | |
478 | " sc $1, %1 \n" | |
976a0d0d | 479 | " beqz $1, 1b \n" |
c4b89d18 TS |
480 | " .set pop " |
481 | : "=r" (ret), "+R" (*p) | |
482 | : | |
483 | : "memory"); | |
484 | ||
485 | return ret; | |
486 | } | |
204a1b8d TS |
487 | #else |
488 | #error unimplemented CPU support | |
c4b89d18 TS |
489 | #endif |
490 | ||
aebcb60e | 491 | #if defined(CONFIG_USER_ONLY) |
d4e8164f FB |
492 | static inline void spin_lock(spinlock_t *lock) |
493 | { | |
494 | while (testandset(lock)); | |
495 | } | |
496 | ||
497 | static inline void spin_unlock(spinlock_t *lock) | |
498 | { | |
15a51156 | 499 | resetlock(lock); |
d4e8164f FB |
500 | } |
501 | ||
502 | static inline int spin_trylock(spinlock_t *lock) | |
503 | { | |
504 | return !testandset(lock); | |
505 | } | |
3c1cf9fa FB |
506 | #else |
507 | static inline void spin_lock(spinlock_t *lock) | |
508 | { | |
509 | } | |
510 | ||
511 | static inline void spin_unlock(spinlock_t *lock) | |
512 | { | |
513 | } | |
514 | ||
515 | static inline int spin_trylock(spinlock_t *lock) | |
516 | { | |
517 | return 1; | |
518 | } | |
519 | #endif | |
d4e8164f FB |
520 | |
521 | extern spinlock_t tb_lock; | |
522 | ||
36bdbe54 | 523 | extern int tb_invalidated_flag; |
6e59c1db | 524 | |
e95c8d51 | 525 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 526 | |
6ebbf390 | 527 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
6e59c1db FB |
528 | void *retaddr); |
529 | ||
6ebbf390 | 530 | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
6e59c1db FB |
531 | #define MEMSUFFIX _code |
532 | #define env cpu_single_env | |
533 | ||
534 | #define DATA_SIZE 1 | |
535 | #include "softmmu_header.h" | |
536 | ||
537 | #define DATA_SIZE 2 | |
538 | #include "softmmu_header.h" | |
539 | ||
540 | #define DATA_SIZE 4 | |
541 | #include "softmmu_header.h" | |
542 | ||
c27004ec FB |
543 | #define DATA_SIZE 8 |
544 | #include "softmmu_header.h" | |
545 | ||
6e59c1db FB |
546 | #undef ACCESS_TYPE |
547 | #undef MEMSUFFIX | |
548 | #undef env | |
549 | ||
550 | #endif | |
4390df51 FB |
551 | |
552 | #if defined(CONFIG_USER_ONLY) | |
553 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) | |
554 | { | |
555 | return addr; | |
556 | } | |
557 | #else | |
558 | /* NOTE: this function can trigger an exception */ | |
1ccde1cb FB |
559 | /* NOTE2: the returned address is not exactly the physical address: it |
560 | is the offset relative to phys_ram_base */ | |
4390df51 FB |
561 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
562 | { | |
6ebbf390 | 563 | int mmu_idx, index, pd; |
4390df51 FB |
564 | |
565 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
6ebbf390 JM |
566 | mmu_idx = cpu_mmu_index(env); |
567 | if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code != | |
4390df51 | 568 | (addr & TARGET_PAGE_MASK), 0)) { |
c27004ec FB |
569 | ldub_code(addr); |
570 | } | |
6ebbf390 | 571 | pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; |
2a4188a3 | 572 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
647de6ca | 573 | #if defined(TARGET_SPARC) || defined(TARGET_MIPS) |
6c36d3fa BS |
574 | do_unassigned_access(addr, 0, 1, 0); |
575 | #else | |
36d23958 | 576 | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
6c36d3fa | 577 | #endif |
4390df51 | 578 | } |
6ebbf390 | 579 | return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base; |
4390df51 FB |
580 | } |
581 | #endif | |
9df217a3 | 582 | |
9df217a3 | 583 | #ifdef USE_KQEMU |
f32fc648 FB |
584 | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
585 | ||
9df217a3 FB |
586 | int kqemu_init(CPUState *env); |
587 | int kqemu_cpu_exec(CPUState *env); | |
588 | void kqemu_flush_page(CPUState *env, target_ulong addr); | |
589 | void kqemu_flush(CPUState *env, int global); | |
4b7df22f | 590 | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr); |
f32fc648 | 591 | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr); |
a332e112 | 592 | void kqemu_cpu_interrupt(CPUState *env); |
f32fc648 | 593 | void kqemu_record_dump(void); |
9df217a3 FB |
594 | |
595 | static inline int kqemu_is_ok(CPUState *env) | |
596 | { | |
597 | return(env->kqemu_enabled && | |
5fafdf24 | 598 | (env->cr[0] & CR0_PE_MASK) && |
f32fc648 | 599 | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
9df217a3 | 600 | (env->eflags & IF_MASK) && |
f32fc648 | 601 | !(env->eflags & VM_MASK) && |
5fafdf24 | 602 | (env->kqemu_enabled == 2 || |
f32fc648 FB |
603 | ((env->hflags & HF_CPL_MASK) == 3 && |
604 | (env->eflags & IOPL_MASK) != IOPL_MASK))); | |
9df217a3 FB |
605 | } |
606 | ||
607 | #endif |