[mirror_qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if GCC_MAJOR < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
                    
#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb, 
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page(CPUState *env, target_ulong vaddr, 
                 target_phys_addr_t paddr, int prot, 
                 int is_user, int is_softmmu);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) 
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching tb for virtual address */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next; 
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2]; 
    target_ulong page_addr[2]; 

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_HASH_SIZE - 1);
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(unsigned long pc);
void tb_flush(CPUState *env);
void tb_link(TranslationBlock *tb);
void tb_link_phys(TranslationBlock *tb, 
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        target_ulong pc, 
                                        target_ulong cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = tb_hash_func(pc);
    ptb = &tb_hash[h];
    for(;;) {
        tb = *ptb;
        if (!tb)
            break;
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
        ptb = &tb->hash_next;
    }
    *pptb = ptb;
    return NULL;
}


#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (".section \".data\"\n"\
		  "__op_label" #n "." stringify(opname) ":\n"\
		  ".long 1f\n"\
		  ".previous\n"\
                  "b __op_jmp" #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("b __op_jmp" #n "\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

#ifdef _WIN32
#define ASM_PREVIOUS_SECTION ".section .text\n"
#else
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

/* we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (".section .data\n"\
		  "__op_label" #n "." stringify(opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp __op_jmp" #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("jmp __op_jmp" #n "\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n:\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
dummy_label ## n:\
    EXIT_TB();\
} while (0)

/* second jump to same destination 'n' */
#define JUMP_TB2(opname, tbparam, n)\
do {\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
} while (0)

#endif

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1 ;"
                          "      xor. %0,%3,%0;"
                          "      bne 1f;"
                          "      stwcx. %2,0,%1;"
                          "      bne- 0b;"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    char ret;
    long int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __x86_64__
static inline int testandset (int *p)
{
    char ret;
    int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret == 0;
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if (defined(TARGET_I386) || defined(TARGET_PPC)) && \
    !defined(CONFIG_USER_ONLY)

void tlb_fill(unsigned long addr, int is_write, int is_user, 
              void *retaddr);

#define ACCESS_TYPE 3
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
/* XXX: i386 target specific */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int is_user, index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
#if defined(TARGET_I386)
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
#elif defined (TARGET_PPC)
    is_user = msr_pr;
#else
#error "Unimplemented !"
#endif
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & TARGET_PAGE_MASK), 0)) {
#if defined (TARGET_PPC)
	env->access_type = ACCESS_CODE;
	ldub_code((void *)addr);
	env->access_type = ACCESS_INT;
#else
        ldub_code((void *)addr);
#endif
    }
    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
	31	#if GCC_MAJOR < 3
	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
	58	extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
66e85a21	59	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46 FB	60	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
b346ff46 FB	61
9886cc16 FB	62	typedef void (GenOpFunc)(void);
	63	typedef void (GenOpFunc1)(long);
	64	typedef void (GenOpFunc2)(long, long);
	65	typedef void (GenOpFunc3)(long, long, long);
	66
b346ff46 FB	67	#if defined(TARGET_I386)
b346ff46 FB	68
33417e70	69	void optimize_flags_init(void);
d4e8164f	70
b346ff46 FB	71	#endif
	72
	73	extern FILE *logfile;
	74	extern int loglevel;
	75
4c3a88a2 FB	76	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	77	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	78	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	79	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	80	int max_code_size, int *gen_code_size_ptr);
66e85a21	81	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	82	CPUState *env, unsigned long searched_pc,
	83	void *puc);
	84	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	85	int max_code_size, int *gen_code_size_ptr);
	86	int cpu_restore_state_copy(struct TranslationBlock *tb,
	87	CPUState *env, unsigned long searched_pc,
	88	void *puc);
2e12669a	89	void cpu_resume_from_signal(CPUState env1, void puc);
b346ff46	90	void cpu_exec_init(void);
2e12669a FB	91	int page_unprotect(unsigned long address, unsigned long pc, void *puc);
	92	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
	93	int is_cpu_write_access);
4390df51	94	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	95	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	96	void tlb_flush(CPUState *env, int flush_global);
2e12669a FB	97	int tlb_set_page(CPUState *env, target_ulong vaddr,
2e12669a FB	98	target_phys_addr_t paddr, int prot,
4390df51	99	int is_user, int is_softmmu);
d4e8164f FB	100
	101	#define CODE_GEN_MAX_SIZE 65536
	102	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	103
	104	#define CODE_GEN_HASH_BITS 15
	105	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
	106
4390df51 FB	107	#define CODE_GEN_PHYS_HASH_BITS 15
	108	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	109
d4e8164f	110	/* maximum total translate dcode allocated */
4390df51 FB	111
4390df51 FB	112	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	113	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	114	summary of the ranges:
	115
	116	i386 : signed 32 bits
	117	arm : signed 26 bits
	118	ppc : signed 24 bits
	119	sparc : signed 32 bits
	120	alpha : signed 23 bits
	121	*/
	122
	123	#if defined(__alpha__)
	124	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
	125	#elif defined(__powerpc__)
c4c7e3e6	126	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51 FB	127	#else
	128	#define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
	129	#endif
	130
d4e8164f FB	131	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	132
4390df51 FB	133	/* estimated block size for TB allocation */
	134	/* XXX: use a per code average code fragment size and modulate it
	135	according to the host CPU */
	136	#if defined(CONFIG_SOFTMMU)
	137	#define CODE_GEN_AVG_BLOCK_SIZE 128
	138	#else
	139	#define CODE_GEN_AVG_BLOCK_SIZE 64
	140	#endif
	141
	142	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	143
	144	#if defined(__powerpc__)
	145	#define USE_DIRECT_JUMP
	146	#endif
67b915a5	147	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	148	#define USE_DIRECT_JUMP
	149	#endif
	150
	151	typedef struct TranslationBlock {
2e12669a FB	152	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	153	target_ulong cs_base; /* CS base for this block */
d4e8164f FB	154	unsigned int flags; /* flags defining in which context the code was generated */
	155	uint16_t size; /* size of target code for this block (1 <=
	156	size <= TARGET_PAGE_SIZE) */
58fe2f10	157	uint16_t cflags; /* compile flags */
bf088061 FB	158	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	159	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	160	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	161	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	162
d4e8164f	163	uint8_t tc_ptr; / pointer to the translated code */
4390df51 FB	164	struct TranslationBlock hash_next; / next matching tb for virtual address */
	165	/* next matching tb for physical address. */
	166	struct TranslationBlock *phys_hash_next;
	167	/* first and second physical page containing code. The lower bit
	168	of the pointer tells the index in page_next[] */
	169	struct TranslationBlock *page_next[2];
	170	target_ulong page_addr[2];
	171
d4e8164f FB	172	/* the following data are used to directly call another TB from
	173	the code of this one. */
	174	uint16_t tb_next_offset[2]; /* offset of original jump target */
	175	#ifdef USE_DIRECT_JUMP
4cbb86e1	176	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	177	#else
95f7652d	178	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	179	#endif
	180	/* list of TBs jumping to this one. This is a circular list using
	181	the two least significant bits of the pointers to tell what is
	182	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	183	jmp_first */
	184	struct TranslationBlock *jmp_next[2];
	185	struct TranslationBlock *jmp_first;
	186	} TranslationBlock;
	187
	188	static inline unsigned int tb_hash_func(unsigned long pc)
	189	{
	190	return pc & (CODE_GEN_HASH_SIZE - 1);
	191	}
	192
4390df51 FB	193	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	194	{
	195	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	196	}
	197
d4e8164f	198	TranslationBlock *tb_alloc(unsigned long pc);
0124311e	199	void tb_flush(CPUState *env);
d4e8164f	200	void tb_link(TranslationBlock *tb);
4390df51 FB	201	void tb_link_phys(TranslationBlock *tb,
4390df51 FB	202	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f FB	203
d4e8164f FB	204	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
4390df51	205	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	206
	207	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	208	extern uint8_t *code_gen_ptr;
	209
	210	/* find a translation block in the translation cache. If not found,
	211	return NULL and the pointer to the last element of the list in pptb */
	212	static inline TranslationBlock tb_find(TranslationBlock **pptb,
2e12669a FB	213	target_ulong pc,
2e12669a FB	214	target_ulong cs_base,
d4e8164f FB	215	unsigned int flags)
	216	{
	217	TranslationBlock *ptb, tb;
	218	unsigned int h;
	219
	220	h = tb_hash_func(pc);
	221	ptb = &tb_hash[h];
	222	for(;;) {
	223	tb = *ptb;
	224	if (!tb)
	225	break;
	226	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
	227	return tb;
	228	ptb = &tb->hash_next;
	229	}
	230	*pptb = ptb;
	231	return NULL;
	232	}
	233
d4e8164f	234
4390df51 FB	235	#if defined(USE_DIRECT_JUMP)
	236
	237	#if defined(__powerpc__)
4cbb86e1	238	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	239	{
d4e8164f FB	240	uint32_t val, *ptr;
d4e8164f FB	241
d4e8164f FB	242	/* patch the branch destination */
4cbb86e1	243	ptr = (uint32_t *)jmp_addr;
d4e8164f	244	val = *ptr;
4cbb86e1	245	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	246	*ptr = val;
	247	/* flush icache */
	248	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	249	asm volatile ("sync" : : : "memory");
	250	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	251	asm volatile ("sync" : : : "memory");
	252	asm volatile ("isync" : : : "memory");
	253	}
4390df51 FB	254	#elif defined(__i386__)
	255	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	256	{
	257	/* patch the branch destination */
	258	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	259	/* no need to flush icache explicitely */
	260	}
	261	#endif
d4e8164f	262
4cbb86e1 FB	263	static inline void tb_set_jmp_target(TranslationBlock *tb,
	264	int n, unsigned long addr)
	265	{
	266	unsigned long offset;
	267
	268	offset = tb->tb_jmp_offset[n];
	269	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	270	offset = tb->tb_jmp_offset[n + 2];
	271	if (offset != 0xffff)
	272	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	273	}
	274
d4e8164f FB	275	#else
	276
	277	/* set the jump target */
	278	static inline void tb_set_jmp_target(TranslationBlock *tb,
	279	int n, unsigned long addr)
	280	{
95f7652d	281	tb->tb_next[n] = addr;
d4e8164f FB	282	}
	283
	284	#endif
	285
	286	static inline void tb_add_jump(TranslationBlock *tb, int n,
	287	TranslationBlock *tb_next)
	288	{
cf25629d FB	289	/* NOTE: this test is only needed for thread safety */
	290	if (!tb->jmp_next[n]) {
	291	/* patch the native jump address */
	292	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	293
	294	/* add in TB jmp circular list */
	295	tb->jmp_next[n] = tb_next->jmp_first;
	296	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	297	}
d4e8164f FB	298	}
d4e8164f FB	299
a513fe19 FB	300	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	301
d4e8164f FB	302	#ifndef offsetof
	303	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	304	#endif
	305
b346ff46 FB	306	#if defined(__powerpc__)
b346ff46 FB	307
4390df51	308	/* we patch the jump instruction directly */
9257a9e4	309	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46	310	do {\
9257a9e4 FB	311	asm volatile (".section \".data\"\n"\
	312	"__op_label" #n "." stringify(opname) ":\n"\
	313	".long 1f\n"\
	314	".previous\n"\
	315	"b __op_jmp" #n "\n"\
	316	"1:\n");\
b346ff46 FB	317	T0 = (long)(tbparam) + (n);\
b346ff46 FB	318	EIP = eip;\
31e8f3c8	319	EXIT_TB();\
b346ff46 FB	320	} while (0)
b346ff46 FB	321
4cbb86e1 FB	322	#define JUMP_TB2(opname, tbparam, n)\
4cbb86e1 FB	323	do {\
4390df51 FB	324	asm volatile ("b __op_jmp" #n "\n");\
	325	} while (0)
	326
	327	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	328
67b915a5 FB	329	#ifdef _WIN32
	330	#define ASM_PREVIOUS_SECTION ".section .text\n"
	331	#else
	332	#define ASM_PREVIOUS_SECTION ".previous\n"
	333	#endif
	334
4390df51 FB	335	/* we patch the jump instruction directly */
	336	#define JUMP_TB(opname, tbparam, n, eip)\
	337	do {\
67b915a5	338	asm volatile (".section .data\n"\
4390df51 FB	339	"__op_label" #n "." stringify(opname) ":\n"\
4390df51 FB	340	".long 1f\n"\
67b915a5	341	ASM_PREVIOUS_SECTION \
4390df51 FB	342	"jmp __op_jmp" #n "\n"\
	343	"1:\n");\
	344	T0 = (long)(tbparam) + (n);\
	345	EIP = eip;\
	346	EXIT_TB();\
	347	} while (0)
	348
	349	#define JUMP_TB2(opname, tbparam, n)\
	350	do {\
	351	asm volatile ("jmp __op_jmp" #n "\n");\
4cbb86e1 FB	352	} while (0)
4cbb86e1 FB	353
b346ff46 FB	354	#else
	355
	356	/* jump to next block operations (more portable code, does not need
	357	cache flushing, but slower because of indirect jump) */
9257a9e4	358	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46 FB	359	do {\
b346ff46 FB	360	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
2f62b397	361	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
b346ff46 FB	362	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
	363	label ## n:\
	364	T0 = (long)(tbparam) + (n);\
	365	EIP = eip;\
2f62b397	366	dummy_label ## n:\
9621339d	367	EXIT_TB();\
b346ff46 FB	368	} while (0)
b346ff46 FB	369
4cbb86e1 FB	370	/* second jump to same destination 'n' */
	371	#define JUMP_TB2(opname, tbparam, n)\
	372	do {\
4390df51	373	goto (void )(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
4cbb86e1 FB	374	} while (0)
4cbb86e1 FB	375
b346ff46 FB	376	#endif
b346ff46 FB	377
33417e70 FB	378	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	379	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	380	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	381
d4e8164f FB	382	#ifdef __powerpc__
	383	static inline int testandset (int *p)
	384	{
	385	int ret;
	386	__asm__ __volatile__ (
	387	"0: lwarx %0,0,%1 ;"
	388	" xor. %0,%3,%0;"
	389	" bne 1f;"
	390	" stwcx. %2,0,%1;"
	391	" bne- 0b;"
	392	"1: "
	393	: "=&r" (ret)
	394	: "r" (p), "r" (1), "r" (0)
	395	: "cr0", "memory");
	396	return ret;
	397	}
	398	#endif
	399
	400	#ifdef __i386__
	401	static inline int testandset (int *p)
	402	{
	403	char ret;
	404	long int readval;
	405
	406	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	407	: "=q" (ret), "=m" (*p), "=a" (readval)
	408	: "r" (1), "m" (*p), "a" (0)
	409	: "memory");
	410	return ret;
	411	}
	412	#endif
	413
bc51c5c9 FB	414	#ifdef __x86_64__
	415	static inline int testandset (int *p)
	416	{
	417	char ret;
	418	int readval;
	419
	420	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	421	: "=q" (ret), "=m" (*p), "=a" (readval)
	422	: "r" (1), "m" (*p), "a" (0)
	423	: "memory");
	424	return ret;
	425	}
	426	#endif
	427
d4e8164f FB	428	#ifdef __s390__
	429	static inline int testandset (int *p)
	430	{
	431	int ret;
	432
	433	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	434	" jl 0b"
	435	: "=&d" (ret)
	436	: "r" (1), "a" (p), "0" (*p)
	437	: "cc", "memory" );
	438	return ret;
	439	}
	440	#endif
	441
	442	#ifdef __alpha__
2f87c607	443	static inline int testandset (int *p)
d4e8164f FB	444	{
	445	int ret;
	446	unsigned long one;
	447
	448	__asm__ __volatile__ ("0: mov 1,%2\n"
	449	" ldl_l %0,%1\n"
	450	" stl_c %2,%1\n"
	451	" beq %2,1f\n"
	452	".subsection 2\n"
	453	"1: br 0b\n"
	454	".previous"
	455	: "=r" (ret), "=m" (*p), "=r" (one)
	456	: "m" (*p));
	457	return ret;
	458	}
	459	#endif
	460
	461	#ifdef __sparc__
	462	static inline int testandset (int *p)
	463	{
	464	int ret;
	465
	466	__asm__ __volatile__("ldstub [%1], %0"
	467	: "=r" (ret)
	468	: "r" (p)
	469	: "memory");
	470
	471	return (ret ? 1 : 0);
	472	}
	473	#endif
	474
a95c6790 FB	475	#ifdef __arm__
	476	static inline int testandset (int *spinlock)
	477	{
	478	register unsigned int ret;
	479	__asm__ __volatile__("swp %0, %1, [%2]"
	480	: "=r"(ret)
	481	: "0"(1), "r"(spinlock));
	482
	483	return ret;
	484	}
	485	#endif
	486
38e584a0 FB	487	#ifdef __mc68000
	488	static inline int testandset (int *p)
	489	{
	490	char ret;
	491	__asm__ __volatile__("tas %1; sne %0"
	492	: "=r" (ret)
	493	: "m" (p)
	494	: "cc","memory");
	495	return ret == 0;
	496	}
	497	#endif
	498
d4e8164f FB	499	typedef int spinlock_t;
	500
	501	#define SPIN_LOCK_UNLOCKED 0
	502
aebcb60e	503	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	504	static inline void spin_lock(spinlock_t *lock)
	505	{
	506	while (testandset(lock));
	507	}
	508
	509	static inline void spin_unlock(spinlock_t *lock)
	510	{
	511	*lock = 0;
	512	}
	513
	514	static inline int spin_trylock(spinlock_t *lock)
	515	{
	516	return !testandset(lock);
	517	}
3c1cf9fa FB	518	#else
	519	static inline void spin_lock(spinlock_t *lock)
	520	{
	521	}
	522
	523	static inline void spin_unlock(spinlock_t *lock)
	524	{
	525	}
	526
	527	static inline int spin_trylock(spinlock_t *lock)
	528	{
	529	return 1;
	530	}
	531	#endif
d4e8164f FB	532
	533	extern spinlock_t tb_lock;
	534
36bdbe54	535	extern int tb_invalidated_flag;
6e59c1db	536
9886cc16 FB	537	#if (defined(TARGET_I386) \|\| defined(TARGET_PPC)) && \
9886cc16 FB	538	!defined(CONFIG_USER_ONLY)
6e59c1db FB	539
	540	void tlb_fill(unsigned long addr, int is_write, int is_user,
	541	void *retaddr);
	542
	543	#define ACCESS_TYPE 3
	544	#define MEMSUFFIX _code
	545	#define env cpu_single_env
	546
	547	#define DATA_SIZE 1
	548	#include "softmmu_header.h"
	549
	550	#define DATA_SIZE 2
	551	#include "softmmu_header.h"
	552
	553	#define DATA_SIZE 4
	554	#include "softmmu_header.h"
	555
	556	#undef ACCESS_TYPE
	557	#undef MEMSUFFIX
	558	#undef env
	559
	560	#endif
4390df51 FB	561
	562	#if defined(CONFIG_USER_ONLY)
	563	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	564	{
	565	return addr;
	566	}
	567	#else
	568	/* NOTE: this function can trigger an exception */
1ccde1cb FB	569	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	570	is the offset relative to phys_ram_base */
4390df51 FB	571	/* XXX: i386 target specific */
	572	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	573	{
	574	int is_user, index;
	575
	576	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
3f5dcc34	577	#if defined(TARGET_I386)
4390df51	578	is_user = ((env->hflags & HF_CPL_MASK) == 3);
3f5dcc34 FB	579	#elif defined (TARGET_PPC)
	580	is_user = msr_pr;
	581	#else
	582	#error "Unimplemented !"
	583	#endif
4390df51 FB	584	if (__builtin_expect(env->tlb_read[is_user][index].address !=
4390df51 FB	585	(addr & TARGET_PAGE_MASK), 0)) {
a541f297 FB	586	#if defined (TARGET_PPC)
	587	env->access_type = ACCESS_CODE;
	588	ldub_code((void *)addr);
	589	env->access_type = ACCESS_INT;
	590	#else
4390df51	591	ldub_code((void *)addr);
a541f297	592	#endif
4390df51 FB	593	}
	594	return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
	595	}
	596	#endif