[mirror_qemu.git] / exec-i386.c

/*
 *  i386 emulator main execution loop
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "exec-i386.h"
#include "disas.h"

//#define DEBUG_EXEC
#define DEBUG_FLUSH
//#define DEBUG_SIGNAL

/* main execution loop */

/* maximum total translate dcode allocated */
#define CODE_GEN_BUFFER_SIZE     (2048 * 1024)
//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

/* threshold to flush the translated code buffer */
#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / 64)
#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

typedef struct TranslationBlock {
    unsigned long pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    unsigned long cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching block */
} TranslationBlock;

TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
int nb_tbs;

uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
uint8_t *code_gen_ptr;

/* thread support */

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1 ;"
                          "      xor. %0,%3,%0;"
                          "      bne 1f;"
                          "      stwcx. %2,0,%1;"
                          "      bne- 0b;"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    char ret;
    long int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

int global_cpu_lock = 0;

void cpu_lock(void)
{
    while (testandset(&global_cpu_lock));
}

void cpu_unlock(void)
{
    global_cpu_lock = 0;
}

/* exception support */
/* NOTE: not static to force relocation generation by GCC */
void raise_exception_err(int exception_index, int error_code)
{
    /* NOTE: the register at this point must be saved by hand because
       longjmp restore them */
#ifdef __sparc__
	/* We have to stay in the same register window as our caller,
	 * thus this trick.
	 */
	__asm__ __volatile__("restore\n\t"
			     "mov\t%o0, %i0");
#endif
#ifdef reg_EAX
    env->regs[R_EAX] = EAX;
#endif
#ifdef reg_ECX
    env->regs[R_ECX] = ECX;
#endif
#ifdef reg_EDX
    env->regs[R_EDX] = EDX;
#endif
#ifdef reg_EBX
    env->regs[R_EBX] = EBX;
#endif
#ifdef reg_ESP
    env->regs[R_ESP] = ESP;
#endif
#ifdef reg_EBP
    env->regs[R_EBP] = EBP;
#endif
#ifdef reg_ESI
    env->regs[R_ESI] = ESI;
#endif
#ifdef reg_EDI
    env->regs[R_EDI] = EDI;
#endif
    env->exception_index = exception_index;
    env->error_code = error_code;
    longjmp(env->jmp_env, 1);
}

/* short cut if error_code is 0 or not present */
void raise_exception(int exception_index)
{
    raise_exception_err(exception_index, 0);
}

void cpu_x86_tblocks_init(void)
{
    if (!code_gen_ptr) {
        code_gen_ptr = code_gen_buffer;
    }
}

/* flush all the translation blocks */
static void tb_flush(void)
{
    int i;
#ifdef DEBUG_FLUSH
    printf("gemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d\n", 
           code_gen_ptr - code_gen_buffer, 
           nb_tbs, 
           (code_gen_ptr - code_gen_buffer) / nb_tbs);
#endif
    nb_tbs = 0;
    for(i = 0;i < CODE_GEN_HASH_SIZE; i++)
        tb_hash[i] = NULL;
    code_gen_ptr = code_gen_buffer;
    /* XXX: flush processor icache at this point */
}

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        unsigned long pc, 
                                        unsigned long cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = pc & (CODE_GEN_HASH_SIZE - 1);
    ptb = &tb_hash[h];
#if 0
    /* XXX: hack to handle 16 bit modyfing code */
    if (flags & (1 << GEN_FLAG_CODE32_SHIFT))
#endif
        for(;;) {
            tb = *ptb;
            if (!tb)
                break;
            if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
            ptb = &tb->hash_next;
        }
    *pptb = ptb;
    return NULL;
}

/* allocate a new translation block. flush the translation buffer if
   too many translation blocks or too much generated code */
static inline TranslationBlock *tb_alloc(void)
{
    TranslationBlock *tb;
    if (nb_tbs >= CODE_GEN_MAX_BLOCKS || 
        (code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE)
        tb_flush();
    tb = &tbs[nb_tbs++];
    return tb;
}

int cpu_x86_exec(CPUX86State *env1)
{
    int saved_T0, saved_T1, saved_A0;
    CPUX86State *saved_env;
#ifdef reg_EAX
    int saved_EAX;
#endif
#ifdef reg_ECX
    int saved_ECX;
#endif
#ifdef reg_EDX
    int saved_EDX;
#endif
#ifdef reg_EBX
    int saved_EBX;
#endif
#ifdef reg_ESP
    int saved_ESP;
#endif
#ifdef reg_EBP
    int saved_EBP;
#endif
#ifdef reg_ESI
    int saved_ESI;
#endif
#ifdef reg_EDI
    int saved_EDI;
#endif
    int code_gen_size, ret;
    void (*gen_func)(void);
    TranslationBlock *tb, **ptb;
    uint8_t *tc_ptr, *cs_base, *pc;
    unsigned int flags;

    /* first we save global registers */
    saved_T0 = T0;
    saved_T1 = T1;
    saved_A0 = A0;
    saved_env = env;
    env = env1;
#ifdef reg_EAX
    saved_EAX = EAX;
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    saved_ECX = ECX;
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    saved_EDX = EDX;
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    saved_EBX = EBX;
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    saved_ESP = ESP;
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    saved_EBP = EBP;
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    saved_ESI = ESI;
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    saved_EDI = EDI;
    EDI = env->regs[R_EDI];
#endif
    
    /* put eflags in CPU temporary format */
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
    CC_OP = CC_OP_EFLAGS;
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    env->interrupt_request = 0;

    /* prepare setjmp context for exception handling */
    if (setjmp(env->jmp_env) == 0) {
        for(;;) {
            if (env->interrupt_request) {
                raise_exception(EXCP_INTERRUPT);
            }
#ifdef DEBUG_EXEC
            if (loglevel) {
                /* XXX: save all volatile state in cpu state */
                /* restore flags in standard format */
                env->regs[R_EAX] = EAX;
                env->regs[R_EBX] = EBX;
                env->regs[R_ECX] = ECX;
                env->regs[R_EDX] = EDX;
                env->regs[R_ESI] = ESI;
                env->regs[R_EDI] = EDI;
                env->regs[R_EBP] = EBP;
                env->regs[R_ESP] = ESP;
                env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
                cpu_x86_dump_state(env, logfile, 0);
                env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
            }
#endif
            /* we compute the CPU state. We assume it will not
               change during the whole generated block. */
            flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
            flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
            flags |= (((unsigned long)env->seg_cache[R_DS].base | 
                       (unsigned long)env->seg_cache[R_ES].base |
                       (unsigned long)env->seg_cache[R_SS].base) != 0) << 
                GEN_FLAG_ADDSEG_SHIFT;
            if (!(env->eflags & VM_MASK)) {
                flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
            } else {
                /* NOTE: a dummy CPL is kept */
                flags |= (1 << GEN_FLAG_VM_SHIFT);
                flags |= (3 << GEN_FLAG_CPL_SHIFT);
            }
            flags |= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT);
            flags |= (env->eflags & TF_MASK) << (GEN_FLAG_TF_SHIFT - 8);
            cs_base = env->seg_cache[R_CS].base;
            pc = cs_base + env->eip;
            tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, 
                         flags);
            if (!tb) {
                /* if no translated code available, then translate it now */
                /* XXX: very inefficient: we lock all the cpus when
                   generating code */
                cpu_lock();
                tc_ptr = code_gen_ptr;
                ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE, 
                                       &code_gen_size, pc, cs_base, flags);
                /* if invalid instruction, signal it */
                if (ret != 0) {
                    cpu_unlock();
                    raise_exception(EXCP06_ILLOP);
                }
                tb = tb_alloc();
                *ptb = tb;
                tb->pc = (unsigned long)pc;
                tb->cs_base = (unsigned long)cs_base;
                tb->flags = flags;
                tb->tc_ptr = tc_ptr;
                tb->hash_next = NULL;
                code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
                cpu_unlock();
            }
#ifdef DEBUG_EXEC
	    if (loglevel) {
		fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
			(long)tb->tc_ptr, (long)tb->pc,
			lookup_symbol((void *)tb->pc));
	    }
#endif
            /* execute the generated code */
            tc_ptr = tb->tc_ptr;
            gen_func = (void *)tc_ptr;
#ifdef __sparc__
	    __asm__ __volatile__("call	%0\n\t"
				 " mov	%%o7,%%i0"
				 : /* no outputs */
				 : "r" (gen_func)
				 : "i0", "i1", "i2", "i3", "i4", "i5");
#else
            gen_func();
#endif
        }
    }
    ret = env->exception_index;

    /* restore flags in standard format */
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);

    /* restore global registers */
#ifdef reg_EAX
    EAX = saved_EAX;
#endif
#ifdef reg_ECX
    ECX = saved_ECX;
#endif
#ifdef reg_EDX
    EDX = saved_EDX;
#endif
#ifdef reg_EBX
    EBX = saved_EBX;
#endif
#ifdef reg_ESP
    ESP = saved_ESP;
#endif
#ifdef reg_EBP
    EBP = saved_EBP;
#endif
#ifdef reg_ESI
    ESI = saved_ESI;
#endif
#ifdef reg_EDI
    EDI = saved_EDI;
#endif
    T0 = saved_T0;
    T1 = saved_T1;
    A0 = saved_A0;
    env = saved_env;
    return ret;
}

void cpu_x86_interrupt(CPUX86State *s)
{
    s->interrupt_request = 1;
}


void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    load_seg(seg_reg, selector);
    env = saved_env;
}

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#include <sys/ucontext.h>

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception */
static inline int handle_cpu_signal(unsigned long pc,
                                    unsigned long address,
                                    sigset_t *old_set)
{
#ifdef DEBUG_SIGNAL
    printf("gemu: SIGSEGV pc=0x%08lx oldset=0x%08lx\n", 
           pc, *(unsigned long *)old_set);
#endif
    if (pc >= (unsigned long)code_gen_buffer &&
        pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        /* we restore the process signal mask as the sigreturn should
           do it */
        sigprocmask(SIG_SETMASK, old_set, NULL);
        /* XXX: need to compute virtual pc position by retranslating
           code. The rest of the CPU state should be correct. */
        env->cr2 = address;
        /* XXX: more precise exception code */
        raise_exception_err(EXCP0E_PAGE, 4);
        /* never comes here */
        return 1;
    } else {
        return 0;
    }
}

int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
#if defined(__i386__)
    struct ucontext *uc = puc;
    unsigned long pc;
    sigset_t *pold_set;
    
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP EIP
#endif
    pc = uc->uc_mcontext.gregs[REG_EIP];
    pold_set = &uc->uc_sigmask;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, pold_set);
#else
#warning No CPU specific signal handler: cannot handle target SIGSEGV events
    return 0;
#endif
}
Commit	Line	Data
7d13299d FB	1	/*
	2	* i386 emulator main execution loop
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
3ef693a0 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
7d13299d	10	*
3ef693a0 FB	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
7d13299d	15	*
3ef693a0 FB	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d FB	19	*/
7d13299d FB	20	#include "exec-i386.h"
956034d7	21	#include "disas.h"
7d13299d	22
dc99065b	23	//#define DEBUG_EXEC
7d13299d	24	#define DEBUG_FLUSH
9de5e440	25	//#define DEBUG_SIGNAL
7d13299d FB	26
	27	/* main execution loop */
	28
	29	/* maximum total translate dcode allocated */
	30	#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
	31	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
	32	#define CODE_GEN_MAX_SIZE 65536
	33	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	34
	35	/* threshold to flush the translated code buffer */
	36	#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
	37
	38	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / 64)
	39	#define CODE_GEN_HASH_BITS 15
	40	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
6dbad63e	41
7d13299d	42	typedef struct TranslationBlock {
dab2ed99 FB	43	unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
dab2ed99 FB	44	unsigned long cs_base; /* CS base for this block */
6dbad63e	45	unsigned int flags; /* flags defining in which context the code was generated */
7d13299d FB	46	uint8_t tc_ptr; / pointer to the translated code */
	47	struct TranslationBlock hash_next; / next matching block */
	48	} TranslationBlock;
	49
	50	TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
	51	TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
	52	int nb_tbs;
	53
	54	uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	55	uint8_t *code_gen_ptr;
	56
1b6b029e FB	57	/* thread support */
	58
	59	#ifdef __powerpc__
	60	static inline int testandset (int *p)
	61	{
	62	int ret;
	63	__asm__ __volatile__ (
	64	"0: lwarx %0,0,%1 ;"
	65	" xor. %0,%3,%0;"
	66	" bne 1f;"
	67	" stwcx. %2,0,%1;"
	68	" bne- 0b;"
	69	"1: "
	70	: "=&r" (ret)
	71	: "r" (p), "r" (1), "r" (0)
	72	: "cr0", "memory");
	73	return ret;
	74	}
	75	#endif
	76
	77	#ifdef __i386__
	78	static inline int testandset (int *p)
	79	{
	80	char ret;
	81	long int readval;
	82
	83	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	84	: "=q" (ret), "=m" (*p), "=a" (readval)
	85	: "r" (1), "m" (*p), "a" (0)
	86	: "memory");
	87	return ret;
	88	}
	89	#endif
	90
fb3e5849 FB	91	#ifdef __s390__
	92	static inline int testandset (int *p)
	93	{
	94	int ret;
	95
	96	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	97	" jl 0b"
	98	: "=&d" (ret)
	99	: "r" (1), "a" (p), "0" (*p)
	100	: "cc", "memory" );
	101	return ret;
	102	}
	103	#endif
	104
e026db58 FB	105	#ifdef __alpha__
	106	int testandset (int *p)
	107	{
	108	int ret;
	109	unsigned long one;
	110
	111	__asm__ __volatile__ ("0: mov 1,%2\n"
	112	" ldl_l %0,%1\n"
	113	" stl_c %2,%1\n"
	114	" beq %2,1f\n"
	115	".subsection 2\n"
	116	"1: br 0b\n"
	117	".previous"
	118	: "=r" (ret), "=m" (*p), "=r" (one)
	119	: "m" (*p));
	120	return ret;
	121	}
	122	#endif
	123
d014c98c FB	124	#ifdef __sparc__
	125	static inline int testandset (int *p)
	126	{
	127	int ret;
	128
	129	__asm__ __volatile__("ldstub [%1], %0"
	130	: "=r" (ret)
	131	: "r" (p)
	132	: "memory");
	133
	134	return (ret ? 1 : 0);
	135	}
	136	#endif
	137
1b6b029e FB	138	int global_cpu_lock = 0;
	139
	140	void cpu_lock(void)
	141	{
	142	while (testandset(&global_cpu_lock));
	143	}
	144
	145	void cpu_unlock(void)
	146	{
	147	global_cpu_lock = 0;
	148	}
	149
9de5e440 FB	150	/* exception support */
9de5e440 FB	151	/* NOTE: not static to force relocation generation by GCC */
b56dad1c	152	void raise_exception_err(int exception_index, int error_code)
9de5e440 FB	153	{
	154	/* NOTE: the register at this point must be saved by hand because
	155	longjmp restore them */
ae228531 FB	156	#ifdef __sparc__
	157	/* We have to stay in the same register window as our caller,
	158	* thus this trick.
	159	*/
	160	__asm__ __volatile__("restore\n\t"
	161	"mov\t%o0, %i0");
	162	#endif
9de5e440 FB	163	#ifdef reg_EAX
	164	env->regs[R_EAX] = EAX;
	165	#endif
	166	#ifdef reg_ECX
	167	env->regs[R_ECX] = ECX;
	168	#endif
	169	#ifdef reg_EDX
	170	env->regs[R_EDX] = EDX;
	171	#endif
	172	#ifdef reg_EBX
	173	env->regs[R_EBX] = EBX;
	174	#endif
	175	#ifdef reg_ESP
	176	env->regs[R_ESP] = ESP;
	177	#endif
	178	#ifdef reg_EBP
	179	env->regs[R_EBP] = EBP;
	180	#endif
	181	#ifdef reg_ESI
	182	env->regs[R_ESI] = ESI;
	183	#endif
	184	#ifdef reg_EDI
	185	env->regs[R_EDI] = EDI;
	186	#endif
	187	env->exception_index = exception_index;
b56dad1c	188	env->error_code = error_code;
9de5e440 FB	189	longjmp(env->jmp_env, 1);
	190	}
	191
b56dad1c FB	192	/* short cut if error_code is 0 or not present */
	193	void raise_exception(int exception_index)
	194	{
	195	raise_exception_err(exception_index, 0);
	196	}
	197
7d13299d FB	198	void cpu_x86_tblocks_init(void)
	199	{
	200	if (!code_gen_ptr) {
	201	code_gen_ptr = code_gen_buffer;
	202	}
	203	}
	204
	205	/* flush all the translation blocks */
	206	static void tb_flush(void)
	207	{
	208	int i;
	209	#ifdef DEBUG_FLUSH
	210	printf("gemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d\n",
	211	code_gen_ptr - code_gen_buffer,
	212	nb_tbs,
	213	(code_gen_ptr - code_gen_buffer) / nb_tbs);
	214	#endif
	215	nb_tbs = 0;
	216	for(i = 0;i < CODE_GEN_HASH_SIZE; i++)
	217	tb_hash[i] = NULL;
	218	code_gen_ptr = code_gen_buffer;
	219	/* XXX: flush processor icache at this point */
	220	}
	221
	222	/* find a translation block in the translation cache. If not found,
9de5e440 FB	223	return NULL and the pointer to the last element of the list in pptb */
	224	static inline TranslationBlock tb_find(TranslationBlock **pptb,
	225	unsigned long pc,
	226	unsigned long cs_base,
	227	unsigned int flags)
7d13299d FB	228	{
	229	TranslationBlock *ptb, tb;
	230	unsigned int h;
	231
	232	h = pc & (CODE_GEN_HASH_SIZE - 1);
	233	ptb = &tb_hash[h];
b56dad1c FB	234	#if 0
	235	/* XXX: hack to handle 16 bit modyfing code */
	236	if (flags & (1 << GEN_FLAG_CODE32_SHIFT))
	237	#endif
	238	for(;;) {
	239	tb = *ptb;
	240	if (!tb)
	241	break;
	242	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
7d13299d	243	return tb;
b56dad1c FB	244	ptb = &tb->hash_next;
b56dad1c FB	245	}
9de5e440 FB	246	*pptb = ptb;
	247	return NULL;
	248	}
	249
	250	/* allocate a new translation block. flush the translation buffer if
	251	too many translation blocks or too much generated code */
	252	static inline TranslationBlock *tb_alloc(void)
	253	{
	254	TranslationBlock *tb;
7d13299d FB	255	if (nb_tbs >= CODE_GEN_MAX_BLOCKS \|\|
	256	(code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE)
	257	tb_flush();
	258	tb = &tbs[nb_tbs++];
7d13299d FB	259	return tb;
	260	}
	261
	262	int cpu_x86_exec(CPUX86State *env1)
	263	{
	264	int saved_T0, saved_T1, saved_A0;
	265	CPUX86State *saved_env;
04369ff2 FB	266	#ifdef reg_EAX
	267	int saved_EAX;
	268	#endif
	269	#ifdef reg_ECX
	270	int saved_ECX;
	271	#endif
	272	#ifdef reg_EDX
	273	int saved_EDX;
	274	#endif
	275	#ifdef reg_EBX
	276	int saved_EBX;
	277	#endif
	278	#ifdef reg_ESP
	279	int saved_ESP;
	280	#endif
	281	#ifdef reg_EBP
	282	int saved_EBP;
	283	#endif
	284	#ifdef reg_ESI
	285	int saved_ESI;
	286	#endif
	287	#ifdef reg_EDI
	288	int saved_EDI;
	289	#endif
7d13299d FB	290	int code_gen_size, ret;
7d13299d FB	291	void (*gen_func)(void);
9de5e440	292	TranslationBlock tb, *ptb;
dab2ed99	293	uint8_t tc_ptr, cs_base, *pc;
6dbad63e FB	294	unsigned int flags;
6dbad63e FB	295
7d13299d FB	296	/* first we save global registers */
	297	saved_T0 = T0;
	298	saved_T1 = T1;
	299	saved_A0 = A0;
	300	saved_env = env;
	301	env = env1;
04369ff2 FB	302	#ifdef reg_EAX
	303	saved_EAX = EAX;
	304	EAX = env->regs[R_EAX];
	305	#endif
	306	#ifdef reg_ECX
	307	saved_ECX = ECX;
	308	ECX = env->regs[R_ECX];
	309	#endif
	310	#ifdef reg_EDX
	311	saved_EDX = EDX;
	312	EDX = env->regs[R_EDX];
	313	#endif
	314	#ifdef reg_EBX
	315	saved_EBX = EBX;
	316	EBX = env->regs[R_EBX];
	317	#endif
	318	#ifdef reg_ESP
	319	saved_ESP = ESP;
	320	ESP = env->regs[R_ESP];
	321	#endif
	322	#ifdef reg_EBP
	323	saved_EBP = EBP;
	324	EBP = env->regs[R_EBP];
	325	#endif
	326	#ifdef reg_ESI
	327	saved_ESI = ESI;
	328	ESI = env->regs[R_ESI];
	329	#endif
	330	#ifdef reg_EDI
	331	saved_EDI = EDI;
	332	EDI = env->regs[R_EDI];
	333	#endif
7d13299d	334
9de5e440	335	/* put eflags in CPU temporary format */
fc2b4c48 FB	336	CC_SRC = env->eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
fc2b4c48 FB	337	DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440	338	CC_OP = CC_OP_EFLAGS;
fc2b4c48	339	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
9de5e440	340	env->interrupt_request = 0;
9d27abd9	341
7d13299d FB	342	/* prepare setjmp context for exception handling */
	343	if (setjmp(env->jmp_env) == 0) {
	344	for(;;) {
9de5e440 FB	345	if (env->interrupt_request) {
	346	raise_exception(EXCP_INTERRUPT);
	347	}
7d13299d FB	348	#ifdef DEBUG_EXEC
7d13299d FB	349	if (loglevel) {
9d27abd9 FB	350	/* XXX: save all volatile state in cpu state */
	351	/* restore flags in standard format */
	352	env->regs[R_EAX] = EAX;
	353	env->regs[R_EBX] = EBX;
	354	env->regs[R_ECX] = ECX;
	355	env->regs[R_EDX] = EDX;
	356	env->regs[R_ESI] = ESI;
	357	env->regs[R_EDI] = EDI;
	358	env->regs[R_EBP] = EBP;
	359	env->regs[R_ESP] = ESP;
	360	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
	361	cpu_x86_dump_state(env, logfile, 0);
	362	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
7d13299d FB	363	}
7d13299d FB	364	#endif
6dbad63e FB	365	/* we compute the CPU state. We assume it will not
	366	change during the whole generated block. */
	367	flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
dab2ed99	368	flags \|= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
6dbad63e FB	369	flags \|= (((unsigned long)env->seg_cache[R_DS].base \|
	370	(unsigned long)env->seg_cache[R_ES].base \|
	371	(unsigned long)env->seg_cache[R_SS].base) != 0) <<
	372	GEN_FLAG_ADDSEG_SHIFT;
9d27abd9 FB	373	if (!(env->eflags & VM_MASK)) {
	374	flags \|= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
	375	} else {
	376	/* NOTE: a dummy CPL is kept */
	377	flags \|= (1 << GEN_FLAG_VM_SHIFT);
	378	flags \|= (3 << GEN_FLAG_CPL_SHIFT);
	379	}
b56dad1c	380	flags \|= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT);
cabb4d61	381	flags \|= (env->eflags & TF_MASK) << (GEN_FLAG_TF_SHIFT - 8);
dab2ed99 FB	382	cs_base = env->seg_cache[R_CS].base;
dab2ed99 FB	383	pc = cs_base + env->eip;
9de5e440 FB	384	tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
	385	flags);
	386	if (!tb) {
7d13299d	387	/* if no translated code available, then translate it now */
1b6b029e FB	388	/* XXX: very inefficient: we lock all the cpus when
	389	generating code */
	390	cpu_lock();
7d13299d	391	tc_ptr = code_gen_ptr;
9de5e440 FB	392	ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE,
	393	&code_gen_size, pc, cs_base, flags);
	394	/* if invalid instruction, signal it */
	395	if (ret != 0) {
	396	cpu_unlock();
	397	raise_exception(EXCP06_ILLOP);
	398	}
	399	tb = tb_alloc();
	400	*ptb = tb;
	401	tb->pc = (unsigned long)pc;
	402	tb->cs_base = (unsigned long)cs_base;
	403	tb->flags = flags;
7d13299d	404	tb->tc_ptr = tc_ptr;
9de5e440	405	tb->hash_next = NULL;
7d13299d	406	code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
1b6b029e	407	cpu_unlock();
7d13299d	408	}
9d27abd9	409	#ifdef DEBUG_EXEC
956034d7 FB	410	if (loglevel) {
	411	fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
	412	(long)tb->tc_ptr, (long)tb->pc,
	413	lookup_symbol((void *)tb->pc));
956034d7	414	}
9d27abd9	415	#endif
7d13299d	416	/* execute the generated code */
9de5e440	417	tc_ptr = tb->tc_ptr;
7d13299d	418	gen_func = (void *)tc_ptr;
ae228531 FB	419	#ifdef __sparc__
	420	__asm__ __volatile__("call %0\n\t"
	421	" mov %%o7,%%i0"
	422	: /* no outputs */
	423	: "r" (gen_func)
	424	: "i0", "i1", "i2", "i3", "i4", "i5");
	425	#else
7d13299d	426	gen_func();
ae228531	427	#endif
7d13299d FB	428	}
	429	}
	430	ret = env->exception_index;
	431
9de5e440	432	/* restore flags in standard format */
fc2b4c48	433	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
9de5e440	434
7d13299d	435	/* restore global registers */
04369ff2 FB	436	#ifdef reg_EAX
	437	EAX = saved_EAX;
	438	#endif
	439	#ifdef reg_ECX
	440	ECX = saved_ECX;
	441	#endif
	442	#ifdef reg_EDX
	443	EDX = saved_EDX;
	444	#endif
	445	#ifdef reg_EBX
	446	EBX = saved_EBX;
	447	#endif
	448	#ifdef reg_ESP
	449	ESP = saved_ESP;
	450	#endif
	451	#ifdef reg_EBP
	452	EBP = saved_EBP;
	453	#endif
	454	#ifdef reg_ESI
	455	ESI = saved_ESI;
	456	#endif
	457	#ifdef reg_EDI
	458	EDI = saved_EDI;
	459	#endif
7d13299d FB	460	T0 = saved_T0;
	461	T1 = saved_T1;
	462	A0 = saved_A0;
	463	env = saved_env;
	464	return ret;
	465	}
6dbad63e	466
9de5e440 FB	467	void cpu_x86_interrupt(CPUX86State *s)
	468	{
	469	s->interrupt_request = 1;
	470	}
	471
	472
6dbad63e FB	473	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
	474	{
	475	CPUX86State *saved_env;
	476
	477	saved_env = env;
	478	env = s;
	479	load_seg(seg_reg, selector);
	480	env = saved_env;
	481	}
9de5e440 FB	482
	483	#undef EAX
	484	#undef ECX
	485	#undef EDX
	486	#undef EBX
	487	#undef ESP
	488	#undef EBP
	489	#undef ESI
	490	#undef EDI
	491	#undef EIP
	492	#include <signal.h>
	493	#include <sys/ucontext.h>
	494
b56dad1c FB	495	/* 'pc' is the host PC at which the exception was raised. 'address' is
b56dad1c FB	496	the effective address of the memory exception */
9de5e440	497	static inline int handle_cpu_signal(unsigned long pc,
b56dad1c	498	unsigned long address,
9de5e440 FB	499	sigset_t *old_set)
	500	{
	501	#ifdef DEBUG_SIGNAL
	502	printf("gemu: SIGSEGV pc=0x%08lx oldset=0x%08lx\n",
	503	pc, (unsigned long )old_set);
	504	#endif
	505	if (pc >= (unsigned long)code_gen_buffer &&
	506	pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
	507	/* the PC is inside the translated code. It means that we have
	508	a virtual CPU fault */
	509	/* we restore the process signal mask as the sigreturn should
	510	do it */
	511	sigprocmask(SIG_SETMASK, old_set, NULL);
	512	/* XXX: need to compute virtual pc position by retranslating
	513	code. The rest of the CPU state should be correct. */
b56dad1c FB	514	env->cr2 = address;
	515	/* XXX: more precise exception code */
	516	raise_exception_err(EXCP0E_PAGE, 4);
9de5e440 FB	517	/* never comes here */
	518	return 1;
	519	} else {
	520	return 0;
	521	}
	522	}
	523
	524	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
	525	void *puc)
	526	{
	527	#if defined(__i386__)
	528	struct ucontext *uc = puc;
	529	unsigned long pc;
	530	sigset_t *pold_set;
	531
d691f669 FB	532	#ifndef REG_EIP
	533	/* for glibc 2.1 */
	534	#define REG_EIP EIP
	535	#endif
fc2b4c48	536	pc = uc->uc_mcontext.gregs[REG_EIP];
9de5e440	537	pold_set = &uc->uc_sigmask;
b56dad1c	538	return handle_cpu_signal(pc, (unsigned long)info->si_addr, pold_set);
9de5e440 FB	539	#else
	540	#warning No CPU specific signal handler: cannot handle target SIGSEGV events
	541	return 0;
	542	#endif
	543	}