[mirror_qemu.git] / exec-i386.c

/*
 *  i386 emulator main execution loop
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "exec-i386.h"
#include "disas.h"

//#define DEBUG_EXEC
//#define DEBUG_SIGNAL

/* main execution loop */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

void cpu_loop_exit(void)
{
    /* NOTE: the register at this point must be saved by hand because
       longjmp restore them */
#ifdef __sparc__
	/* We have to stay in the same register window as our caller,
	 * thus this trick.
	 */
	__asm__ __volatile__("restore\n\t"
			     "mov\t%o0, %i0");
#endif
#ifdef reg_EAX
    env->regs[R_EAX] = EAX;
#endif
#ifdef reg_ECX
    env->regs[R_ECX] = ECX;
#endif
#ifdef reg_EDX
    env->regs[R_EDX] = EDX;
#endif
#ifdef reg_EBX
    env->regs[R_EBX] = EBX;
#endif
#ifdef reg_ESP
    env->regs[R_ESP] = ESP;
#endif
#ifdef reg_EBP
    env->regs[R_EBP] = EBP;
#endif
#ifdef reg_ESI
    env->regs[R_ESI] = ESI;
#endif
#ifdef reg_EDI
    env->regs[R_EDI] = EDI;
#endif
    longjmp(env->jmp_env, 1);
}

int cpu_x86_exec(CPUX86State *env1)
{
    int saved_T0, saved_T1, saved_A0;
    CPUX86State *saved_env;
#ifdef reg_EAX
    int saved_EAX;
#endif
#ifdef reg_ECX
    int saved_ECX;
#endif
#ifdef reg_EDX
    int saved_EDX;
#endif
#ifdef reg_EBX
    int saved_EBX;
#endif
#ifdef reg_ESP
    int saved_ESP;
#endif
#ifdef reg_EBP
    int saved_EBP;
#endif
#ifdef reg_ESI
    int saved_ESI;
#endif
#ifdef reg_EDI
    int saved_EDI;
#endif
    int code_gen_size, ret;
    void (*gen_func)(void);
    TranslationBlock *tb, **ptb;
    uint8_t *tc_ptr, *cs_base, *pc;
    unsigned int flags;
    
    /* first we save global registers */
    saved_T0 = T0;
    saved_T1 = T1;
    saved_A0 = A0;
    saved_env = env;
    env = env1;
#ifdef reg_EAX
    saved_EAX = EAX;
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    saved_ECX = ECX;
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    saved_EDX = EDX;
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    saved_EBX = EBX;
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    saved_ESP = ESP;
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    saved_EBP = EBP;
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    saved_ESI = ESI;
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    saved_EDI = EDI;
    EDI = env->regs[R_EDI];
#endif
    
    /* put eflags in CPU temporary format */
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
    CC_OP = CC_OP_EFLAGS;
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    env->interrupt_request = 0;

    /* prepare setjmp context for exception handling */
    if (setjmp(env->jmp_env) == 0) {
        T0 = 0; /* force lookup of first TB */
        for(;;) {
            if (env->interrupt_request) {
                env->exception_index = EXCP_INTERRUPT;
                cpu_loop_exit();
            }
#ifdef DEBUG_EXEC
            if (loglevel) {
                /* XXX: save all volatile state in cpu state */
                /* restore flags in standard format */
                env->regs[R_EAX] = EAX;
                env->regs[R_EBX] = EBX;
                env->regs[R_ECX] = ECX;
                env->regs[R_EDX] = EDX;
                env->regs[R_ESI] = ESI;
                env->regs[R_EDI] = EDI;
                env->regs[R_EBP] = EBP;
                env->regs[R_ESP] = ESP;
                env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
                cpu_x86_dump_state(env, logfile, 0);
                env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
            }
#endif
            /* we compute the CPU state. We assume it will not
               change during the whole generated block. */
            flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
            flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
            flags |= (((unsigned long)env->seg_cache[R_DS].base | 
                       (unsigned long)env->seg_cache[R_ES].base |
                       (unsigned long)env->seg_cache[R_SS].base) != 0) << 
                GEN_FLAG_ADDSEG_SHIFT;
            if (!(env->eflags & VM_MASK)) {
                flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
            } else {
                /* NOTE: a dummy CPL is kept */
                flags |= (1 << GEN_FLAG_VM_SHIFT);
                flags |= (3 << GEN_FLAG_CPL_SHIFT);
            }
            flags |= (env->eflags & (IOPL_MASK | TF_MASK));
            cs_base = env->seg_cache[R_CS].base;
            pc = cs_base + env->eip;
            tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, 
                         flags);
            if (!tb) {
                spin_lock(&tb_lock);
                /* if no translated code available, then translate it now */
                tb = tb_alloc((unsigned long)pc);
                if (!tb) {
                    /* flush must be done */
                    tb_flush();
                    /* cannot fail at this point */
                    tb = tb_alloc((unsigned long)pc);
                    /* don't forget to invalidate previous TB info */
                    ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
                    T0 = 0;
                }
                tc_ptr = code_gen_ptr;
                tb->tc_ptr = tc_ptr;
                tb->cs_base = (unsigned long)cs_base;
                tb->flags = flags;
                ret = cpu_x86_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
                /* if invalid instruction, signal it */
                if (ret != 0) {
                    /* NOTE: the tb is allocated but not linked, so we
                       can leave it */
                    spin_unlock(&tb_lock);
                    raise_exception(EXCP06_ILLOP);
                }
                *ptb = tb;
                tb->hash_next = NULL;
                tb_link(tb);
                code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
                spin_unlock(&tb_lock);
            }
#ifdef DEBUG_EXEC
	    if (loglevel) {
		fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
			(long)tb->tc_ptr, (long)tb->pc,
			lookup_symbol((void *)tb->pc));
	    }
#endif
            /* see if we can patch the calling TB */
            if (T0 != 0 && !(env->eflags & TF_MASK)) {
                spin_lock(&tb_lock);
                tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
                spin_unlock(&tb_lock);
            }

            tc_ptr = tb->tc_ptr;

            /* execute the generated code */
            gen_func = (void *)tc_ptr;
#ifdef __sparc__
	    __asm__ __volatile__("call	%0\n\t"
				 " mov	%%o7,%%i0"
				 : /* no outputs */
				 : "r" (gen_func) 
				 : "i0", "i1", "i2", "i3", "i4", "i5");
#else
            gen_func();
#endif
        }
    }
    ret = env->exception_index;

    /* restore flags in standard format */
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);

    /* restore global registers */
#ifdef reg_EAX
    EAX = saved_EAX;
#endif
#ifdef reg_ECX
    ECX = saved_ECX;
#endif
#ifdef reg_EDX
    EDX = saved_EDX;
#endif
#ifdef reg_EBX
    EBX = saved_EBX;
#endif
#ifdef reg_ESP
    ESP = saved_ESP;
#endif
#ifdef reg_EBP
    EBP = saved_EBP;
#endif
#ifdef reg_ESI
    ESI = saved_ESI;
#endif
#ifdef reg_EDI
    EDI = saved_EDI;
#endif
    T0 = saved_T0;
    T1 = saved_T1;
    A0 = saved_A0;
    env = saved_env;
    return ret;
}

void cpu_x86_interrupt(CPUX86State *s)
{
    s->interrupt_request = 1;
}


void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    if (env->eflags & VM_MASK) {
        SegmentCache *sc;
        selector &= 0xffff;
        sc = &env->seg_cache[seg_reg];
        /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
           so we must load them here */
        sc->base = (void *)(selector << 4);
        sc->limit = 0xffff;
        sc->seg_32bit = 0;
        env->segs[seg_reg] = selector;
    } else {
        load_seg(seg_reg, selector, 0);
    }
    env = saved_env;
}

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#include <sys/ucontext.h>

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    TranslationBlock *tb;
    int ret;
    uint32_t found_pc;
    
#if defined(DEBUG_SIGNAL)
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n", 
           pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && page_unprotect(address)) {
        return 1;
    }
    tb = tb_find_pc(pc);
    if (tb) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        ret = cpu_x86_search_pc(tb, &found_pc, pc);
        if (ret < 0)
            return 0;
        env->eip = found_pc - tb->cs_base;
        env->cr2 = address;
        /* we restore the process signal mask as the sigreturn should
           do it (XXX: use sigsetjmp) */
        sigprocmask(SIG_SETMASK, old_set, NULL);
        raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
        /* never comes here */
        return 1;
    } else {
        return 0;
    }
}

#if defined(__i386__)

int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = uc->uc_mcontext.gregs[REG_EIP];
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? 
                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                             &uc->uc_sigmask);
}

#elif defined(__powerpc)

int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    struct pt_regs *regs = uc->uc_mcontext.regs;
    unsigned long pc;
    int is_write;

    pc = regs->nip;
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (regs->dsisr & 0x00800000)
        is_write = 1;
#else
    if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
        is_write = 1;
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}

#else

#error CPU specific signal handler needed

#endif
Commit	Line	Data
7d13299d FB	1	/*
	2	* i386 emulator main execution loop
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
3ef693a0 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
7d13299d	10	*
3ef693a0 FB	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
7d13299d	15	*
3ef693a0 FB	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d FB	19	*/
7d13299d FB	20	#include "exec-i386.h"
956034d7	21	#include "disas.h"
7d13299d	22
dc99065b	23	//#define DEBUG_EXEC
9de5e440	24	//#define DEBUG_SIGNAL
7d13299d FB	25
	26	/* main execution loop */
	27
1b6b029e FB	28	/* thread support */
1b6b029e FB	29
25eb4484	30	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
1b6b029e FB	31
	32	void cpu_lock(void)
	33	{
25eb4484	34	spin_lock(&global_cpu_lock);
1b6b029e FB	35	}
	36
	37	void cpu_unlock(void)
	38	{
25eb4484	39	spin_unlock(&global_cpu_lock);
1b6b029e FB	40	}
1b6b029e FB	41
a513fe19	42	void cpu_loop_exit(void)
9de5e440 FB	43	{
	44	/* NOTE: the register at this point must be saved by hand because
	45	longjmp restore them */
ae228531 FB	46	#ifdef __sparc__
	47	/* We have to stay in the same register window as our caller,
	48	* thus this trick.
	49	*/
	50	__asm__ __volatile__("restore\n\t"
	51	"mov\t%o0, %i0");
	52	#endif
9de5e440 FB	53	#ifdef reg_EAX
	54	env->regs[R_EAX] = EAX;
	55	#endif
	56	#ifdef reg_ECX
	57	env->regs[R_ECX] = ECX;
	58	#endif
	59	#ifdef reg_EDX
	60	env->regs[R_EDX] = EDX;
	61	#endif
	62	#ifdef reg_EBX
	63	env->regs[R_EBX] = EBX;
	64	#endif
	65	#ifdef reg_ESP
	66	env->regs[R_ESP] = ESP;
	67	#endif
	68	#ifdef reg_EBP
	69	env->regs[R_EBP] = EBP;
	70	#endif
	71	#ifdef reg_ESI
	72	env->regs[R_ESI] = ESI;
	73	#endif
	74	#ifdef reg_EDI
	75	env->regs[R_EDI] = EDI;
	76	#endif
9de5e440 FB	77	longjmp(env->jmp_env, 1);
	78	}
	79
7d13299d FB	80	int cpu_x86_exec(CPUX86State *env1)
	81	{
	82	int saved_T0, saved_T1, saved_A0;
	83	CPUX86State *saved_env;
04369ff2 FB	84	#ifdef reg_EAX
	85	int saved_EAX;
	86	#endif
	87	#ifdef reg_ECX
	88	int saved_ECX;
	89	#endif
	90	#ifdef reg_EDX
	91	int saved_EDX;
	92	#endif
	93	#ifdef reg_EBX
	94	int saved_EBX;
	95	#endif
	96	#ifdef reg_ESP
	97	int saved_ESP;
	98	#endif
	99	#ifdef reg_EBP
	100	int saved_EBP;
	101	#endif
	102	#ifdef reg_ESI
	103	int saved_ESI;
	104	#endif
	105	#ifdef reg_EDI
	106	int saved_EDI;
	107	#endif
a513fe19	108	int code_gen_size, ret;
7d13299d	109	void (*gen_func)(void);
9de5e440	110	TranslationBlock tb, *ptb;
dab2ed99	111	uint8_t tc_ptr, cs_base, *pc;
6dbad63e	112	unsigned int flags;
d4e8164f	113
7d13299d FB	114	/* first we save global registers */
	115	saved_T0 = T0;
	116	saved_T1 = T1;
	117	saved_A0 = A0;
	118	saved_env = env;
	119	env = env1;
04369ff2 FB	120	#ifdef reg_EAX
	121	saved_EAX = EAX;
	122	EAX = env->regs[R_EAX];
	123	#endif
	124	#ifdef reg_ECX
	125	saved_ECX = ECX;
	126	ECX = env->regs[R_ECX];
	127	#endif
	128	#ifdef reg_EDX
	129	saved_EDX = EDX;
	130	EDX = env->regs[R_EDX];
	131	#endif
	132	#ifdef reg_EBX
	133	saved_EBX = EBX;
	134	EBX = env->regs[R_EBX];
	135	#endif
	136	#ifdef reg_ESP
	137	saved_ESP = ESP;
	138	ESP = env->regs[R_ESP];
	139	#endif
	140	#ifdef reg_EBP
	141	saved_EBP = EBP;
	142	EBP = env->regs[R_EBP];
	143	#endif
	144	#ifdef reg_ESI
	145	saved_ESI = ESI;
	146	ESI = env->regs[R_ESI];
	147	#endif
	148	#ifdef reg_EDI
	149	saved_EDI = EDI;
	150	EDI = env->regs[R_EDI];
	151	#endif
7d13299d	152
9de5e440	153	/* put eflags in CPU temporary format */
fc2b4c48 FB	154	CC_SRC = env->eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
fc2b4c48 FB	155	DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440	156	CC_OP = CC_OP_EFLAGS;
fc2b4c48	157	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
9de5e440	158	env->interrupt_request = 0;
9d27abd9	159
7d13299d FB	160	/* prepare setjmp context for exception handling */
7d13299d FB	161	if (setjmp(env->jmp_env) == 0) {
d4e8164f	162	T0 = 0; /* force lookup of first TB */
7d13299d	163	for(;;) {
9de5e440	164	if (env->interrupt_request) {
a513fe19 FB	165	env->exception_index = EXCP_INTERRUPT;
a513fe19 FB	166	cpu_loop_exit();
9de5e440	167	}
7d13299d FB	168	#ifdef DEBUG_EXEC
7d13299d FB	169	if (loglevel) {
9d27abd9 FB	170	/* XXX: save all volatile state in cpu state */
	171	/* restore flags in standard format */
	172	env->regs[R_EAX] = EAX;
	173	env->regs[R_EBX] = EBX;
	174	env->regs[R_ECX] = ECX;
	175	env->regs[R_EDX] = EDX;
	176	env->regs[R_ESI] = ESI;
	177	env->regs[R_EDI] = EDI;
	178	env->regs[R_EBP] = EBP;
	179	env->regs[R_ESP] = ESP;
	180	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
	181	cpu_x86_dump_state(env, logfile, 0);
	182	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
7d13299d FB	183	}
7d13299d FB	184	#endif
6dbad63e FB	185	/* we compute the CPU state. We assume it will not
	186	change during the whole generated block. */
	187	flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
dab2ed99	188	flags \|= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
6dbad63e FB	189	flags \|= (((unsigned long)env->seg_cache[R_DS].base \|
	190	(unsigned long)env->seg_cache[R_ES].base \|
	191	(unsigned long)env->seg_cache[R_SS].base) != 0) <<
	192	GEN_FLAG_ADDSEG_SHIFT;
9d27abd9 FB	193	if (!(env->eflags & VM_MASK)) {
	194	flags \|= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
	195	} else {
	196	/* NOTE: a dummy CPL is kept */
	197	flags \|= (1 << GEN_FLAG_VM_SHIFT);
	198	flags \|= (3 << GEN_FLAG_CPL_SHIFT);
	199	}
cf25629d	200	flags \|= (env->eflags & (IOPL_MASK \| TF_MASK));
dab2ed99 FB	201	cs_base = env->seg_cache[R_CS].base;
dab2ed99 FB	202	pc = cs_base + env->eip;
9de5e440 FB	203	tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
	204	flags);
	205	if (!tb) {
cf25629d	206	spin_lock(&tb_lock);
7d13299d	207	/* if no translated code available, then translate it now */
d4e8164f FB	208	tb = tb_alloc((unsigned long)pc);
	209	if (!tb) {
	210	/* flush must be done */
	211	tb_flush();
	212	/* cannot fail at this point */
	213	tb = tb_alloc((unsigned long)pc);
	214	/* don't forget to invalidate previous TB info */
	215	ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
	216	T0 = 0;
	217	}
7d13299d	218	tc_ptr = code_gen_ptr;
d4e8164f	219	tb->tc_ptr = tc_ptr;
a513fe19 FB	220	tb->cs_base = (unsigned long)cs_base;
	221	tb->flags = flags;
	222	ret = cpu_x86_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
9de5e440 FB	223	/* if invalid instruction, signal it */
9de5e440 FB	224	if (ret != 0) {
d4e8164f FB	225	/* NOTE: the tb is allocated but not linked, so we
d4e8164f FB	226	can leave it */
25eb4484	227	spin_unlock(&tb_lock);
9de5e440 FB	228	raise_exception(EXCP06_ILLOP);
9de5e440 FB	229	}
9de5e440	230	*ptb = tb;
9de5e440	231	tb->hash_next = NULL;
d4e8164f	232	tb_link(tb);
7d13299d	233	code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
cf25629d	234	spin_unlock(&tb_lock);
7d13299d	235	}
9d27abd9	236	#ifdef DEBUG_EXEC
956034d7 FB	237	if (loglevel) {
	238	fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
	239	(long)tb->tc_ptr, (long)tb->pc,
	240	lookup_symbol((void *)tb->pc));
956034d7	241	}
9d27abd9	242	#endif
d4e8164f FB	243	/* see if we can patch the calling TB */
d4e8164f FB	244	if (T0 != 0 && !(env->eflags & TF_MASK)) {
cf25629d	245	spin_lock(&tb_lock);
d4e8164f	246	tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
cf25629d	247	spin_unlock(&tb_lock);
d4e8164f	248	}
cf25629d	249
9de5e440	250	tc_ptr = tb->tc_ptr;
d4e8164f FB	251
d4e8164f FB	252	/* execute the generated code */
7d13299d	253	gen_func = (void *)tc_ptr;
ae228531 FB	254	#ifdef __sparc__
	255	__asm__ __volatile__("call %0\n\t"
	256	" mov %%o7,%%i0"
	257	: /* no outputs */
d4e8164f	258	: "r" (gen_func)
ae228531 FB	259	: "i0", "i1", "i2", "i3", "i4", "i5");
ae228531 FB	260	#else
7d13299d	261	gen_func();
ae228531	262	#endif
7d13299d FB	263	}
	264	}
	265	ret = env->exception_index;
	266
9de5e440	267	/* restore flags in standard format */
fc2b4c48	268	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
9de5e440	269
7d13299d	270	/* restore global registers */
04369ff2 FB	271	#ifdef reg_EAX
	272	EAX = saved_EAX;
	273	#endif
	274	#ifdef reg_ECX
	275	ECX = saved_ECX;
	276	#endif
	277	#ifdef reg_EDX
	278	EDX = saved_EDX;
	279	#endif
	280	#ifdef reg_EBX
	281	EBX = saved_EBX;
	282	#endif
	283	#ifdef reg_ESP
	284	ESP = saved_ESP;
	285	#endif
	286	#ifdef reg_EBP
	287	EBP = saved_EBP;
	288	#endif
	289	#ifdef reg_ESI
	290	ESI = saved_ESI;
	291	#endif
	292	#ifdef reg_EDI
	293	EDI = saved_EDI;
	294	#endif
7d13299d FB	295	T0 = saved_T0;
	296	T1 = saved_T1;
	297	A0 = saved_A0;
	298	env = saved_env;
	299	return ret;
	300	}
6dbad63e	301
9de5e440 FB	302	void cpu_x86_interrupt(CPUX86State *s)
	303	{
	304	s->interrupt_request = 1;
	305	}
	306
	307
6dbad63e FB	308	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
	309	{
	310	CPUX86State *saved_env;
	311
	312	saved_env = env;
	313	env = s;
a513fe19 FB	314	if (env->eflags & VM_MASK) {
	315	SegmentCache *sc;
	316	selector &= 0xffff;
	317	sc = &env->seg_cache[seg_reg];
	318	/* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
	319	so we must load them here */
	320	sc->base = (void *)(selector << 4);
	321	sc->limit = 0xffff;
	322	sc->seg_32bit = 0;
	323	env->segs[seg_reg] = selector;
	324	} else {
	325	load_seg(seg_reg, selector, 0);
	326	}
6dbad63e FB	327	env = saved_env;
6dbad63e FB	328	}
9de5e440 FB	329
	330	#undef EAX
	331	#undef ECX
	332	#undef EDX
	333	#undef EBX
	334	#undef ESP
	335	#undef EBP
	336	#undef ESI
	337	#undef EDI
	338	#undef EIP
	339	#include <signal.h>
	340	#include <sys/ucontext.h>
	341
b56dad1c	342	/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6 FB	343	the effective address of the memory exception. 'is_write' is 1 if a
	344	write caused the exception and otherwise 0'. 'old_set' is the
	345	signal set which should be restored */
2b413144 FB	346	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
2b413144 FB	347	int is_write, sigset_t *old_set)
9de5e440	348	{
a513fe19 FB	349	TranslationBlock *tb;
	350	int ret;
	351	uint32_t found_pc;
	352
fd6ce8f6 FB	353	#if defined(DEBUG_SIGNAL)
	354	printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
	355	pc, address, is_write, (unsigned long )old_set);
9de5e440	356	#endif
25eb4484	357	/* XXX: locking issue */
fd6ce8f6	358	if (is_write && page_unprotect(address)) {
fd6ce8f6 FB	359	return 1;
fd6ce8f6 FB	360	}
a513fe19 FB	361	tb = tb_find_pc(pc);
a513fe19 FB	362	if (tb) {
9de5e440 FB	363	/* the PC is inside the translated code. It means that we have
9de5e440 FB	364	a virtual CPU fault */
a513fe19 FB	365	ret = cpu_x86_search_pc(tb, &found_pc, pc);
	366	if (ret < 0)
	367	return 0;
	368	env->eip = found_pc - tb->cs_base;
	369	env->cr2 = address;
9de5e440	370	/* we restore the process signal mask as the sigreturn should
a513fe19	371	do it (XXX: use sigsetjmp) */
9de5e440	372	sigprocmask(SIG_SETMASK, old_set, NULL);
fd6ce8f6	373	raise_exception_err(EXCP0E_PAGE, 4 \| (is_write << 1));
9de5e440 FB	374	/* never comes here */
	375	return 1;
	376	} else {
	377	return 0;
	378	}
	379	}
	380
2b413144 FB	381	#if defined(__i386__)
2b413144 FB	382
9de5e440 FB	383	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
	384	void *puc)
	385	{
9de5e440 FB	386	struct ucontext *uc = puc;
9de5e440 FB	387	unsigned long pc;
9de5e440	388
d691f669 FB	389	#ifndef REG_EIP
d691f669 FB	390	/* for glibc 2.1 */
fd6ce8f6 FB	391	#define REG_EIP EIP
	392	#define REG_ERR ERR
	393	#define REG_TRAPNO TRAPNO
d691f669	394	#endif
fc2b4c48	395	pc = uc->uc_mcontext.gregs[REG_EIP];
fd6ce8f6 FB	396	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	397	uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
	398	(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
2b413144 FB	399	&uc->uc_sigmask);
	400	}
	401
25eb4484	402	#elif defined(__powerpc)
2b413144 FB	403
	404	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
	405	void *puc)
	406	{
25eb4484 FB	407	struct ucontext *uc = puc;
	408	struct pt_regs *regs = uc->uc_mcontext.regs;
	409	unsigned long pc;
25eb4484 FB	410	int is_write;
	411
	412	pc = regs->nip;
25eb4484 FB	413	is_write = 0;
	414	#if 0
	415	/* ppc 4xx case */
	416	if (regs->dsisr & 0x00800000)
	417	is_write = 1;
	418	#else
	419	if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
	420	is_write = 1;
	421	#endif
	422	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
2b413144 FB	423	is_write, &uc->uc_sigmask);
	424	}
	425
9de5e440	426	#else
2b413144	427
25eb4484	428	#error CPU specific signal handler needed
2b413144	429
9de5e440	430	#endif